Patent Application
20170092790
Semiconductor devices, for example photovoltaic (PV) cells among others, are well known electronic devices. In one example, photovoltaic (PV) cells, commonly known as solar cells, are devices for conversion of solar radiation into electrical energy. Generally, solar radiation impinging on the surface of, and entering into, the substrate of a solar cell creates electron and hole pairs in the bulk of the substrate. The electron and hole pairs migrate to p-doped and n-doped regions in the substrate, thereby creating a voltage differential between the doped regions. The doped regions are connected to the conductive regions on the solar cell to direct an electrical current from the cell to an external circuit. When PV cells are combined in an array such as a PV module, the electrical energy collected from all of the PV cells can be combined in series and parallel arrangements to provide power with a certain voltage and current.
Efficiency in producing semiconductor devices is directly related to the cost effectiveness of such semiconductor devices. Accordingly, techniques for increasing the efficiency of semiconductor devices, or techniques for increasing the efficiency in the manufacture of semiconductor devices, are generally desirable. Some embodiments of the present disclosure allow for increased semiconductor devices manufacture efficiency by providing novel processes for fabricating semiconductor devices structures.
The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter of the application or uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.
This specification includes references to “one embodiment” or “an embodiment.” The appearances of the phrases “in one embodiment” or “in an embodiment” do not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.
Terminology. The following paragraphs provide definitions and/or context for terms found in this disclosure (including the appended claims):
“Comprising.” This term is open-ended. As used in the appended claims, this term does not foreclose additional structure or steps.
“Configured To.” Various units or components may be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that the units/components include structure that performs those task or tasks during operation. As such, the unit/component can be said to be configured to perform the task even when the specified unit/component is not currently operational (e.g., is not on/active). Reciting that a unit/circuit/component is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, sixth paragraph, for that unit/component.
“First,” “Second,” etc. As used herein, these terms are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, reference to a “first” conductive strip does not necessarily imply that this conductive strip is the first conductive strip in a sequence; instead the term “first” is used to differentiate this conductive strip from another conductive strip (e.g., a “second” conductive strip).
“Based On.” As used herein, this term is used to describe one or more factors that affect a determination. This term does not foreclose additional factors that may affect a determination. That is, a determination may be solely based on those factors or based, at least in part, on those factors. Consider the phrase “determine A based on B.” While B may be a factor that affects the determination of A, such a phrase does not foreclose the determination of A from also being based on C. In other instances, A may be determined based solely on B.
“Coupled”—The following description refers to elements or nodes or features being “coupled” together. As used herein, unless expressly stated otherwise, “coupled” means that one element/node/feature is directly or indirectly joined to (or directly or indirectly communicates with) another element/node/feature, and not necessarily mechanically.
“Inhibit”—As used herein, inhibit is used to describe a reducing or minimizing effect. When a component or feature is described as inhibiting an action, motion, or condition it may completely prevent the result or outcome or future state completely. Additionally, “inhibit” can also refer to a reduction or lessening of the outcome, performance, and/or effect which might otherwise occur. Accordingly, when a component, element, or feature is referred to as inhibiting a result or state, it need not completely prevent or eliminate the result or state.
In addition, certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as “upper”, “lower”, “above”, and “below” refer to directions in the drawings to which reference is made. Terms such as “front”, “back”, “rear”, “side”, “outboard”, and “inboard” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.
In the following description, numerous specific details are set forth, such as specific operations, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known techniques are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure.
This specification includes a description of an example method for manufacturing a semiconductor device, followed by example semiconductor devices formed from the described methods. In an example, the semiconductor devices can be, but are not limited to, solar cells as described in
Turning now to
Referring to
In an embodiment, a dielectric region 213 can be formed over the surface 215 of the substrate 202, as shown. In an embodiment, the dielectric region 213 can include silicon oxide and/or other oxides. In an embodiment, a contact opening 216 can be formed in the dielectric region 213 as shown and, as a result, the metal region 220 can be formed on the surface 215 of the substrate 202 within the contact opening 216. In an example, the contact opening 216 can be formed by laser ablation and/or by a mask and etch process, among others.
In an embodiment, the substrate 202 can be a silicon substrate. In some embodiments, the silicon substrate can be cleaned, polished, planarized and/or thinned or otherwise processed prior to the formation of the metal region 220. In an embodiment, the silicon substrate can be single-crystalline or a multi-crystalline silicon substrate. In an embodiment, the silicon substrate can be an N-type or a P-type silicon substrate.
In an embodiment, prior to the formation of the metal region 220, a semiconductor region can be formed in or above the substrate 202. In an example, a first semiconductor region 212 can include an N-type doped region. In one example, a second semiconductor region 214 can include a P-type doped region. In an embodiment, the first and second semiconductor regions 212, 214 can be in the substrate 202. In an embodiment, the first and second semiconductor regions 212, 214 can be formed over the substrate 202. In an example, the first and second semiconductor regions 212, 214 can be doped polysilicon regions. In an embodiment, the doped polysilicon regions can be formed over the substrate. In one embodiment, a dielectric region (e.g., a tunnel oxide) can be formed between the doped polysilicon regions and the substrate. In an embodiment, the semiconductor regions 212, 214 can be formed at the back side 206 of the semiconductor device 200, as shown in
In an embodiment, the metal region 220 can include aluminum (e.g., an aluminum region), aluminum/Si, nickel, copper, titanium, tungsten, and/or alloys thereof, among other examples. In an embodiment, the metal region 220 can be formed by blanket deposition, sputtering, by printing techniques (e.g., screen printing, ink-jet printing and/or spin coating), among other examples. In an embodiment, the metal region 220 can have a thickness 221 in a range of 50-1000 nanometers. In one embodiment, the metal region 220 can have a thickness 221 greater than 1000 nanometers (e.g., 2000 nanometers).
In an embodiment, the front side 204 of the semiconductor device 200 can be a textured surface 203 as shown in
Referring to
In some embodiments, a first conductive strip can be placed on the front side 204 and/or back side 206 of the semiconductor device 200. In an example, a first conductive strip can be placed over a first semiconductor region located on the back side of the semiconductor device 200 and/or a second conductive strip can be placed over a second semiconductor region located on the front side 204 of the semiconductor device 200. In some embodiments, a first and second metal region can be formed between the first and second conductive strips and the first and second semiconductor regions, respectively.
Referring to
In an embodiment, the bonding process of operation 106 can include applying a force 240 to the contacting portion of the conductive strip 230 to electrically connect the conductive strip 230 to the metal region 220. In an example, as shown in
In an embodiment, the bonding can include heating the contacting portion 232 of the conductive strip 230 to electrically connect the conductive strip 230 to the metal region 220. In one example, heat can be applied after, during, or before applying a force 240 to the contacting portion of the conductive strip 230. In an example, a laser can be used to heat the contacting portion of the conductive strip. In one example, a laser can be used to electrically connect the conductive strip 230 to the metal region 220. In some examples, a welding process (e.g., a laser weld process) can be used to bond the contacting portion 232 of the conductive strip 230 to the first portion 222 of the metal region 220. In one embodiment, the heating can include inductive heating and/or contacting heating.
In an embodiment, the conductive strip 230 can include a conductive adhesive disposed between the contacting portion 232 of the conductive strip and the first portion 222 of the metal region 230. In an example, the conductive adhesive can be a solder paste. In an embodiment, the bonding can include heating the conductive adhesive (e.g., solder paste) to electrically connect the conductive strip 230 to the metal region 220. In one embodiment, heating the conductive adhesive can include inductive heating and/or contacting heating.
Referring to
In some embodiments, one or more conductive contacts can instead be formed at the front side of the semiconductor device. In an example, a first conductive contact can be formed over a first semiconductor region located on the back side of the semiconductor device 200 and/or a second conductive contact can be formed over a second semiconductor region located on the front side of the semiconductor device 200.
In an example, the conductive strip 230 of
In an embodiment, a first etchant can be used to etch through the second portion 224 of the metal region 220 of
In an embodiment, the conductive contacts 234, 236 can include the conductive strip 230 and the metal region 220. In one embodiment, the conductive contacts 234, 236 can form metal contact fingers. In an embodiment, the metal contact fingers can be interdigitated.
In an embodiment, the front side 204 of the solar cell 200 can have a textured surface 203 as shown in
In an embodiment, the solar cell 200 can include a substrate 202. In an embodiment, the substrate 202 can be a silicon substrate. In some embodiments, the silicon substrate can be single-crystalline or a multi-crystalline silicon substrate. In one embodiment, the silicon substrate can be an N-type or a P-type silicon substrate.
In an embodiment, the substrate 202 can include a semiconductor region 212, 214 on the back side 206 of the solar cell 200. In an example, a first semiconductor region 212 can include an N-type doped region. In one example, a second semiconductor region 214 can include a P-type doped region. In an embodiment, the first and second semiconductor regions 212, 214 can be in the substrate 202. In an embodiment, the first and second semiconductor regions 212, 214 can be disposed over the substrate 202. In an example, the first and second semiconductor regions 212, 214 can be doped polysilicon regions. In an embodiment, the doped polysilicon regions can be disposed over the substrate 202 at the back side 206 of the solar cell 200. In one embodiment, a dielectric region (e.g., a tunnel oxide) can be disposed between the doped polysilicon regions and the substrate.
In an embodiment, conductive contacts 234, 236 can be disposed on the semiconductor regions 212, 214 at the back side 206 of the solar cell 200. In an example, a first conductive contact 234 can be disposed over the first semiconductor region 212. In one example, a second conductive contact 236 can be disposed over the second semiconductor region 214. In an example, the conductive contacts 234, 236 can be metal contact fingers. In some examples, the metal contact fingers can be interdigitated. In an embodiment, the conductive contacts 234, 236 allow for pathways for electrical current conduction from the first and second semiconductor regions 212, 214 to an external circuit. In some embodiments, the conductive contacts 220, 221 can include a metal region 220. In an embodiment, a dielectric region 213 can be disposed between the metal region 220 and the substrate 202, as shown. In one embodiment, the dielectric region 213 can include silicon oxide, among other oxides. In an embodiment, the metal region 220 can include aluminum (e.g., an aluminum region), aluminum/Si, nickel, copper, titanium, tungsten, and/or alloys thereof In an embodiment, the metal region 220 can have a thickness approximately in the range of 50-1000 nanometers.
In an embodiment, the conductive contacts 234, 236 can include a conductive strip 230. In one embodiment, the conductive strip 230 can be disposed on the metal region 220, as shown. In an embodiment, the conductive strip 224 can include copper, nickel, aluminum, iron, and/or alloys thereof In an embodiment, the conductive strip 230 can have a thickness approximately in the range of 60-1200 nanometers.
In some embodiments, the metal region 220 and the conductive strip 230 can include the same metal. In an example, the metal region 220 and the conductive strip 230 can both, respectively, include aluminum. In some examples, the metal at the first portion 222 of the metal seed region 220 and the metal of the contacting portion 232 can be substantially the same. For example, the first portion 222 of the metal region 220 and contacting portion 232 of the conductive strip 230 can be aluminum or an aluminum-containing alloy.
In one embodiment, the metal region 220 and the conductive strip 230 can be substantially different. In one example, the metal region 220 can include aluminum and the conductive strip 230 can include iron or steel. In the same example, a thermocompression process can be used to bond the conductive strip including iron or steel to the metal seed region including aluminum.
In an embodiment, another semiconductor region can be located on the front side 204 of a solar cell 200. In an example, the semiconductor region can include an N-type or P-type doped region. In an embodiment, another conductive contact can be disposed on the semiconductor region on the front side 204 of the solar cell 200. In an embodiment, the conductive contact can also include a conductive strip bonded to a metal region, where the conductive contact is located on the semiconductor region on the front side of the solar cell 200. In the same embodiment, the semiconductor device 200 can be a front contact solar cell.
With reference to
Referring to
In some embodiments, a first coated conductive strip can be placed on the front side 304 and/or back side 306 of the semiconductor device 300. In an example, a first conductive strip can be placed over a first semiconductor region located on the back side of the semiconductor device 300 and/or a second conductive strip can be placed over a second semiconductor region located on the front side 304 of the semiconductor device 300. In some embodiments, a first and second metal region can be formed between the first and second conductive strips and the first and second semiconductor regions, respectively. As discussed above, a plurality of conductive strips (e.g., first, second conductive strips) ca be used.
Referring to
Referring to
In one example, as shown, the first and second conductive contacts 334, 336 can be formed on the back side 306 of the semiconductor device 300. In some embodiments, one or more conductive contacts including a coated conductive strips can instead be formed at the front side of the semiconductor device. In an example, a first conductive contact can be formed over a first semiconductor region located on the back side of the semiconductor device 300 and/or a second conductive contact can be formed over a second semiconductor region located on the front side of the semiconductor device 300.
In an embodiment, the coated conductive strip 330 can inhibit etching of the first portion 322 of the metal region 320. In an example, the etching 325 can include etching the coating 335 of the coated conductive strip 330, where the coating 335 can inhibit etching, at block 108, of the first portion 322 of the metal region 320. In one example, the coating 335 of coated conductive strip 330 of
In one example, the etching 325 can include at least partially etching, the coating 337 of the conductive strip 330, where the coated conductive strip 330 can inhibit etching, at block 108, of the first portion 322 of the metal seed region 320. In one example, the coating 337 of coated conductive strip 330 of
In an embodiment, a first etchant can be used to etch through the second portion 324 of the metal region 320 of Figure. In an example, the first etchant can include an acid having oxidizing agents (e.g., hydrogen peroxide). In some examples, the first etchant can include a base (e.g., potassium hydroxide, sodium hydroxide). In one example, the coated conductive strip 330 of
In an embodiment, the solar cell 300 can include conductive contacts 334, 336. In one embodiment, the conductive contacts 334, 336 include a coated conductive strip disposed on a metal region 320. In an example, the conductive contacts 334, 336 can be metal contact fingers. In some examples, the metal contact fingers can be interdigitated. In an embodiment, the coated conductive strip can include a metal strip 333 having a coating 337 as shown. In an example, the coating 337 can surround the metal strip 333. In an embodiment, the metal region 320 can have a thickness approximately in the range of 50-1000 nanometers. In an embodiment, the coating 337 can include aluminum (e.g., an aluminum region), aluminum/Si, nickel, copper, titanium, tungsten, and/or alloys thereof, among other examples. In an embodiment, the metal strip 333 can include nickel, copper, iron and steel, among other examples. In an embodiment, the ratio of the thickness of the coating 337 can be twice, ten times or 100 times, or more, to the thickness of the metal region 320. In one embodiment, the coating 337 can have a thickness 331 approximately in the range of 1-10 μm. In an embodiment, the coated conductive strip 330 can be a coated conductive wire, coated ribbon, coated pre-cut foil or a coated strip of foil. In one example, the coated conductive strip 330 can be a coated copper wire or a coated aluminum foil.
In an embodiment, another semiconductor region 414 can be located on the front side 404 of a solar cell 400. In an example, the semiconductor region 414 can include an N-type or P-type doped region. In an embodiment, another coated conductive contact 435 can be disposed on the semiconductor region 414 on the front side 404 of the solar cell 400. In an embodiment, the coated conductive contact 435 can also include a conductive strip 433 bonded to a metal region 420, where the conductive contact 435 is located on the semiconductor region 414 on the front side 404 of the solar cell 400. In an embodiment, the coated conductive strip 433 can have a coating 437. In some embodiments, the coated conductive strip 433 can be at least partially coated.
Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even where only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to a person skilled in the art having the benefit of this disclosure.
The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.
