Patent Application
20090115451
Embodiments of the invention relate generally to NAND devices and more particularly to a configurable and reusable NAND system.
A NAND device includes a plurality of blocks, each of which has a predetermined size for preserving data similar to a cluster of a hard disk. A Read/write operation to a NAND device is performed with a block and a page as a processed unit. An I/O (Input/Output) port with, for example, 8 bits may be used on a NAND device. A NAND device accesses data in sequence and the access mode is in a serial fashion. A NAND system provides interaction capabilities between a NAND device and a processor.
Deploying NAND systems in today's System on Chip (SoC) designs requires highly integrated solutions to address issues of data integrity and system performance.
Although the above goal of maximizing the usability of NAND systems with different NAND devices seems to be straightforward, immense complexity arises from the fact that NAND devices from different vendors, and different NAND devices from the same vendor, are inherently different in their command sets and command sequences. The value of a NAND system increases with the number of different NAND devices with which the hardware and software components of that NAND system can interact. Once the NAND controller is fixed in silicon and on a NAND platform, it will only be able to interact with NAND devices described in a lookup table incorporated into the NAND controller. In the existing NAND system, if a new NAND device that the NAND controller is not aware of is coupled to the NAND system, the NAND controller will fail to interact with that NAND device.
Thus, an important challenge of designing a NAND system lies in its adaptability to the devices of the present and of the future. Intelligence of how to interact with present NAND devices can be built into the system. What is needed is a NAND system adaptable to future NAND devices, which could be different from all existing NAND devices in command set and command sequencing.
Embodiments of the invention described herein provide a method and system for a configurable and reusable NAND system which is adaptive to various NAND devices independent of the NAND device manufacturer and NAND device characteristics.
An exemplary embodiment of the invention provides a method for configuring a NAND system when coupled with a NAND device. The method decodes a device identification signature signal from at least one NAND; analyzes the device identification signature signal to obtain control phase sequence values descriptive of the characteristic of the NAND device; populates the control phase registers with the control phase sequence values; and control phase registers then provide the stored control phase sequence values to the command sequencer.
An exemplary embodiment of the invention provides a system for configuring a NAND system when coupled with the NAND device. The system includes an initialization engine for capturing device identification signature signal of a NAND device; a command sequencer that interacts with the NAND device; a set of control phase registers that stores control phase sequence values corresponding to device identification signature signal and provides control phase sequence values to the command sequencer; and a low level driver for providing an initialization sequence comprising a set of control phase sequence values to the control phase registers.
Other aspects and example embodiments are provided in the Figures and the Detailed Description that follows.
Embodiments of the invention described herein provide a method and system for a configurable and reusable hardware-software NAND system which is adaptive to various NAND devices independent of the NAND device manufacturer and NAND device characteristics.
If a particular NAND device's information which is coupled to a NAND system is not present in a lookup table, the lookup table fails to decode the correct device identification signature signals and instead provides a default set of signals to the control phase registers. When the lookup table fails to decode the correct device identification signature signals for the control phase registers, the method of the embodiment of the invention configures the NAND controller to interact with the NAND device using steps 205-220. In short, steps 205-220 override the control phase registers with the control phase sequence values that are required for the NAND controller to interact with the new NAND device.
In step 205, the Low Level Driver (LLD) of the software reads the device identification signature from the NAND controller. In step 210, LLD analyzes the device signature identification signal to determine a set of control phase sequence values descriptive of the characteristics of the NAND device and thereby captures the NAND device's information that needs to be populated in the set of control phase registers. Upon analyzing the NAND device's information, the control phase registers are populated with the above-determined control phase sequence values using the NAND controller in step 215. In step 220, the control phase sequence values stored in the control phase registers are provided to the command sequencer for the NAND system to interact with the NAND device. The control phase sequence values include command phase sequence values and data phase sequence values which are derived from the device identification values.
In one embodiment of the invention, for populating the control phase registers with a set of control phase sequence values in case of a new NAND device, device signature information of the new NAND device is captured from a manufacturer ID, NAND device ID, page size information and device size information. Upon capturing the device signature information, the control phase registers are populated with the control phase sequence values of the new NAND device using the LLD.
In one embodiment of the invention, a set of abstracted control phase registers is populated with the control phase sequence values representing the device characteristics, and an initialization sequence is provided from the LLD to populate the abstracted control phase registers in case of a new NAND device. The abstracted control phase registers contain device signature information, which is decoded to populate the control phase registers with control phase sequence values characteristic to the NAND device. The control phase registers then provide the control phase sequence values to the command sequencer to interact with the NAND device.
The command sequencer 335, which is programmable, generates different command sets and command sequences. Depending on the type of NAND device 315 coupled to the NAND controller 310, the command sequencer 335 in the NAND controller 310 can be programmed to interact with that NAND device 315. Command sequencer 335 may be programmed through a set of unique device identification signature signals, which guide the command sequencer 335 through different command/address/data phases on the NAND device 315 interfaces. A device identification signature signal exists for every command type that the NAND device 315 supports.
At power-on of the NAND system 305, the NAND controller 310 reads the device ID of the NAND device 315 coupled to the NAND system 305. The NAND controller 310 further includes a lookup table 320 which includes information of all known NAND devices existing at the time of a particular NAND controller 310 release. If the read NAND device ID matches a known device ID, NAND controller 310 auto configures itself to work with that NAND device 315. After the device ID is decoded, the NAND controller 310 decodes values of the device identification signature signals to be applied to the control phase register set 330 from the lookup table 320. As in the prior art, this method works for all devices existing at the time of NAND controller 310 release.
As discussed in
In one embodiment of the invention, to configure the NAND controller 310 for providing the critical command phase signal, the signals from the NAND device 315 are routed to the command sequencer 335 from the control phase register 330. After reading NAND device ID through an initialization engine (not shown in
For a new NAND device 315 that the NAND system 305 needs to support, an initialization sequence for values stored in the abstracted control phase register 325 or control phase registers 330 can be packaged with the LLD 340 of the software. The initialization sequence includes the correct control phase sequence values to be programmed into the abstracted control phase register 325 or control phase register 330 for the NAND controller 310 to interact with the new NAND device 315. As new NAND devices become available, newer initialization sequences can be integrated to the NAND system 305, enhancing its usability and lifetime on the deployed platform.
The forgoing description sets forth numerous specific details to convey a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the invention may be practiced without these specific details. Well-known features are sometimes not described in detail in order to avoid obscuring the invention. Other variations and embodiments are possible in light of above teachings, and it is thus intended that the scope of invention not be limited by this Detailed Description, but only by the following Claims.
