Claims
- 1. A branch prediction mechanism comprising:a branch prediction cache configured to convey a hit/miss signal corresponding to an address, wherein said hit/miss signal is indicative of whether or not data corresponding to said address is present in said cache; a branch history table configured to convey a first branch prediction corresponding to said address; and a prediction circuit configured to convey a final branch prediction, wherein said prediction circuit is configured to: receive said hit/miss signal and said first branch prediction; convey said first branch prediction as said final branch prediction in response to detecting an enable signal indicates a first state; and convey a second branch prediction as said final branch prediction in response to detecting said enable signal indicates a second state.
- 2. The branch prediction mechanism of claim 1, wherein said first state of said enable signal indicates said hit/miss signal is ignored, and wherein said second state of said enable signal indicates said hit/miss signal is not ignored.
- 3. The branch prediction mechanism of claim 2, wherein said second branch prediction is a not taken prediction, in response to detecting:said enable signal indicates said second state; and said hit/miss signal indicates said data is not present in said branch prediction cache.
- 4. The branch prediction mechanism of claim 3, wherein said first branch prediction is a taken prediction.
- 5. The branch prediction mechanism of claim 2, wherein said final branch prediction is a taken prediction, in response to detecting:said enable signal indicates said second state; said first branch prediction indicates a taken prediction; and said hit/miss signal indicates said data is present in said branch prediction cache.
- 6. The branch prediction mechanism of claim 1, wherein said branch history table is configured to update a next branch prediction corresponding to said address, wherein said next branch prediction is a not taken prediction, in response to detecting said hit/miss signal indicates said data is not present in said branch prediction cache.
- 7. The branch prediction mechanism of claim 1, wherein said prediction circuit is further configured to:receive decode information corresponding to said address; and convey a taken prediction as said final prediction, in response to detecting said decode information indicates a first opcode.
- 8. The branch prediction mechanism of claim 7, wherein said opcode corresponds to a Loop instruction.
- 9. A method for performing branch prediction comprising:conveying a hit/miss signal corresponding to an address, wherein said hit/miss signal is indicative of whether or not data corresponding to said address is present in a branch prediction cache; conveying a first branch prediction corresponding to said address; receiving said hit/miss signal and said first branch prediction at a prediction circuit; conveying said first branch prediction as a final branch prediction in response to detecting an enable signal indicates a first state; and conveying a second branch prediction as said final branch prediction in response to detecting said enable signal indicates a second state.
- 10. The method of claim 9, wherein said first state of said enable signal indicates said hit/miss signal is ignored, and wherein said second state of said enable signal indicates said hit/miss signal is not ignored.
- 11. The method of claim 10, wherein said second branch prediction is a not taken prediction, in response to detecting:said enable signal indicates said second state; and said hit/miss signal indicates said data is not present in said branch prediction cache.
- 12. The method of claim 11, wherein said first branch prediction is a taken prediction.
- 13. The method of claim 10, wherein said final branch prediction is a taken prediction, in response to detecting:said enable signal indicates said second state; said first branch prediction indicates a taken prediction; and said hit/miss signal indicates said data is present in said branch prediction cache.
- 14. The method of claim 9, wherein said first branch prediction is conveyed from a branch history table, and wherein said method further comprises updating a next branch prediction corresponding to said address, wherein said next branch prediction is a not taken prediction, in response to detecting said hit/miss signal indicates said data is not present in said branch prediction cache.
- 15. The method of claim 9, further comprising:receiving decode information corresponding to said address; and conveying a taken prediction as said final prediction, in response to detecting said decode information indicates a first opcode.
- 16. The method of claim 15, wherein said opcode corresponds to a Loop instruction.
- 17. A processor comprising:branch prediction logic, said logic comprising: a branch prediction cache configured to: convey a hit/miss signal corresponding to an address, wherein said hit/miss signal is indicative of whether or not data corresponding to said address is present in said cache; a branch history table configured to convey a first branch prediction corresponding to said address; and a prediction circuit configured to convey a final branch prediction, wherein said prediction circuit is configured to: receive said hit/miss signal and said first branch prediction; convey said first branch prediction as said final branch prediction in response to detecting an enable signal indicates a first state; and convey a second branch prediction as said final branch prediction in response to detecting said enable signal indicates a second state.
- 18. The processor of claim 17, wherein said first state of said enable signal indicates said hit/miss signal is ignored, and wherein said second state of said enable signal indicates said hit/miss signal is not ignored.
- 19. The processor of claim 18, wherein said second branch prediction is a not taken prediction, in response to detecting:said enable signal indicates said second state; and said hit/miss signal indicates said data is not present in said branch prediction cache.
- 20. The processor of claim 19, wherein said first branch prediction is a taken prediction.
- 21. The processor of claim 18, wherein said final branch prediction is a taken prediction, in response to detecting:said enable signal indicates said second state; said first branch prediction indicates a taken prediction; and said hit/miss signal indicates said data is present in said branch prediction cache.
- 22. The processor of claim 17, wherein said branch history table is configured to update a next branch prediction corresponding to said address, wherein said next branch prediction is a not taken prediction, in response to detecting said hit/miss signal indicates said data is not present in said branch prediction cache.
- 23. The processor of claim 17, further comprising a decode unit configured to decode an instruction corresponding to said address, wherein said prediction circuit is further configured to:receive decode information corresponding to said address; and convey a taken prediction as said final prediction, in response to detecting said decode information indicates a first opcode.
- 24. The processor of claim 23, wherein said opcode corresponds to a Loop instruction.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. application Ser. No. 09/608,451, filed Jun. 29, 2000, now U.S. Pat. No. 6,360,318, which is a continuation of Ser. No. 09/073,499, filed May 6, 1998, now U.S. Pat. No. 6,108,777, which is a division of Ser. No. 08/472,698, filed Jun. 6, 1995, now U.S. Pat. No. 5,815,699, which is a continuation of Ser. No. 08/112,572, filed Aug. 25, 1993, now U.S. Pat. No. 5,454,117.
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Continuations (3)
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Number |
Date |
Country |
Parent |
09/608451 |
Jun 2000 |
US |
Child |
09/992822 |
|
US |
Parent |
09/073499 |
May 1998 |
US |
Child |
09/608451 |
|
US |
Parent |
08/112572 |
Aug 1993 |
US |
Child |
08/472698 |
|
US |