Patent Application
20080114918
1. Field of the Invention
This invention relates to computer systems, and more particularly, to reconfigurable computer systems.
2. Description of the Related Art
The proliferation of computer networks in recent years has increased the demand for server systems. Server systems can be implemented in local area networks, wide area networks, internet service providers, storage systems, and the like. The variety of networks has correspondingly resulted in a wide variety of server systems available on the market.
While some server systems include only a single processor, many utilize multiple processors. In server systems utilizing multiple processors, it may be necessary for the processors to communicate with each other for various reasons (e.g., maintaining cache coherency, sharing the application load, etc.). Various topologies may be implemented for coupling the processors in a manner that enables them to communicate with each other.
At times, it may be desirable to change the configuration of a server. For example, an expanding business may need to increase the number of computers coupled to its local area network, and may in turn need to implement more processing power in the network server(s). Increasing the processing power may be more than a simple matter of adding processors to the server system. Since it may be necessary for the processors to communicate with each other, the addition of processors may require conformance to a topology that enables them to do so. This may be difficult, if not impossible, given that such a change could require a significant rerouting of the system board. Thus, the addition of processing power may require the replacement of a server instead of a mere addition of processors.
A method for providing multiple configurations for a computer system is disclosed. In one embodiment, the method provides interconnection of processor boards in a first configuration and a second configuration. In the first configuration, a first plurality of processor boards are interconnected through a first backplane. In a second configuration, a second plurality of processor boards are interconnected through a second backplane. The first and second pluralities of processor boards are interchangeable with each other. This allows the changing of a system configuration by changing the backplane with no other hardware changes. For example, in one embodiment, a system having 8 processors (with 8-bit interconnections) can be reconfigured to a system having 4 processors (with 16-bit interconnections) by simply changing the backplane.
In one embodiment, the interconnections for both of the first and second processors are direct, point-to-point links. The point-to-point links may comply with a point-to-point protocol (e.g., such as the HyperTransport™ protocol). Through this interconnection topology, each processor may have a direct link to every other processor, or in other words, the link is shared only by the two processors linked together and is thus a “one-hop” topology. This is in contrast to topologies that are not fully connected, and thus involve at least 2 hops to another processor (i.e. a first processor connecting to a second processor via a third processor). Thus, each processor can directly communicate with any other processor with no dependency on a third processor, thereby reducing system latency.
The interconnections between processors may be of various bit-widths. For example, in the first configuration, each interconnection may be eight bits wide, while in the second configuration (with fewer processor boards than the first configuration), the interconnections may be doubled up to form sixteen bit interconnections. Also contemplated are configurations wherein some of the interconnections are sixteen bits wide while others are eight bits wide.
Other aspects of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and description thereto are not intended to limit the invention to the particular form disclosed, but, on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling with the spirit and scope of the present invention as defined by the appended claims.
Turning now to
Server system 5 is a computer system including a backplane 10 having a plurality of connectors 102 mounted thereupon. Each of a plurality of processor boards 100 is coupled to backplane 10 by a corresponding connector 102. In this particular embodiment, there are eight connectors 102 mounted to backplane 10, and eight processor boards 100 coupled to the backplane via the connectors. Embodiments having a different number of connectors (and thus, a different number of processor boards) are possible and contemplated. Furthermore, embodiments wherein some connectors may be unoccupied (i.e. a system configuration wherein six processors are connected to a backplane having eight connectors and thus the capacity to accommodate eight processors) are also possible and comtemplated.
Server system 5 also includes one or more I/O connectors 120, which may accommodate various devices capable of communicating with the processor boards 100. Such devices may include disk drives, optical disk drives (e.g., DVD-ROM drives), monitors, printers, and other types of peripherals.
Backplane 10 is configured to accommodate a plurality of inter-processor links 110. In the embodiment shown, each link 110 is a point-to-point, clock-forwarded link. Each processor 101 includes a plurality of link interfaces each configured to couple to a link 110. Through the topology of the links 110, each processor 101 shares a direct point-to-point link with every other processor 101. In contrast to a bussed link between two processors (which may be shared by additional processors as well as other devices), each point-to-point link is shared only by two processors, and thus allows communication between them without arbitration with other processors. This type of interconnection topology may result in a significant performance improvement over topologies where a number of processors share the same, bussed link. For a given processor 101 having eight link interfaces, seven of these link interfaces may be used to couple the processor to the other seven processors via a point-to-point link. The point-to-point links establish a “one-hop” topology, whereby each processor can communicate directly with any other processor without being dependent upon a third, intervening processor.
In the embodiment of
In addition to the links between the processors, each processor 101 has a link to an I/O connector 120, which in turn may be linked to an I/O device 135 by a link 110. These links 110 may be of the same protocol of the inter-processor links 110 on backplane 10, and may allow for the coupling of peripheral devices to the processors of computer system 5. Additional I/O devices (beyond those shown here) may also be linked to the processors in accordance with the protocol of the links 110. Thus, each of the processors 101 may have a direct link to every other processor 101 in the system as well as direct, point-to-point links to various I/O devices 135.
Embodiments are also possible and contemplated wherein some of the inter-processor links are wider than other inter-processor links. For example, embodiments are possible wherein a processor shares a 16-bit link with at least a first other processor in the system and an 8-bit link with at least a second other processor in the system. Embodiments including an odd number of processor boards, which may include links of differing bit-widths (e.g., at least one 16-bit link and at least one 8-bit link) are also possible and contemplated.
Configuration changes from the embodiment shown in
It should also be noted that the examples of
Processor 101 in the embodiment shown includes a plurality of interfaces 103 which are used to enable the point-to-point links with other processors and I/O connections. For example, in one embodiment interfaces 103 are HyperTransport™ interfaces, and more particularly, an HT3 interfaces. As such, interfaces are eight bits wide in this particular embodiment, although other bit-widths are possible and contemplated. As previously noted, in embodiments such as that shown in
Each processor board 100 may be interchangeable with other instances of processor board 100. Thus, even if one processor board 100 is not identical with another processor board 100 in every respect, it may be functionally interchangeable such that it may be used in a number of different embodiments/configurations, and may further be re-utilized when from one configuration to another (e.g., may be used in the configurations of both
The second plurality of processor boards may include one or more of the first plurality of processor boards and/or include a plurality of processor boards that is interchangeable with the first plurality. For example, if changing the configuration from a 4-processor system to an 8-processor system, the four processor boards of the first system may be combined with four additional (and interchangeable) processor boards to create the second plurality. In another example, if changing the configuration from an 8-processor system to a 4-processor system, the second plurality of processor boards may be comprised of four of the processor boards from the first plurality. Alternatively, the same processor boards need not be used in a configuration change, wherein the second plurality of processor boards may comprise a separate plurality of processor boards, each being interchangeable with any processor board of the first plurality.
Although the systems and methods discussed herein have been directed to server systems, the disclosure is not intended to be limiting as such. The systems and methods discussed herein may be applied to any computer system having a backplane configured to receive a processor board, regardless of the intended use of the computer system.
While the present invention has been described with reference to particular embodiments, it will be understood that the embodiments are illustrative and that the invention scope is not so limited. Any variations, modifications, additions, and improvements to the embodiments described are possible. These variations, modifications, additions, and improvements may fall within the scope of the inventions as detailed within the following claims.
