The present invention relates to a data port, such as an ingress/egress data port of an Ethernet switch, which is configurable to operate in one of multiple modes.
A gradual shift is occurring from Fast Ethernet (FE) systems to Gigabit Ethernet (GE) systems. This, and the use of Ethernet in First Mile (EFM), makes it advantageous to provide a configurable Ethernet switch which can function both as a Fast Ethernet and as a Gigabit Ethernet switch, in order to facilitate the transition from FE to GE Ethernet.
In general terms, the present invention proposes that an ingress/egress port is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port includes a plurality of MAC interfaces each of which is capable of receiving/transmitting FE packets. At least one of the MAC interfaces is further configurable to receive GE packets. The port further includes receive and transmit modules which are configurable respectively to receive both GE and FE packets from, and transmit GE and FE packets to, the interfaces.
Preferably, there is only a single MAC interface which is configurable to receive/transmit either GE or FE packets, and the other MAC interfaces are only adapted to receive/transmit FE packets. Typically, there are 8 MAC interfaces per port.
Preferably, the MAC interfaces are each associated with a buffer, so that, as packets are received by the interfaces they are stored. Packets may arrive concurrently on all FE ports and are stored in individual buffers. The buffers are polled sequentially by the receive module.
Preferably, there are a plurality of such ports in the Ethernet switch. For example, if there are 8 such ports, then by switching different numbers of the ports between the two modes, the switch may operate in 9 different modes: as 8 GE ports, 7 GE ports and 8 FE ports, . . . , 2 GE ports and 48 FE ports, 1 GE port and 56 FE ports, or simply as 64 FE ports.
Preferred features of the invention will now be described, for the sake of illustration only, with reference to the following figures in which:
Referring firstly to
The receive module 5 is shown including the following major sections: a memory 51 rx_mem; a 53 section having an interface rx_max_iface for extracting the Ethernet header from incoming data packets and putting it into a descriptor, and for putting data from incoming packets into cells, and a parser rx_parser for extracting information from other headers in the packet, and adding this information also to the descriptor; and a section 55 having a first interface ax_ed_iface and a second interface rx_pr_iface
The Ethernet port 1 further includes a transmit module 7, shown having the following major sections: a memory TX_MEM 71; a TX_MAC_IFACE 73; and a section 75 including a tx_edram_iface and a tx_pq_iface.
The receive module 5 communicates with a packet resolution module 2 and an embedded DRAM (eDRAM) 4. The transmit module 7 communicates with the embedded DRAM 4 and a queue/packet manager 6.
The Ethernet port 1 further includes an interface 9 to the CPU, and MIB (management information base) counters 11. These counters count various packet types, e.g. the number of 64 byte packets.
The structure of the RX module 5 is shown in more detail in
The timechart of
The above scheme is not altered fundamentally when the switch occurs between GE and FE. The changes are that the amount of data is larger in GE, so that more of the memory cells RXD_CELLs are used are used per packet, and that the parsing is different.
If the delay is longer than 88 cycles, only the performance is impacted. Packets stay longer in the RX. If this trend continues then eventually all PCT_DCC will be occupied.
Turning now to
Accessing data from the eDRAM 4 (the first pbnum and current pbnum).
Sending data to tx_ofifo (ready for transmission, current offset in TXD_CELL, etc).
Receiving packets from the packet manager pm (ready for release, etc).
Basic buffer allocation (entry assigned, etc).
Unlike in the receive module 5, the storage of a frame within tx_mem mgr is uniform with all data being stored in 32 byte cells called TXD_CELLs. There are 24 packet descriptors and 36 TXD cells. When the Ethernet port 1 is configured as 8 FE ports, all packet descriptors PKT_DSCs and TXD_CELLs are divided equally among all the FE ports.
Again, the above scheme is hardly varied as between the GE and FE cases. The RX and TX interfaces know which type of packets they are to handle from data received as PINS signals shown in
This application is a continuation application of U.S. application Ser. No. 10/526,990, filed Mar. 7, 2005, which claims priority to International Application No. PCT/SG02/00211, filed Sep. 6, 2002.
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Number | Date | Country | |
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20120069848 A1 | Mar 2012 | US |
Number | Date | Country | |
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Parent | 10526990 | US | |
Child | 13270760 | US |