Patent Application
20220345089
The disclosure relates to phase matching between output paths or between gain modes. Specifically, it relates to matching the phase between gain paths of low noise amplifiers (LNAs), including two-stage LNAs.
As a signal goes through a device, such as a low-noise amplifier, the elements of the device can impose a phase shift from the input signal. For devices with different paths (e.g. different gain paths, such as high gain wideband paths vs. low current power saving paths) for the signal to traverse in different operation modes, these phase shifts can be different from each other. For example, in a low noise amplifier, there may be different selectable paths for different gains, including a bypass path for low gain. Some applications require that switching between these modes apply a minimal phase shift.
The systems and methods presented herein provide for phase matching different output paths of a circuit in a way that minimizes the number of added components to the circuit. Specifically, it utilizes existing components of a given path, for example components used for output impedance matching, in the phase matching elements added to that path.
According to a first aspect of the present disclosure, a device is described comprising: a first gain path with a first gain and a first circuit component; a second gain path with a second gain different than the first gain and a second circuit component separate from the first circuit component; a phase shift sub-circuit on the second gain path wherein the phase shift sub-circuit includes the second circuit component and the second circuit component performs output matching for the device on the second gain path. In various embodiments the first gain path comprises a first low noise amplifier with a first active device, or the second gain path comprises a second low noise amplifier with a second one active device, or the first gain path comprises the first low noise amplifier with the first active device and the second gain path comprises the second low noise amplifier with the second one active device.
According to a second aspect of the present disclosure, a method for adding a phase matching sub-circuit to a circuit with multiple gain paths is described, the method comprising: selecting a gain path of the multiple gain paths; determining a phase shift to match a phase of the gain path to phases of other gain paths of the multiple gain paths; determining a circuit component on the gain path to include in the phase matching sub-circuit; selecting a topology of the phase matching sub-circuit based on the phase shift and the circuit component; including the phase matching sub-circuit to the circuit.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference numbers and designations in the various drawings indicate like elements.
An improved group of systems and methods is presented that minimizes phase discontinuity between different gain modes (including bypass modes) with minimal increase in circuit size (footprint or number of components) and complexity. This is particularly useful for low noise amplifier design but can also be applied to other devices.
As used herein, “phase matching” refers to minimizing or effectively reducing the phase difference between two or more signals. As used herein, “phase shift” refers to adjusting the phase of a signal to be temporally either ahead or behind the signal's previous phase. Changing the phase to be later in time can be referred to as increasing the phase or making a positive phase shift. Changing the phase to be earlier in time can be referred to as decreasing the phase or making a negative phase shift.
As used herein, “gain mode” is a mode of the circuit that provides a specific gain level (usually as a function of frequency) relative to other gain modes.
As used herein, “gain path” refers to a circuit path to an output that has a gain or loss relative to other outputs. As used herein, “bypass path” is a gain path that has a lower gain than most other gain paths and lower gain than any other non-bypass gain paths. A single given gain path can have multiple gain modes depending on what elements in the path are connected (via switches) during use. Gain paths can include transistor amplifiers such as one stage amplifiers (e.g. for low gain paths) and two stage amplifiers (e.g. for high gain paths).
As used in the present disclosure, the term “sub-circuit” refers to a circuit/network of elements that are used as part of a larger circuit/network/device.
These phase shift sub-circuits (310, 320) can be placed anywhere in their respective paths where a circuit element (e.g. capacitor or inductor) is already located (e.g. as an output matching element). There can be one phase shift element, or multiple, so long as the cumulative effect is that the paths (gain and bypass) are all phase matched. These sub-circuits can take many forms, depending on the requirements of the sub-circuit at that location (phase shift direction, high-pass vs. low pass, number and type of existing elements used, etc.)
In some embodiments, the highest gain mode is used as the reference phase and other gain modes are phases shifted to match the highest gain mode. This prevents loss in the highest gain mode due to any addition of elements (e.g. the phase shifter). In some embodiments, a different reference is used, for examples another gain mode (whereby that gain mode would not be phase shifted) or an external reference phase (whereby all gain modes are phase shifted).
Examples of simple sub-circuit topologies are shown in
As stated herein, a circuit that typically has an active and a passive bypass can be simplified by adding, for example, a configurable phase correction sub-circuit centered around 180 degrees, to the passive bypass path. With the passive bypass corrected, the active bypass is no longer need and can be removed from the circuit. This allows the circuit to have a smaller footprint, reduced complexity (thus better high gain mode performance), lower cost, etc. Table 1 shows the differences between the different paths, with and without the phase shifting sub-circuit added.
As shown in Table 1, the new output match/phase shifter architecture phase correction in bypass mode provides a very high linearity with high phase matching with the least IDD current (supply current) consumed.
In some embodiments the ratio of inductors to capacitors is kept at a fixed ratio (e.g. 1:2) when scaling in order to modify the phase value while keeping the impedance constant (e.g. 50 Ohms).
The combination of output matching and phase shifter sub-circuit elements is exemplified in
A phase shift correction sub-circuit can be implemented using transmission lines. This is especially useful at millimeter-scale wavelength signals.
A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, or parallel fashion.
Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.
Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.
Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or or modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.
It is to be understood that the disclosure is not limited to particular methods or systems, which can, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in this specification and the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the content clearly dictates otherwise. The term “plurality” includes two or more referents unless the content clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains.
It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).
