1. Field
The present invention relates generally to wireless communication. More specifically, a configurable wireless interface is disclosed.
2. Background
With the increasing popularity of portable computing devices and wireless connectivity, there has been a proliferation of wireless communication standards and protocols. For example, a Personal Digital Assistant (PDA) may communicate with several other portable or non portable devices wirelessly and run wireless applications. Such a PDA may at different times (and in some cases, concurrently) implement WLAN, BLUETOOTH® (a short-range wireless radio technology), GPS, Cellular, Cordless or other RF applications. Currently, each such application requires its own software and hardware and as a result each application that is enabled contributes individually to the cost of the portable device. In addition, each application is generally configured in the device before the device is sold, or in some cases purchased as a hardware add on.
It would be very useful if a device could be developed that could be configured and reconfigured to implement different wireless applications and protocols as desired. Furthermore, if such a device could use common hardware or reconfigurable software resources to implement different protocols or applications, then the cost of potentially including a large selection of applications in a device could be reduced. What is needed, therefore, is a configurable wireless interface that could be included in a device to allow that device to be configured to run multiple wireless applications.
The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which:
A detailed description of a preferred embodiment of the invention is provided below. While the invention is described in conjunction with that preferred embodiment, it should be understood that the invention is not limited to any one embodiment. On the contrary, the scope of the invention is limited only by the appended claims and the invention encompasses numerous alternatives, modifications and equivalents. For the purpose of example, numerous specific details are set forth in the following description in order to provide a thorough understanding of the present invention. The present invention may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the present invention is not unnecessarily obscured.
Modular RF interface 100 likewise includes a data interface 114 and a control interface 116. Modular RF interface 100 also includes a feature register 118 that communicates with control interface 116 and is described further in
In some embodiments, programming interface 122 is provided to write new application tables to control database 120 or to edit existing application tables. By loading new parameters for an application, the modular RF interface can be configured to support a new application or an updated existing application without a hardware change. The RF interface is engineered or re-engineered by software input to the programming interface. This flexible design allows new applications to be installed in the modular RF interface and made available to the host by simply downloading the required parameters.
It should be noted that programming interface 122 may logically and/or physically be a separate interface as shown in
When an application table is selected, the data from the table is used to configure various devices included in RF processor 124. RF processor 124, once configured, receives data from the host via data interface 114 for transmission and/or receives a signal from an antenna for processing and returns the processed signal to the host. Data interface 114 may be any suitable interface capable of exchanging data between the host and the modular RF interface. In one embodiment, data interface 114 is a serial interface. In embodiments that plug the modular RF interface into a legacy application, data interface 114 may include a remodulator that recreates a signal that is processed by a conventional baseband processor on the host.
On the transmit side, in the embodiment shown, three possible antenna inputs 202 are shown. The signal paths from each of the antennas are shown separately through amplifiers 204 which are preferably low noise amplifiers and mixers 206 which are driven by local oscillator 205 controlled by a digital synthesizer 207. In some embodiments, a common amplifier may be used by the different antennas by implementing a series of switches to select the desired antenna. Likewise, in some embodiments, a common antenna may be shared by different amplifiers by implementing a series of switches or other appropriate arrangement.
It should be noted that in other embodiments, different numbers of signal paths may be included. Also, in some embodiments, a signal path may be used for more than one application. For example, one signal path may be used for GSM, GPRS, and EDGE. In general, the low noise amplifier and the mixer are determined by the frequency band of the application or wireless protocol that is being implemented. Applications that may be implemented in a signal path include WCDMA, or GSM, GPRS, and EDGE or TDMA, CDMA and CDMA 2000-xx or wireless LANs, BLUETOOTH® (a short-range wireless radio technology), cordless phones and GPS or DCS 1800 and PCS or PCS 1900. Other applications may be included as well.
Filter 208 receives a signal from the selected signal path that includes a selected amplifier and mixer. Filter 208 is programmed according to a selected application to appropriately provide anti aliasing and/or image rejection. In one embodiment, filter 208 is a low pass filter and the frequency cutoff is programmed according to the selected application. Filter 208 may also be a bandpass filter. In one embodiment, filter 208 is an active or passive RC filter and a switchable array of capacitors or resistors or both is programmed to select the required components for a given response. The output of filter 208 is input to an analog to digital converter (ADC) 210. The digital output of ADC 210 is processed by a digital signal processor (DSP) 212. DSP 212 is reconfigurable and is programmed to process the signal in a manner that varies with the selected application. In general, DSP 212 processes both I and Q channel signals received from ADC 210. DSP 212 may also be configured to process a signal that is being transmitted.
In some embodiments, the signal is not converted all the way down to baseband in the analog domain and DSP 212 includes a numerical oscillator that down converts the signal in the digital domain the remainder of the way to baseband from the intermediate frequency achieved by the selected mixer and digitally controlled local oscillator.
In one embodiment, DSP 212 is configured to perform all baseband processing of the signal. However, in different embodiments, various signal processing functions may be performed off chip by a host processor. For example, voice processing, coding/decoding, and error correction may be performed on the host processor while modulation and demodulation, equalization and filtering are performed by the on chip transceiver using DSP 212. A host controller function may be implemented partly on chip and partly on the host. In certain embodiments, for the purpose of communicating with a legacy system that includes a baseband processor configured to receive an analog IF signal input, DAC 214 is provided to remodulate the signal to communicate with baseband processor 216. The baseband processor preferably is implemented on the host. In some embodiments, a dedicated baseband processor chip may be used.
In a similar manner, the transmit side includes programmable components that are configured to work with different applications such as the ones listed above as well as separate components included in alternative signal paths. An analog signal may be received from baseband processor 216 if a legacy device is being used. ADC 234 converts an analog input to a digital signal to be processed by DSP 212. Alternatively, a digital signal may be input to the chip using a suitable digital interface. DSP 212 encodes and/or modulates the signal according to the selected application and provides an output to DAC 230. The output of DAC 230 is filtered by a programmable analog filter 228. The output of filter 228 is selectably routed to a signal path that includes a mixer 226 and an amplifier 224. The output of amplifier 224 is sent to a transmit antenna or transmitting system. In some embodiments, the separate signal paths may be combined.
In some embodiments, the transmitter may additionally be reconfigured to include digital up conversion. Also, the transmitter mode may be switched to a translational loop architecture for constant envelope modulation schemes such as GSM.
The transceiver architecture shown shows a configurable signal path using switches as well as individually configurable components that are reprogrammed and reused in different modes. In other embodiments, the signal path is configured in other manners and different configurable components may be selected. However, the benefit of reusing certain components is still enjoyed. In particular, the common DSP greatly reduces the amount of area required to implement the different protocols.
The programmable analog filter is programmed according to filter parameters 410 which define the analog filter response. It should be noted that each of the parameters shown may be an array of parameters or a pointer to a data structure that contains the parameter or set of parameters.
The ADC is configured according to the ADC parameters 416 and 418. Parameter 416 specifies the ADC sample rate and Parameter 418 specifies the ADC precision. Other ADC parameters are specified in other embodiments. By specifying the filter parameters and the ADC parameters, the filter and ADC are configured to operate for different applications. The reuse of the ADC and filter components for different applications greatly reduces the cost of the modular RF interface.
If a digital down conversion is performed, then parameter 420 may be used to specify a numerical oscillator or digital IF. Digital filter parameters may also be specified. For example, parameter 422 specifies digital filter coefficients; and parameter 424 specifies digital filter taps.
If a DAC is used after the DSP to generate an analog signal for a legacy interface to communicate with the baseband processor, then analog interface identifier 426 may be included to indicate the type of analog waveform that is to be generated. In general, different analog waveforms may be generated for different types of baseband processors. In one embodiment, either a digital or an analog PLL is used to generate a timing signal for the legacy or digital interface. A digital or analog PLL may be used with the DAC or digital interface for the baseband or host processor and support various types of timing and data formatting. The PLL can generate different phase or frequency through programming. Parameter 428 is used to program various kinds of timing and data formatting.
The programmable analog filter is programmed according to filter parameters 460 which define the analog filter response. It should be noted that each of the parameters shown may be an array of parameters or a pointer to a data structure that contains the parameter or set of parameters.
The DAC is configured according to the DAC parameters 416 and 418. Parameter 416 specifies the DAC sample rate and Parameter 418 specifies the DAC precision. Other DAC parameters are specified in other embodiments. By specifying the filter parameters and the DAC parameters, the filter and DAC are configured to operate for different applications. The reuse of the DAC and filter components for different applications greatly reduces the cost of the modular RF interface.
If a digital up conversion to a digital IF is performed, then parameter 420 may be used to specify a numerical oscillator or digital IF. Digital filter parameters may also be specified. For example, parameter 422 specifies digital filter coefficients; and parameter 424 specifies digital filter taps. If an ADC is used before the DSP in the transmit path to receive an analog signal from the baseband processor, then analog interface identifier 476 may be included to indicate the type of analog waveform is to be received. In general, different analog waveforms may be generated by different types of baseband processors. In one embodiment, either a digital or an analog PLL is used to generate a timing signal for the legacy or digital interface. A digital or analog PLL may be used with the ADC or digital interface to receive the data from the baseband or host processor and provide various type of timing and identify the data formatting. The PLL can generate different phase or frequency through programming. Parameter 4478 is used to program various kinds of timing and data formatting.
It should be noted that in other embodiments, different data structures are used to configure or select components for the modular RF interface. The disclosed table format is one of many structures that may be used as is deemed appropriate for a specific system.
In a similar manner, identifiers and parameters are also specified on the transmit side so that the transmit signal path is selected and the transmit DAC and analog filter are configured.
In some embodiments, depending on the host or baseband processor, it may be desirable to program the control/data interface, protocol or signaling. The programming interface supports this programming.
A modular RF interface has been described. The modular RF interface is configurable to support different applications by selecting a set of stored parameters that select a signal path and configure components. The modular RF interface may be programmed to support additional applications by loading in configuration data for such applications.
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the exemplary embodiments of the invention.
The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The previous description of the disclosed exemplary embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these exemplary embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The present Application for Patent is a divisional of patent application Ser. No. 11/352,438, entitled, “CONFIGURABLE WIRELESS INTERFACE”, pending and filed Feb. 10, 2006, which is a continuation of U.S. Pat. No. 7,035,595, entitled, “CONFIGURABLE WIRELESS INTERFACE”, issued Apr. 25, 2006, and assigned to the assignee hereof and hereby expressly incorporated by reference herein.
Number | Date | Country | |
---|---|---|---|
Parent | 11352438 | Feb 2006 | US |
Child | 12554621 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 10043642 | Jan 2002 | US |
Child | 11352438 | US |