Configuration and controlling method of Fractional-N PLL having fractional frequency divider

Abstract

The provided fractional frequency divider includes a divider controlling unit for generating a divider selection signal in response to a dual-edge triggering of an input signal and a frequency dividing unit coupled to the divider controlling unit for dividing the frequency of the input signal by one of an integer and a fractional dividers in response to the dual-edge triggering and the divider selection signal to generate the output signal of the fractional frequency divider. An operation of the frequency dividing unit is not suppressed when the integer divider is employed, the operation of the frequency dividing unit is not suppressed for a period of the input signal and is suppressed for half of that period, and this cycle is kept on recurring when the fractional divider is employed. The fractional-n PLL having the fractional frequency divider is also provided.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is the block diagram of a conventional PLL frequency synthesizer;

FIG. 2 is the block diagram of a conventional Fractional-N PLL frequency synthesizer;

FIG. 3 is the schematic circuit diagram of a conventional PFFD;

FIG. 4 is the schematic circuit diagram of a conventional 2/3 frequency divider;

FIG. 5 is the schematic circuit diagram of a 1/1.5 frequency divider according to the first preferred embodiment of the present invention;

FIG. 6 is the timing chart of the 1/1.5 frequency divider according to the first preferred embodiment of the present invention in the divide-by-1.5 mode;

FIG. 7 is the schematic circuit diagram of a PFFD having a modulus resolution of 0.5 according to the second preferred embodiment of the present invention;

FIG. 8 illustrates the measured 50% duty free cycle output waveform (871 MHz) of the divide-by-three circuit according to the second preferred embodiment of the present invention when a 2.6 GHz input signal is applied;

FIG. 9 illustrates the measured output waveform (10.02 MHz) of the PFFD according to the second preferred embodiment of the present invention when the modulus=255.5 and a 2.56 GHz input signal is applied;

FIG. 10 illustrates the measured output waveform (2.504 MHz) of the PFFD according to the second preferred embodiment of the present invention when the modulus=511 and a 1.28 GHz input signal is applied;

FIG. 11 is the schematic circuit diagram of a PFFD having an AMR according to the third preferred embodiment of the present invention;

FIGS. 12 (a) to 12(c) are the system block diagram of a FNPLL frequency synthesizer according to the fourth preferred embodiment of the present invention, the block diagram of the main circuit of the FNPLL frequency synthesizer according to the fourth preferred embodiment of the present invention and the block diagram of the main circuit of a FNPLL frequency synthesizer according to the fifth preferred embodiment of the present invention respectively;

FIG. 13 is the schematic circuit diagram of a PFFD having a modulus combiner according to the sixth preferred embodiment of the present invention;

FIG. 14 shows the measuring apparatus for the chip built according to FIG. 12(a);

FIG. 15 illustrates the measured phase noise profiles of the chip built according to FIG. 12(a) when the reference signal frequency is 33 MHz, the carrier frequency is 2813 MHz and the 1/1.5 frequency divider 411 is turned on and off respectively; and

FIG. 16 illustrates the measured phase noise profiles of the chip built according to FIG. 12(a) when the modulus combiner has the same carrier frequency and the DSM has different modulating bits of 0 bit, 1 bit, 2 bits and 3 bits respectively.

Claims

1. A fractional frequency divider (FFD), comprising: a modulus controlling unit (MCU) generating a modulus selection signal (MSS) in response to a dual-edge triggering (DET) of an input signal; anda frequency dividing unit (FDU) coupled to said MCU and dividing a frequency of said input signal by one of an integer and a fractional moduli in response to said DET and said MSS to generate an output signal.

2. The FFD according to claim 1, wherein said DET indicates that both said MCU and said FDU are triggered by a rising edge and a falling edge of said input signal.

3. The FFD according to claim 1, wherein said MSS is in a logic low state and an operation of said FDU is not suppressed when said FFD is in a divided-by-said integer modulus mode, said operation is suppressed when said MSS is in a logic high state, and said operation has a recurring cycle, in which said operation is not suppressed for a time period of said input signal and then suppressed for half of said time period of said input signal, when said FFD is in a divided-by-said fractional modulus mode.

4. The FFD according to claim 3, wherein said MCU further receives a modulus control signal (MCS) and a feedback control signal (FCS), said MSS is in said logic low state when one of said MCS and said FCS is in said logic low state, and said MSS is in said logic high state when said MCS and said FCS are both in said logic high state.

5. The FFD according to claim 4, wherein said integer modulus is 1 and said fractional modulus is 1.5.

6. The FFD according to claim 5, further comprising an input terminal receiving said input signal and an output terminal outputting said output signal, wherein said FDU further comprises: a first NOT gate having an input and an output terminals;a first AND gate having a first terminal, a second terminal coupled to said output terminal of said first NOT gate and an output terminal;a second NOT gate having an input terminal coupled to said output terminal of said FFD and receiving a first feedback signal and an output terminal coupled to said first terminal of said first AND gate;a first latch having a first terminal coupled to said output terminal of said first AND gate, a second terminal being an enable terminal, coupled to said input terminal of said FFD and receiving said input signal and an output terminal;a second latch having a first terminal coupled to said output terminal of said first AND gate, a second terminal coupled to said input terminal of said FFD and receiving said input signal and an output terminal; anda first multiplexer having a first terminal coupled to said output terminal of said first latch, a second terminal coupled to said output terminal of said second latch, a third terminal coupled to said input terminal of said FFD and receiving said input signal and an output terminal coupled to said output terminal of said FFD.

7. The FFD according to claim 6, wherein said MCU further comprises: a second AND gate having a first terminal coupled to said output terminal of said FFD and receiving a second feedback signal, a second terminal receiving said FCS and an output terminal;a third latch having a first terminal coupled to said output terminal of said second AND gate, a second terminal being an enable terminal, coupled to said input terminal of said FFD and receiving said input signal and an output terminal;a fourth latch having a first terminal coupled to said output terminal of said second AND gate, a second terminal coupled to said input terminal of said FFD and receiving said input signal and an output terminal;a second multiplexer having a first terminal coupled to said output terminal of said third latch, a second terminal coupled to said output terminal of said fourth latch, a third terminal coupled to said input terminal of said FFD and receiving said input signal and an output terminal; anda third AND gate having a first terminal coupled to said output terminal of said second multiplexer, a second terminal receiving said MCS and an output terminal coupled to said input terminal of said first NOT gate.

8. A fractional frequency divider (FFD) comprising an integer and a fractional moduli and a first and a second states and generating an output signal through dividing a frequency of an input signal, wherein said frequency of said input signal is divided by said integer modulus and a generation of said output signal is not suppressed when said FFD is in said first state, and said frequency of said input signal is divided by said fractional modulus and said generation has a recurring cycle, in which said generation is not suppressed for a time period of said input signal and then suppressed for half of said time period of said input signal, when said FFD is in said second state.

9. The FFD according to claim 8, further comprising: a modulus controlling unit (MCU) generating a modulus selection signal (MSS) in response to a dual-edge triggering (DET) of said input signal and one of said first and said second states; anda frequency dividing unit (FDU) coupled to said MCU and generating said output signal in response to said DET and said MSS,wherein said MSS is in a logic low state when said FFD is in said first state, and said MSS has a recurring cycle, in which said MSS is in a logic low state for a time period of said input signal and then in a logic high state for half of said time period of said input signal, when said FFD is in said second state.

10. A programmable fractional frequency divider (PFFD) generating a first output signal through dividing a frequency of a first input signal by one of a plurality of moduli each having a fractional step size, comprising: a fractional frequency divider (FFD) receiving said first input signal and dividing said frequency of said first input signal by one of a first integer and a fractional moduli in response to a first and a second states respectively so as to generate a second output signal; anda divider chain comprising a plurality of integer frequency dividers (IFDs), having any two neighboring ones of said plurality of IFDs coupled to each other in series, receiving said second output signal and generating said first output signal,wherein each of said plurality of IFDs divides a frequency of a divider input signal by one of a second integer and a third integer moduli in response to a third and a fourth states respectively so as to generate a divider output signal.

11. The PFFD according to claim 10, wherein said FFD is employed to receive one of a plurality of modulus control signals (MCSs) and a feedback control signal (FCS) of said divider chain, and each of said plurality of said IFDs is employed to receive one of said plurality of MCSs and said FCS of each of said plurality of said IFDs.

12. The PFFD according to claim 11, wherein one of one of said plurality of MCSs received by said FFD and said FCS of said divider chain is in a logic low state when said FFD is in said first state, one of said plurality of MCSs received by said FFD and said FCS of said divider chain are both in a logic high state when said FFD is in said second state, one of said FCS of a specific one of said plurality of said IFDs and one of said plurality of MCSs received by said specific IFD is in said logic low state when said specific IFD is in said third state, and one of said plurality of MCSs received by said specific IFD and said FCS of said specific IFD are both in said logic high state when said specific IFD is in said fourth state.

13. The PFFD according to claim 11, wherein a value of one of said plurality of moduli of said PFFD is decided by setting each of said plurality of MCSs in one of said logic high and said logic low states, and said value is ranged from 2N to 2(N+1)−0.5, said step size is 0.5, and said (N+1) is a total number of said plurality of MCSs.

14. The PFFD according to claim 10, wherein said FFD is said FFD as claimed in one of claims 1 and 8.

15. The PFFD according to claim 10, wherein each of said plurality of said IFDs is a 2/3 frequency divider.

16. The PFFD according to claim 10, wherein the first two stages of said FFD and said plurality of said IFDs are two SCL circuits, a remaining part of said plurality of said IFDs are CMOS logic circuits, and there is an interface circuit between said SCL circuits and said CMOS logic circuits.

17. The PFFD according to claim 16, wherein each of said two SCL circuits comprises a plurality of SCL latches and a plurality of SCL multiplexers.

18. A programmable fractional frequency divider (PFFD) having an adjustable modulus range (AMR), receiving an input signal, adjusting said AMR according to a modulus range controlling signal (MRCS) and generating an output signal through dividing a frequency of said input signal by one of a plurality of moduli each having a fractional step size, comprising: a programmable fractional frequency divider (PFFD) circuit dividing said frequency of said input signal by one of said plurality of moduli to generate said output signal, comprising a plurality of integer frequency dividers (IFDs) and having any two neighboring ones of said plurality of IFDs coupled to each other in series; anda modulus range control circuit (MRCC) controlling a turn-on and a turn-off of a feedback control of each of a specific one of said plurality of IFDs and all other said plurality of IFDs following said specific IFD according to said MRCS so as to adjust said AMR.

19. The PFFD according to claim 18, wherein said PFFD is a PFFD as claimed in claim 10 and said MRCC further comprises a plurality of OR gates each having a first, a second and a control terminals, wherein said first and said output terminals are coupled to one of a plurality of feedback loops and each of said plurality of feedback loops is coupled between one of said any two neighboring ones of said plurality of IFDs and said FFD and said plurality of IFDS;a decoder having an input terminal receiving said MRCS and a plurality of output terminals each coupled to said second terminal of one of said plurality of OR gates and outputting one of a plurality of logic low states and a logic high state and a plurality of logic low states, wherein said plurality of IFDs following one of said plurality of output terminals outputs said logic high state are equivalent to be cut off and have no influence on said output signal of said PFFD; anda multiplexer having a plurality of input terminals receiving said MRCS and coupled between one of said any two neighboring ones of said plurality of IFDs and said FFD and said plurality of IFDs and an output terminal outputting said output signal of said PFFD,wherein said multiplexer is employed to select an input signal of one of said plurality of input terminals as said output signal of said PFFD according to said MRC S.

20. A fractional-N phase-locked loop (FNPLL), comprising: a voltage controlled oscillator (VCO) receiving an input signal and generating an output signal; anda programmable fractional frequency divider (PFFD) coupled to said VCO, receiving a feedback signal of said output signal and dividing a frequency of said feedback signal by one of a plurality of moduli having a fractional step size so as to generate a frequency divided output signal.

21. The FNPLL according to claim 20, wherein a frequency of said output signal of said VCO is stabilized at a frequency of a reference signal source multiplied by a mean value of said plurality of moduli.

22. The FNPLL according to claim 20, wherein said PFFD is said PFFD as claimed in claim 10.

23. The FNPLL according to claim 20, wherein said VCO further comprises: a first voltage controlled capacitor (FVCC) having a first terminal coupled to a loop filter (LPF) and adjusting an oscillating frequency of said VCO according to said input signal and a second terminal;a second voltage controlled capacitor (SVCC) having a first terminal coupled to said first terminal of said FVCC and adjusting said oscillating frequency of said VCO according to said input signal and a second terminal;a first inductor having a first terminal coupled to said second terminal of said FVCC and a second terminal coupled to a ground and forming a first resonant cavity with said FVCC;a second inductor having a first terminal coupled to said second terminal of said SVCC and a second terminal coupled to said ground and forming a second resonant cavity with said SVCC;a first capacitor array forming said first resonant cavity with said first inductor and said FVCC, comprising: a plurality of first resonant capacitors each having a first terminal coupled to said first terminal of said first inductor and a second terminal; anda plurality of first switches each having a first terminal coupled to said second terminal of one of said plurality of first resonant capacitors and a second terminal coupled to said ground;a second capacitor array forming said second resonant cavity with said second inductor and said SVCC, comprising: a plurality of second resonant capacitors each having a first terminal coupled to said first terminal of said second inductor and a second terminal; anda plurality of second switches each having a first terminal coupled to said second terminal of one of said plurality of second resonant capacitors and a second terminal coupled to said ground; anda core circuit coupled to said first terminals of said first and said second inductors and generating said output signal of said VCO.

24. The FNPLL according to claim 23, wherein said core circuit further comprises: a first transistor having a first terminal coupled to said PFFD, a second terminal and a control terminal coupled to said second terminal;a second transistor having a first terminal coupled to said PFFD, a second terminal and a control terminal coupled to said control terminal of said first transistor;a first resistor having a first terminal coupled to said second terminal of said first transistor and a second terminal coupled to said ground;a third transistor having a first terminal coupled to said second terminal of said second transistor, a second terminal coupled to said first terminal of said second inductor and a control terminal coupled to said first terminal of said first inductor; anda fourth transistor having a first terminal coupled to said first terminal of said third transistor, a second terminal coupled to said first terminal of said first inductor and a control terminal coupled to said first terminal of said second inductor.

25. The FNPLL according to claim 20, further comprising: a crystal oscillator (XO) generating a reference signal source;a phase frequency detector (PFD) coupled to said XO and said PFFD, comparing a phase and a frequency of said reference signal source and said phase and said frequency of said frequency divided output signal and generating one of a charging signal and a discharging signal accordingly;a charge pump (CP) coupled to said PFD, generating a charging action to raise an output current so as to raise a frequency of said output signal while receiving said charging signal and generating a discharging action to lower said output current so as to lower said frequency of said output signal while receiving said discharging signal;a loop filter (LPF) coupled to said CP and said VCO, filtering a phase noise of said output current of said CP and generating said input signal of said VCO;a delta-sigma modulator (DSM) receiving an external input signal and generating a modulated signal; andan adder coupled to said DSM and said PFFD, receiving an external integer and said modulated signal, adding said external integer and said modulated signal and outputting a sum thereof to said PFFD so as to generate said plurality of moduli.

26. The FNPLL according to claim 25, wherein said XO is a temperature compensated crystal oscillator (TCXO).

27. The FNPLL according to claim 25, wherein said PFD is further employed to receive a polarity control signal (POL), said PFD outputs said charging signal when said POL=1 and said reference signal source leads said output signal, and said PFD outputs said discharging signal when said POL=0 and said output signal leads said reference signal source.

28. The FNPLL according to claim 25, wherein said CP further comprises: a bias current source providing a current bias;a bias circuit coupled to said bias current source and providing a bias voltage;a first output current source coupled to said bias circuit and providing a first output current;a charging switch coupled to said PFD and said first output current source and generating said charging action when said charging signal is received;a discharging switch coupled to said PFD and said first output current source and generating said discharging action when said discharging signal is received;a first control switch coupled to said first output current source and controlling an output current of said CP;a second output current source coupled to said first control switch and providing a second output current;a second control switch coupled to said second output current source and controlling said output current of said CP; anda third output current source coupled to said second control switch and providing a third output current.

29. The FNPLL according to claim 28, wherein said bias circuit is a standard low voltage bias circuit, said output current of said CP is said first output current when said first and said second control switches are both turned off, said output current of said CP is a sum of said first output current and said second output current when said first control switch is turned on and said second control switch is turned off, and said output current of said CP is a sum of said first output current, said second output current and said third output current when said first and said second control switches are both turned on.

30. The FNPLL according to claim 25, wherein said LPF is a third-order LPF.

31. The FNPLL according to claim 30, wherein said third-order LPF further comprises: a first capacitor having a first terminal coupled to said CP and a second terminal coupled to a ground;a first resistor having a first terminal coupled to said first terminal of said first capacitor and a second terminal;a second capacitor having a first terminal coupled to said second terminal of said first resistor and a second terminal coupled to said ground;a second resistor having a first terminal coupled to said first terminal of said first resistor and a second terminal; anda third capacitor having a first terminal coupled to said second terminal of said second resistor and said VCO and a second terminal coupled to said ground.

32. The FNPLL according to claim 25, wherein said DSM is a third-order DSM.

33. The FNPLL according to claim 32, wherein said DSM further comprises: a first first-order DSM receiving said external input signal and generating a first quantization noise and a first output signal;a second first-order DSM coupled to said first first-order DSM, receiving said first quantization noise and generating a second quantization noise and a second output signal;a third first-order DSM coupled to said second first-order DSM, receiving said second quantization noise and generating a third output signal; anda bit manipulation node coupled to said first, said second and said third first-order DSMs, receiving said first, said second and said third output signals and generating said modulated signal.

34. The FNPLL according to claim 33, wherein said first, said second and said third first-order DSMs are 24 bit accumulators.

35. The FNPLL according to claim 33, wherein said first first-order DSM is a 24 bit accumulator, said second first-order DSM is a 16 bit accumulator, and said third first-order DSM is a 8 bit accumulator.

36. A fractional-N phase-locked loop (FNPLL) having an adjustable modulus range (AMR), comprising: an FNPLL circuit receiving an input signal and generating an output signal, comprising: a programmable fractional frequency divider (PFFD) receiving a feedback signal of said output signal and dividing a frequency of said feedback signal by one of a plurality of moduli having a fractional step size so as to generate a frequency divided output signal; anda modulus range control circuit (MRCC) adjusting said AMR formed by said plurality of moduli of said PFFD according to a modulus range controlling signal (MRCS).

37. The FNPLL according to claim 36, wherein said FNPLL circuit is said FNPLL as claimed in claim 25, and said DSM is a third-order DSM.

38. A controlling method of a fractional frequency divider (FFD), comprising one of the steps of: (a) making one of a first modulus control and a first feedback control signals in a first logic low state so as to generate a first modulus selection signal in said first logic low state in response to a dual-edge triggering of a first input signal such that a generation of a first output signal is not suppressed when said FFD is employed in dividing a frequency of said first input signal by an integer modulus; and(b) making one of a second modulus control and a second feedback control signals in a second logic low state so as to generate a second modulus selection signal in said second logic low state in response to a dual-edge triggering of a second input signal such that a generation of a second output signal is not suppressed for a time period of said second input signal, then making both a third modulus control and a third feedback control signals in a first logic high state so as to generate a third modulus selection signal in said first logic high state such that said generation of said second output signal is suppressed for a half of said time period of said second input signal, and recurring in a cycle thereof when said PFD is employed in dividing a frequency of said second input signal by a fractional modulus.

39. The method according to claim 38, wherein said FFD is said FFD as claimed in one of claims 1 and 8.

40. A controlling method of a programmable fractional frequency divider (PFFD), generating a first output signal through dividing a frequency of an input signal by one of a plurality of moduli each having a fractional step size, and comprising a fractional frequency divider (FFD) generating a second output signal and a divider chain coupled to said FFD, comprising a plurality of integer frequency dividers (IFDs), having any two neighboring ones of said plurality of IFDs coupled to each other in series and generating said first output signal, comprising the steps of: (a) making said FFD receive said input signal, one of a plurality of modulus control signals and a feedback control signal of said divider chain and each of said plurality of IFDs receive one of said plurality of modulus control signals and a feedback control signal of said each of said plurality of IFDs;(b) dividing a frequency of said input signal by a first integer modulus to generate said second output signal when one of said modulus control signal of said FFD and said feedback control signal of said divider chain is in a logic low state and dividing said frequency of said input signal by a fractional modulus to generate said second output signal when one of said modulus control signal of said FFD and said feedback control signal of said divider chain is in a logic low state and to last for a time period of said input signal, then both said modulus control signal of said FFD and said feedback control signal of said divider chain are in a logic high state and to last for half of said time period of said input signal, and a cycle thereof is recurring;(c) dividing a frequency of a respective divider input signal of one of said plurality of IFDs by a second integer modulus to generate a respective divider output signal of said one of said plurality of IFDs when one of said modulus control signal and said feedback control signal of said one of said plurality of IFDs is in a logic low state; and dividing said frequency of said respective divider input signal of said one of said plurality of IFDs by a third integer modulus to generate said respective divider output signal of said one of said plurality of IFDs when both said modulus control signal and said feedback control signal of said one of said plurality of IFDs are in a logic high state; and(d) making said PFFD generate said first output signal according to said input signal and said one of said plurality of moduli.

41. The method according to claim 40, wherein said PFFD is said PFFD as claimed in claim 10.

42. A controlling method of a programmable fractional frequency divider (PFFD) having an adjustable modulus range (AMR), generating a first output signal through dividing a frequency of an input signal by one of a plurality of moduli each having a fractional step size, and comprising a fractional frequency divider (FFD) generating a second output signal, a divider chain coupled to said FFD, comprising a plurality of integer frequency dividers (IFDs), having any two neighboring ones of said plurality of IFDs coupled to each other in series and generating said first output signal and a modulus range control circuit (MRCC) adjusting said AMR formed by said plurality of moduli, comprising the steps of: (a) making said MRCC generate a control signal so as to have one of a turn-on and a turn-off of a feedback control of a specific one of said plurality of IFDs and all other IFDs following said specific IFD to adjust said AMR;(b) making said FFD receive said input signal, one of a plurality of modulus control signals and a feedback control signal of said divider chain and each of said plurality of IFDs receive one of said plurality of modulus control signals and a feedback control signal of said each of said plurality of IFDs;(c) dividing a frequency of said input signal by a first integer modulus to generate said second output signal when one of said modulus control signal of said FFD and said feedback control signal of said divider chain is in a logic low state and dividing said frequency of said input signal by a fractional modulus to generate said second output signal when one of said modulus control signal of said FFD and said feedback control signal of said divider chain is in a logic low state and to last for a time period of said input signal, then both said modulus control signal of said FFD and said feedback control signal of said divider chain are in a logic high state and to last for half of said time period of said input signal, and a cycle thereof is recurring;(d) dividing a frequency of a respective divider input signal of one of said plurality of IFDs by a second integer modulus to generate a respective divider output signal of said one of said plurality of IFDs when one of said modulus control signal and said feedback control signal of said one of said plurality of IFDs is in a logic low state; and dividing said frequency of said respective divider input signal of said one of said plurality of IFDs by a third integer modulus to generate said respective divider output signal of said one of said plurality of IFDs when both said modulus control signal and said feedback control signal of said one of said plurality of IFDs are in a logic high state; and(e) making said PFFD generate said first output signal according to said input signal and said one of said plurality of moduli.

43. The method according to claim 42, wherein said PFFD is said PFFD as claimed in claim 18.

44. A controlling method of a fractional-N phase-locked loop (FNPLL), comprising the steps of: (a) making a voltage controlled oscillator (VCO) receive an input signal and generate an output signal; and(b) making a programmable fractional frequency divider (PFFD) receive a feedback signal of said output signal and divide a frequency of said feedback signal by one of a plurality of moduli having a fractional step size so as to generate a frequency divided output signal.

45. The method according to claim 44, further comprising the steps of: (c) making a crystal oscillator (XO) generate a reference signal source;(d) comparing a phase and a frequency of said reference signal source and a phase and a frequency of said frequency divided output signal by a phase frequency detector (PFD) so as to generate one of a charging and a discharging signals;(e) making a charge pump (CP) generate a charging action while receiving said charging signal to raise an output current so as to raise said frequency of said frequency divided output signal and generate a discharging action while receiving said discharging signal to lower said output current so as to lower said frequency of said frequency divided output signal;(f) filtering a phase noise of said output current of said CP by a loop filter (LPF) and generating said input signal of said VCO accordingly;(g) making a delta-sigma modulator (DSM) receive an external input signal and generate a modulated signal;(h) making an adder receive an external integer and said modulated signal, add said external integer and said modulated signal and output a sum thereof to said PFFD so as to generate said plurality of moduli; and(i) making a frequency of said output signal of said VCO stabilize at a product of said frequency of said reference signal source and a mean value of said plurality of moduli after a plurality of operations of said FNPLL.

46. The method according to claim 45 wherein said FNPLL is said FNPLL as claimed in claim 20.

47. A controlling method of a fractional-N phase-locked loop (FNPLL) having an adjustable modulus range (AMR), comprising the steps of: (a) making a voltage controlled oscillator (VCO) receive an input signal and generate an output signal; and(b) making a programmable fractional frequency divider (PFFD) having said AMR receive a feedback signal of said output signal and divide a frequency of said feedback signal by one of a plurality of moduli having a fractional step size so as to generate a frequency divided output signal and adjust said AMR according to a modulus range controlling signal (MRCS) received by said PFFD.

48. The method according to claim 47, further comprising the steps of: (c) making a crystal oscillator (XO) generate a reference signal source;(d) comparing a phase and a frequency of said reference signal source and a phase and a frequency of said frequency divided output signal by a phase frequency detector (PFD) so as to generate one of a charging and a discharging signals;(e) making a charge pump (CP) generate a charging action while receiving said charging signal to raise an output current so as to raise said frequency of said frequency divided output signal and generate a discharging action while receiving said discharging signal to lower said output current so as to lower said frequency of said frequency divided output signal;(f) filtering a phase noise of said output current of said CP by a loop filter (LPF) and generating said input signal of said VCO accordingly;(g) making a delta-sigma modulator (DSM) receive an external input signal and generate a modulated signal;(h) making an adder receive an external integer and said modulated signal, add said external integer and said modulated signal and output a sum thereof to said PFFD so as to generate said plurality of moduli; and(i) making a frequency of said output signal of said VCO stabilize at a product of said frequency of said reference signal source and a mean value of said plurality of moduli after a plurality of operations of said FNPLL.

49. The method according to claim 47, wherein said FNPLL is said FNPLL as claimed in claim 36.