Claims
- 1. A metal oxide silicon semiconductor, comprising:
- a substrate layer having an array of switching elements formed therein, each of the switching elements having outputs selectively connectable to a first external conducting terminal;
- a plurality of deformable conductive gates formed on the upper surface of the substrate, each of said gates in conductive contact with the inputs of an associated one of said switching elements;
- a layer of photosensitive semiconductor material;
- a layer of semiconductor dielectric material formed on the lower surface of said semiconductor layer, said dielectric layer in contact with the surface of said conductive gates opposite said substrate;
- said gates dimensioned such that the upper surface thereof is higher than the highest point on the topography of said substrate;
- a layer of epoxy disposed in the spaces between said gates, the upper exposed surface of said substrate and the exposed lower surface of said dielectric layer; and
- a second external conducting terminal attached to the surface of said semiconductor layer opposite said dielectric layer.
- 2. The metal oxide silicon semiconductor of claim 1 wherein said deformable conductive gates are comprised of Indium alloy.
- 3. The metal oxide silicon semiconductor of claim 1 wherein said semiconductor material comprises mercury cadmium telluride.
- 4. The metal oxide silicon semiconductor of claim 1 wherein said dielectric layer comprises zinc sulfide.
- 5. The metal oxide silicon semiconductor of claim 1 further including an electrically insulating layer in the interstices between said gates.
- 6. The metal oxide silicon semiconductor of claim 2 further including an electrically insulating layer in the interstices between said gates.
- 7. The metal oxide silicon semiconductor of claim 3 further including an electrically insulating layer in the interstices between said gates.
- 8. The metal oxide silicon semiconductor of claim 4 further including an electrically insulating layer in the interstices between said gates.
- 9. The metal oxide silicon semiconductor of claim 5 wherein said gates extend over said electrically insulating layer.
- 10. The metal oxide silicon semiconductor of claim 6 wherein said gates extend over said electrically insulating layer.
- 11. The metal oxide silicon semiconductor of claim 7 wherein said gates extend over said electrically insulating layer.
- 12. The metal oxide silicon semiconductor of claim 8 wherein said gates extend over said electrically insulating layer.
- 13. The metal oxide silicon semiconductor of claim 5 wherein said layer of epoxy is positioned on said electrically insulating layer.
- 14. The metal oxide silicon semiconductor of claim 6 wherein said layer of epoxy is positioned on said electrically insulating layer.
- 15. The metal oxide silicon semiconductor of claim 7 wherein said layer of epoxy is positioned on said electrically insulating layer.
- 16. The metal oxide silicon semiconductor of claim 8 wherein said layer of epoxy is positioned on said electrically insulating layer.
- 17. The metal oxide silicon semiconductor of claim 9 wherein said layer of epoxy is positioned on said electrically insulating layer.
- 18. The metal oxide silicon semiconductor of claim 10 wherein said layer at epoxy is positioned on said electrically insulating layer.
- 19. The metal oxide silicon semiconductor of claim 11 wherein said layer of epoxy is positioned on said electrically insulating layer.
- 20. The metal oxide silicon semiconductor of claim 12 wherein said layer of epoxy is positioned on said electrically insulating layer.
Parent Case Info
This is a division of application Ser. No. 646,659, filed Aug. 31, 1984.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
4447291 |
Schulte |
May 1984 |
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Divisions (1)
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Number |
Date |
Country |
Parent |
646659 |
Aug 1984 |
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