As known in the art, a “stackable switch” is a network switch that can operate independently as a standalone device or in concert with one or more other stackable switches in a “stack” or “stacking system.”
Generally speaking, prior art stacking systems are limited to relatively simple topologies like the ring topology depicted in
Unfortunately, while complex topology support and mixed stacking have clear benefits for users, they can also complicate stacking system administration and management, particularly in instances where an administrator wishes to make topology configuration changes. For example, consider stacking system 200 depicted in
As another example, assume that the administrator attempts to remove the stacking link between high-end switches 202 and 204 from the system's topology configuration as shown in
Techniques for validating configuration changes in a mixed node topology are provided. In one embodiment, a device can identify a link to be removed from a topology comprising a plurality of nodes, where the plurality of nodes includes one or more nodes of a first type and one or more nodes of a second type. The device can then determine whether the removal of the link from the topology would require data traffic between two nodes of the first type to pass through a node of the second type.
The following detailed description and accompanying drawings provide a better understanding of the nature and advantages of particular embodiments.
In the following description, for purposes of explanation, numerous examples and details are set forth in order to provide an understanding of various embodiments. It will be evident, however, to one skilled in the art that certain embodiments can be practiced without some of these details, or can be practiced with modifications or equivalents thereof.
The present disclosure describes techniques for automatically validating configuration changes in a mixed node topology. As used herein, a “mixed node topology” refers to a set of interconnected nodes, where the set includes at least two different node types, and where some of the node types are more “capable” than others (e.g., may support greater bandwidth, a larger number of ports, a higher level of security clearance, etc.). In addition, the set of interconnected nodes includes a master node of the most capable node type. In one set of embodiments, a particular node in the topology (e.g., the master node) can identify a link to be removed from the topology. For example, the master node can receive a user command to remove the link (or a port/trunk associated with the link). The master node can then execute a validation algorithm to ensure that the removal of the link will not cause (1) any node to become unreachable by the master node, and (2) traffic between two nodes to flow through a node that is less capable than either of the two nodes. If the algorithm returns a successful result (indicating that the removal of the link will not cause (1) and/or (2)), the master node can allow the link removal to occur. On the other hand, if the algorithm returns an unsuccessful result (indicating that the removal of the link will cause (1) or (2)), the master node can prevent the link from being removed from the topology.
In certain embodiments, the validation algorithm noted above can be particularly useful when applied to stacking systems that use mixed stacking in combination with complex (e.g., mesh-like) topologies. For example, the algorithm can avoid the problematic scenarios described with respect to stacking system 200 of
In the example of
As discussed in the Background section, there are at least two potential issues that may arise when removing links from a complex, mixed-node topology such as topology 300 of
To address these (and other similar) issues, in various embodiments master node 302 can execute a validation algorithm at the time a link removal is to occur within topology 300 (e.g., at the time an administrator or other agent submits a “remove link” or “remove port” command). In one embodiment, the validation algorithm can check whether the removal of the link will result in any unreachable nodes. In a further embodiment, the validation algorithm can check whether the removal of the link will cause traffic between any two nodes to flow though a less capable node. If the algorithm determines that either of these scenarios will occur, master node 302 can block the link removal from proceeding. In this way, the undesirable consequences associated with these scenarios can be automatically avoided, without any manual intervention by a user or administrator.
It should be noted that this validation algorithm can be applied any arbitrary topology (e.g., ring, linear, mesh, etc.), and is not limited to specific types of topologies. Thus the same algorithm may be used across a variety of different deployments, each having different topological requirements/characteristics. In addition, although topology 300 depicts only two node types for purposes of illustration (i.e., a high-end node type and low-end node type), the validation algorithm may be applied to topologies that have more than two different node types (where each node type has a corresponding “capability” level). In these embodiments, the algorithm can ensure that traffic between any two nodes in the topology (of the same or different node types) will not pass through a node of a less capable type than either of the two nodes.
At block 402, master node 302 can identify a link to be removed from topology 300. For example, in embodiments where topology 300 is a stacking system, master node 302 can receive a user command to remove a particular stacking port or trunk from a stackable switch in the system. Master node 302 can then identify the link to be removed based on the specified port/trunk ID.
At block 404, master node 302 can create a copy of the current topology configuration and remove the link from the copy. Master node 302 can subsequently enter a loop for each endpoint of the link (block 406).
Within the loop of block 406, master node 302 can first create a “node set” and add the current endpoint node as the node set's initial member (block 408). Upon creating the node set, master node 302 can enter a second loop for each node set member (block 410).
Within the second loop of block 410, master node 302 can, for each node directly connected to the current node set member in the copy of the topology configuration, add the node to the node set (block 412). If the node is already part of the node set, it is not added again. In a particular embodiment, as part of the processing of block 412, master node 302 can enforce a restriction where a directly connected node is not added to the node set if the directly connected node is less capable than the current node set member (e.g., the directly connected node is a low-end node and the current node set member is a high-end node). In the context of topology 300 of
Once all of the directly connected nodes for the current node set member have been processed (and added to the node set if appropriate), master node 302 can check whether the node set now includes itself (i.e., the master node) (block 414). In other words, master node 302 can check whether a path has been established from the endpoint node to the master node. If not, the current iteration of loop 410 can end (block 416) and master node 302 can repeat loop 410 in order to recursively process additional members in the node set (including new members added at block 412). If all of members in the node set are processed and the node set still does not include the master node, master node 302 can conclude that there is no viable path from the endpoint node to the master node and can return a “FAIL” result (indicating that the link removal should not be allowed) (block 418).
On the other hand, if the node set does include the master node at some point during loop 410, master node 302 can check whether the current endpoint node (within loop 406) is the last (i.e., second) endpoint node to be processed. If so, master node 302 can conclude there are viable paths between each endpoint node of the removed link and the master node, and can return a “SUCCESS” result (indicating that the link removal should be allowed) (block 424). Otherwise, the current iteration of loop 406 can end (block 422) and master node 302 can repeat loop 406 in order to process the second endpoint node of the removed link. This second iteration of loop 406 will ultimately result in a “FAIL” result per block 418 or a “SUCCESS” result per block 424.
It should be appreciated that the validation algorithm of
In further embodiments, rather than being performed solely by master node 302, portions of flowchart 400 can be performed by other nodes or devices in topology 300. For instance, in a particular embodiment, each endpoint node of the removed link can perform a slightly modified version of blocks 408-424 that returns either a “SUCCESS” result (if the master node is added to the node set for the endpoint node) or a “FAIL” result (if the master node is never added to the node set for the endpoint node). Each endpoint node can then transmit its result to master node 302, which can allow the link removal if both endpoint nodes return “SUCCESS” or block the link removal if either endpoint node returns “FAIL.” One of ordinary skill in the art will recognize many variations, modifications, and alternatives.
To further clarify the operation of the validation algorithm of
Since node 302 is the master node, the algorithm determines that its processing can continue (per blocks 414 and 420), and moves on to creating a node set for second endpoint node 310 (that includes node 310 as its initial member). The algorithm then runs through loop 410 for endpoint node 310, and the node set for endpoint node 310 grows to {310, 312} in the first iteration (note that directly connected node 316 is not added to the node set since node 310 is a high-end node and node 316 is a low-end node). At this point, there are no further nodes in the node set to be processed, and the node set does not include master node 302. Accordingly, the algorithm concludes that there is no viable path between endpoint node 310 and master node 302 and returns a “FAIL” result (thereby blocking the removal of link 326).
Turning now to
Since node 302 is the master node, the algorithm determines that its processing can continue (per blocks 414 and 420), and moves on to creating a node set for second endpoint node 316 (that includes node 316 as its initial member). The algorithm then runs through loop 410 for endpoint node 316, and the node set for endpoint node 316 grows to {316, 310} in the first iteration, {316, 310, 306, 312} in the second iteration, {316, 310, 306, 312, 304, 308} in the third iteration, and {316, 310, 306, 312, 304, 308, 302} in the fourth iteration. Since node 302 is the master node and all endpoint nodes are now processed, the algorithm concludes that there are viable paths between each endpoint node 310, 316 and master node 302 and returns a “SUCCESS” result (thereby allowing the removal of link 332).
As shown, network switch 600 includes a management module 602, a switch fabric module 604, and a number of I/O modules 606(1)-606(N). Management module 602 represents the control plane of network switch 600 and thus includes one or more management CPUs 608 for managing/controlling the operation of the device. Each management CPU 608 can be a general purpose processor, such as a PowerPC, Intel, AMD, or ARM-based processor, that operates under the control of software stored in an associated memory (not shown).
Switch fabric module 604 and I/O modules 606(1)-606(N) collectively represent the data, or forwarding, plane of network switch 600. Switch fabric module 604 is configured to interconnect the various other modules of network switch 600. Each I/O module 606(1)-606(N) can include one or more input/output ports 610(1)-610(N) that are used by network switch 600 to send and receive data packets. As noted with respect to
It should be appreciated that network switch 600 is illustrative and not intended to limit embodiments of the present invention. Many other configurations having more or fewer components than switch 600 are possible.
The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. For example, although certain embodiments have been described with respect to particular process flows and steps, it should be apparent to those skilled in the art that the scope of the present invention is not strictly limited to the described flows and steps. Steps described as sequential may be executed in parallel, order of steps may be varied, and steps may be modified, combined, added, or omitted. As another example, although certain embodiments have been described using a particular combination of hardware and software, it should be recognized that other combinations of hardware and software are possible, and that specific operations described as being implemented in software can also be implemented in hardware and vice versa.
The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense. Other arrangements, embodiments, implementations and equivalents will be evident to those skilled in the art and may be employed without departing from the spirit and scope of the invention as set forth in the following claims.
The present application claims the benefit and priority under 35 U.S.C. 119(e) of U.S. Provisional Application No. 61/825,451, filed May 20, 2013, entitled “FAILSAFE CONFIGURATION VERIFICATION IN A STACKING SYSTEM,” the entire contents of which are incorporated herein by reference for all purposes.
Number | Name | Date | Kind |
---|---|---|---|
4625308 | Kim et al. | Nov 1986 | A |
5481073 | Singer et al. | Jan 1996 | A |
5651003 | Pearce et al. | Jul 1997 | A |
6243756 | Whitmire et al. | Jun 2001 | B1 |
6366582 | Nishikado et al. | Apr 2002 | B1 |
6373840 | Chen | Apr 2002 | B1 |
6490276 | Salett et al. | Dec 2002 | B1 |
6496502 | Fite, Jr. et al. | Dec 2002 | B1 |
6516345 | Kracht | Feb 2003 | B1 |
6526345 | Ryoo | Feb 2003 | B2 |
6597658 | Simmons | Jul 2003 | B1 |
6765877 | Foschiano et al. | Jul 2004 | B1 |
6807182 | Dolphin et al. | Oct 2004 | B1 |
6839342 | Parham et al. | Jan 2005 | B1 |
6839349 | Ambe et al. | Jan 2005 | B2 |
7093027 | Shabtay et al. | Aug 2006 | B1 |
7099315 | Ambe et al. | Aug 2006 | B2 |
7106736 | Kalkunte | Sep 2006 | B2 |
7136289 | Vasavda et al. | Nov 2006 | B2 |
7184441 | Kadambi et al. | Feb 2007 | B1 |
7206283 | Chang et al. | Apr 2007 | B2 |
7206309 | Pegrum et al. | Apr 2007 | B2 |
7274694 | Cheng et al. | Sep 2007 | B1 |
7336622 | Fallis et al. | Feb 2008 | B1 |
7426179 | Harshavardhana et al. | Sep 2008 | B1 |
7480258 | Shuen et al. | Jan 2009 | B1 |
7496096 | Dong et al. | Feb 2009 | B1 |
7523227 | Yager et al. | Apr 2009 | B1 |
7697419 | Donthi | Apr 2010 | B1 |
8209457 | Engel et al. | Jun 2012 | B2 |
9032057 | Agarwal et al. | May 2015 | B2 |
9148387 | Lin et al. | Sep 2015 | B2 |
9185049 | Agarwal et al. | Nov 2015 | B2 |
20010042062 | Tenev et al. | Nov 2001 | A1 |
20020046271 | Huang | Apr 2002 | A1 |
20020101867 | O'Callaghan et al. | Aug 2002 | A1 |
20030005149 | Haas et al. | Jan 2003 | A1 |
20030169734 | Lu et al. | Sep 2003 | A1 |
20030174719 | Sampath et al. | Sep 2003 | A1 |
20030188065 | Golla et al. | Oct 2003 | A1 |
20050063354 | Garnett et al. | Mar 2005 | A1 |
20050271044 | Hsu et al. | Dec 2005 | A1 |
20060013212 | Singh et al. | Jan 2006 | A1 |
20060023640 | Chang et al. | Feb 2006 | A1 |
20060072571 | Navada et al. | Apr 2006 | A1 |
20060077910 | Lundin et al. | Apr 2006 | A1 |
20060092849 | Santoso et al. | May 2006 | A1 |
20060092853 | Santoso et al. | May 2006 | A1 |
20060187900 | Akbar | Aug 2006 | A1 |
20060253557 | Talayco et al. | Nov 2006 | A1 |
20070081463 | Bohra et al. | Apr 2007 | A1 |
20080137530 | Fallis et al. | Jun 2008 | A1 |
20080281947 | Kumar | Nov 2008 | A1 |
20090125617 | Klessig et al. | May 2009 | A1 |
20090135715 | Bennah | May 2009 | A1 |
20100172365 | Baird et al. | Jul 2010 | A1 |
20100185893 | Wang et al. | Jul 2010 | A1 |
20100257283 | Agarwal | Oct 2010 | A1 |
20100284414 | Agarwal et al. | Nov 2010 | A1 |
20100329111 | Wan et al. | Dec 2010 | A1 |
20110238923 | Hooker et al. | Sep 2011 | A1 |
20130215791 | Lin et al. | Aug 2013 | A1 |
20130232193 | Ali et al. | Sep 2013 | A1 |
20130262377 | Agarwal | Oct 2013 | A1 |
20140003228 | Shah et al. | Jan 2014 | A1 |
20140112190 | Chou et al. | Apr 2014 | A1 |
20140112192 | Chou et al. | Apr 2014 | A1 |
20140126354 | Hui et al. | May 2014 | A1 |
20140181275 | Lin et al. | Jun 2014 | A1 |
20140269402 | Vasseur et al. | Sep 2014 | A1 |
20140334494 | Lin et al. | Nov 2014 | A1 |
20140341080 | Lin et al. | Nov 2014 | A1 |
20140376361 | Hui et al. | Dec 2014 | A1 |
20150055452 | Lee | Feb 2015 | A1 |
20150117263 | Agarwal et al. | Apr 2015 | A1 |
20150229565 | Ravipati et al. | Aug 2015 | A1 |
20150281055 | Lin et al. | Oct 2015 | A1 |
20150288567 | Lin et al. | Oct 2015 | A1 |
Number | Date | Country |
---|---|---|
2924927 | Sep 2015 | EP |
2015026950 | Feb 2015 | WO |
Entry |
---|
Amendment to Carrier Multiple Access with Collision Detection (CSMA/CD Access Method and Physical Layer Specifications—Aggregation of Multi[ple Link Segments; IEEE Std. 802.3ad; 2000; 183 pages. |
Appeal Brief Dated Jan. 18, 2013; U.S. Appl. No. 12/463,964 (23p.). |
Brocade: “Fastlron Ethernet Switch”; Administration Guide; Supporting Fastlron Software Release 08.0.00; Apr. 30, 2013; 400 pages. |
Brocade: “Fastlron Ethernet Switch”; IP Multicast Configuration Guide; Supporting Fastlron Software Release 08.0.00; Apr. 30, 2013; 212 pages. |
Brocade: “Fastlron Ethernet Switch”; Stacking Configuration Guide; Supporting Fastlron Software Release 08.0.00; Apr. 30, 2013; 170 pages. |
Brocade: “Fastlron Ethernet Switch”; Traffic Management Guide; Supporting Fastlron Software Release 08.0.00; Apr. 30, 2013; 76 pages. |
Cisco: “Cisco StackWise and StackWise Plus Technology”; technical white paper; C11-377239-01; Oct. 2010; Copyright 2010; 11 pages. |
Cisco: “Delivering High Availability in the Wiring Closet with Cisco Catalyst Switches”; technical white paper; C11-340384-01; Jan. 2007; Copyright 1992-2007; 8 pages. |
Configure, Verify, and Debug Link Aggregation Control Program (LACP); allied Telesyn; 2004; 10 pages. |
Dell: “Stacking Dell PowerConnect 7000 Series Switches”; A Dell Technical White Paper; Jul. 2011; 34 pages. |
DLDP Techology White Paper; H3C products and solutions; 2008; 8 pages; http://www.h3c.com/portal/Products—Solutions/Technology/LAN/Technology—White—Paper/200812/623012—57—0.htm. |
Examiner's Answer Dated May 7, 2013; U.S. Appl. No. 12/463,964 (12 p.). |
Extreme Networks Technical Brief: “SummitStack Stacking Technology”; 1346—06; Dec. 2010; 8 pages . |
Final Office Action Dated Jan. 23, 2012; U.S. Appl. No. 12/463,964 (11 p.). |
Fischer et al.: “A Scalable ATM Switching System Architecture”; IEEE Journal on Selected Areas in Communications, IEEE Service Center, Piscataway, US, vol. 9, No. 8, Oct. 1, 1991; pp. 1299-1307. |
International Search Report and Written Opinion for International Appln. No. PCT/US2013/076251 dated May 22, 2014, 11 pages. |
Juniper Networks datasheet entitled: “Juniper Networks EX 4200 Ethernet Switches with Virtual Chassis Technology”; Dated Aug. 2013 (2120-04300) (12 p.). |
Understanding and Configuring the Undirectional Link Detection Protocol Feature; Cisco support communication; Jul. 9, 2007; Document ID No. 10591; 5 pages; http://www.cisco.com/c/en/us/support/docs/lan-switching/spanning-tree-protocol/10591-77.html. |
Link Aggregation According to IEEE Standard 802.3ad; SysKonnect GmbH; 2002; 22 pages. |
Link Aggregation; http://en.wikipedia.org/wiki/Link—aggregation; downloaded from Internet on Dec. 16, 2013; 9 pages. |
M. Foschiano; Cisco Systems UniDirectional Link Detection (UDLD) Protocol; Memo; Apr. 2008; 13 pages; Cisco Systems. |
Migration from Cisco UDLD to industry standard DLDP; technical white paper; Feb. 2012; 12 pages; Hewlett-Packard Development Company. |
Office Action dated Mar. 21, 2011; U.S. Appl. No. 12/463,964 (10 P.). |
Partial International Search Report for PCT/US2014/051903 dated Nov. 18, 2014. |
Reply Brief Dated Jul. 8, 2013; U.S. Appl. No. 12/463,964 (14 p.). |
Response to Office Action Dated Mar. 21, 2011; U.S. Appl. No. 12/463,964; Response filed Sep. 21, 2011 (12 p.). |
Suckfuell: “Evolution of EWSD During the Eighties”; Institute of Electrical and Electronics Engineers; Global Telecommunications Conference; San Diego; Nov. 28-Dec. 1, 1983; [Global Telecommunications Conference], New York, IEEE, US, vol. 1, Nov. 1, 1983; pp. 577-581. |
U.S. Appl. No. 14/106,302, filed Dec. 13, 2013 by Lin et al. |
U.S. Appl. No. 14/171,152, filed Feb. 3, 2014 by Lin et al. |
U.S. Appl. No. 14/207,146, filed Mar. 12, 2014 by Lin et al. |
U.S. Appl. No. 14/268,507, filed May 2, 2014 by Agarwal. |
U.S. Appl. No. 14/463,419, filed Aug. 19, 2014 by Lee. |
U.S. Appl. No. 14/485,343, filed Sep. 12, 2014 by Lin et al. |
U.S. Appl. No. 14/506,943, filed Oct. 6, 2014 by Lin et al. |
U.S. Appl. No. 14/530,193, filed Oct. 31, 2014 by Ravipati et al. |
U.S. Appl. No. 61/745,396, filed Dec. 21, 2012 by Lin et al. |
U.S. Appl. No. 61/799,093, filed Mar. 15, 2013 by Lin et al. |
U.S. Appl. No. 61/822,216, filed May 10, 2013 by Lin et al. |
U.S. Appl. No. 61/825,449, filed May 20, 2013 by Lin et al. |
U.S. Appl. No. 61/825,451, filed May 20, 2013 by Lin et al. |
U.S. Appl. No. 61/868,982, filed Aug. 22, 2013 by Lee. |
U.S. Appl. No. 61/898,295, filed Oct. 31, 2013 by Agarwal. |
U.S. Appl. No. 61/938,805, filed Feb. 12, 2014 by Ravipati et al. |
U.S. Appl. No. 61/971,429, filed Mar. 27, 2014 by Sinha et al. |
U.S. Appl. No. 61/974,924, filed Apr. 3, 2014 by Lin et al. |
International Search Report and Written Opinion for International Appln. No. PCT/US2014/051903 dated Jan. 27, 2015, 16 pages. |
Final Office Action Dated Feb. 13, 2015; U.S. Appl. No. 13/850,118; (14 p.). |
Continuation U.S. Appl. No. 14/876,639, filed Oct. 6, 2015 by Agarwal et al. |
Notice of Allowance dated Aug. 3, 2015; U.S. Appl. No. 14/207,146 (38 pgs.). |
Pei et al.: “Putting Routing Tables in Silicon”, IEEE Network, IEEE Service Center, New York, NY; vol. 6, No. 1, Jan. 1, 1992; pp. 42-50. |
Hsiao et al.: “A High-Throughput and High-Capacity IPv6 Routing Lookup System”, Computer Networks, Elsevier Science Publishers B.V., Amsterdam, NL, vol. 57, No. 3, Nov. 16, 2012, pp. 782-794. |
Extended European Search Report dated Jul. 30, 2015 for EP Appln. 15000834.0; 8 pages. |
Notice of Allowance dated Sep. 17, 2015; U.S. Appl. No. 14/268,507 (15 pgs.). |
Notice of Allowance dated Oct. 30, 2015; U.S. Appl. No. 13/850,118 (12 pgs.). |
Office Action Dated Nov. 20, 2015; U.S. Appl. No. 14/106,302; (14 pgs.). |
Office Action Dated Feb. 18, 2016; U.S. Appl. No. 14/463,419; (74 pgs.). |
Office Action Dated Feb. 23, 2016; U.S. Appl. No. 14/171,152; (61 pgs.). |
Number | Date | Country | |
---|---|---|---|
20140341079 A1 | Nov 2014 | US |
Number | Date | Country | |
---|---|---|---|
61825451 | May 2013 | US |