1. Field of the Invention
The present invention relates to a constant current source with threshold voltage and channel length modulation compensation, and more particularly to a current source that is applicable to digital-analog converter (DAC).
2. Description of the Related Art
DAC is the most commonly used circuit in integrated circuit (IC) design fields, and can usually be divided into active component type and passive component type. Passive DAC applies resistors or capacitors to complete such a circuit design. Because the passive components have a larger chip thereon, the matching between these passive components has to be taken into consideration. Furthermore, they need to be accompanied with high-efficiency operational amplifiers to have a good performance, so most current circuit designs don't adopt passive components and tend to adopt active components.
The active components generally can be divided into weighted current source, current cell matrix and switched-current modes in the design field of the DAC circuit. All of the above three modes of the active components have current sources formed by a plurality of current source cells, and make use of some switch components to switch current source cells so as to have various signal conversions.
As shown in
However, because the aforementioned circuit makes use of more than one thousand current source cells 11, the homogeneities of the current source cells 11 output current are very important; otherwise, it is impossible to obtain a DAC with a high resolution or high yield ratio.
wherein K1=μnCox/2, μn is electron mobility, Cox is the capacitor value of the unit area, W1 is the channel width of a Metal Oxide Semiconductor (MOS) transistor M1, L1 is the channel length of the MOS transistor M1, Va is the bias voltage of the gate terminal and Vth is the threshold voltage.
From Formula 1, current I1 is variable with the threshold voltage Vth of the MOS transistor M1, so it is unacceptable for a high resolution DAC. In addition, not only the threshold voltage Vth may shift with the manufacture process conditions, but also the great current source cells of a DAC may have a poor PSRR (Power Supply Rejection Ratio; PSRR), which results in a distorted conversion.
To obtain a DAC with a better PSRR, another current source cell 30 is disclosed by Taiwan Patent No.230,284, as shown in FIG. 3. The output current I2 of the current source cell 30 can be simplified into the following formula:
wherein K2 is a constant coefficient same in physics meaning as K1 in Formula 1, W2 is the channel width of MOS transistor M2, L2 is the channel length of a MOS transistor M2, VR1 is a first reference voltage; VDS2 is the relative voltage between the base electrode and source electrode of the MOS transistor M2, λ is a coefficient and the whole term (1+λVDS2) expresses the effect of channel length modulation.
Referring to the formula 2, because VR1 is a constant value, the output current I2 is in proportion to VDS2. However, VDS2 is also variable with the variance of the threshold voltage Vth of the MOS transistor M1. Compared to the current source cell 20 in
However, the current source cell 30 in
The first objective of the present invention is to provide a constant current source with threshold voltage and channel length modulation compensation. A compensation circuit is added in the circuit of a current source cell, and enables a robustness performance in a whole current source that possesses a superior PSRR.
The second objective of the invention is to provide a current source with optimal circuit design. Through adjusting corresponding parameters to minimize the variance of an output current, the current source can be widely applied in the DAC circuit design.
In order to achieve these objectives, the present invention discloses a constant current source with threshold voltage and channel length modulation, which includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor and a fifth MOS transistor. Each of the MOS transistors has a gate terminal, a first terminal and a second terminal. The first terminal of the second MOS transistor is coupled to a loading impedance, and its second terminal is coupled with the first terminal of the first MOS transistor. The gate terminal and the first terminal of the third MOS transistor are coupled together to the gate terminal of the second MOS transistor, and its second terminal is coupled to the first terminal of the fourth MOS transistor. The gate terminal and first terminal of the fourth MOS transistor are coupled to the gate terminal of the first MOS transistor, and its second terminal is coupled to a first reference voltage. The gate terminal and second terminal of the fifth MOS transistor are respectively coupled to a second reference voltage and a third reference voltage, and its first terminal is coupled to the gate terminal and first terminal of the third MOS transistor.
The invention will be described according to the appended drawings in which:
The drain electrode of the second MOS transistor M2 is coupled to the drain electrode of the P-type switch circuit 41. The gate terminal and drain electrode of the third transistor Mb are connected with each other to form a diode, and all are together coupled to the gate terminal of the second MOS transistor M2. The gate terminal of the fourth MOS transistor Mc is coupled to its drain electrode to form a diode, and is also coupled with the gate terminal of the fourth MOS transistor M1. The fourth MOS transistor Mc, the third MOS transistor Mb and the fifth MOS transistor Mp of the compensation circuit 43 are connected in a series to form a reference current Ib. The source electrode of fourth MOS transistor Mc is coupled to a first reference voltage Vr1, while the gate terminal and source electrode of the fifth transistor Mp are respectively coupled to the second reference voltage Vr2 and the third reference voltage Vr3.
The first MOS transistor M1, the second MOS transistor M2, the third MOS transistor Mb, the fourth MOS transistor Mc and the fifth MOS transistor Mp can be N-type MOS transistors (N channel) or P-type MOS transistors (P channel). However, if the polarities of the MOS transistors in
In order to obtain the optimal compensation result of the threshold voltage and the channel length modulation on the cell current source 40, the transistor parameters can be controlled during the manufacture process to reach desired physical characteristics. First, the threshold voltage Vth2 of the second MOS transistor M2 should be decreased to be as low as possible, and the threshold voltages of the second MOS transistor M2 and the third transistor Mb should be kept in consistency (Vthb=Vth2). On the other hand, if the threshold voltages Vth2 and Vthb are decreased, the current Ib passing through the channel of third transistor Mb becomes larger. The fifth transistor Mp can be regarded as a resistor with constant resistance. The bias voltage Vb applied on the gate terminal of the third transistor Mb is decreased, when the current Ib becomes larger. Finally, the decrease of bias-voltage Vb can result in the decrease of bias-voltage VGS2 between the gate terminal and second terminal of the second MOS transistor M2, and a predetermined compensation effect is achieved this way.
In other words, the present invention has a feedback circuit formed by the third MOS transistor Mb and the fourth MOS transistor Mc of the compensation circuit 43 and the first MOS transistor M1 and the second MOS transistor M2 of the cascaded transistor 42 to achieve a low PSRR function.
Output current I1 can be formulated by the following formula:
wherein K1 is a constant as the same physical meaning as K1 in formula 1, W1 is the channel width of the first MOS transistor M1, L1 is the channel length of the MOS transistor M1, Vr1 is the first reference voltage; VDS1 is the relative voltage between the drain electrode and source electrode of the first MOS transistor M1, λ is a coefficient and the whole term (1+λVDS1) expresses the effect of the channel length modulation.
The VDS1 can be denoted by the following formula:
wherein Vth2 is the threshold voltage of the second MOS transistor M2, VOD2 (VOD2=VGS2−Vth2) is the over-driving voltage of the second MOS transistor M2, Kb is the parameter of the third MOS transistor Mb, VGSb is the bias voltage between the gate terminal and second terminal of the third MOS transistor Mb and Ron is the equivalent resistance of the fifth MOS transistor Mp.
The formula 4 is finally simplified as the quadratic parabolic curve of the Vth2 and VDS1, and the most insensitive design range of VDS1 to Vth2 can be obtained through the quadratic parabolic curve. It is determined by
wherein Vth2 (VDS1′min) is the corresponding value of Vth when VDS1 is a minimum.
The most robust current source cell can be obtained through the above-described optimal design considerations. Then, we can use a computer to further analyze and simulate the performances of the optimal current source cell by a Monte-Carlo method. The simulation conditions can assume that Vth1{grave over ( )}Vth2{grave over ( )}Vthb{grave over ( )}Vthc and Vthp all have their Gaussian distribution wit 10% (=3σ) variances, and the variable range of the power supply voltage VDD is from 2.7V to 3.9V. Then, we can obtain 0.15% PSRR as a good performance in comparison with conventional technologies.
The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by persons skilled in the art without departing from the scope of the following claims.
Number | Date | Country | Kind |
---|---|---|---|
92113768 A | May 2003 | TW | national |
Number | Name | Date | Kind |
---|---|---|---|
5517152 | Miki et al. | May 1996 | A |
5598122 | McClure | Jan 1997 | A |
5619166 | Gross | Apr 1997 | A |
5798658 | Werking | Aug 1998 | A |
5936392 | Taylor | Aug 1999 | A |
6008679 | Masuda | Dec 1999 | A |
6081131 | Ishii | Jun 2000 | A |
6320417 | Kirsch et al. | Nov 2001 | B1 |
6515520 | Kiyose | Feb 2003 | B2 |
6587000 | Oikawa | Jul 2003 | B2 |
6621334 | Ausserlechner et al. | Sep 2003 | B2 |
6657485 | Kimura | Dec 2003 | B2 |
Number | Date | Country |
---|---|---|
230284 | Mar 1994 | TW |
Number | Date | Country | |
---|---|---|---|
20040232972 A1 | Nov 2004 | US |