Claims
- 1. A voltage generation circuit, comprising:an external power supply line supplying a first voltage; an internal power supply voltage node from which an internal power supply voltage is output; and a voltage conversion circuit controlling a first current flow supplied from said external power supply line to said internal power supply voltage node to maintain said internal power supply voltage at a target voltage according to a voltage deviation of said internal power supply voltage from said target voltage, said voltage conversion circuit including a switch circuit coupled between said first voltage and an internal node, and turned on according to an activation signal of said voltage generation circuit, an amplify circuit coupled between said internal node and a second voltage, generating a detection deviation signal on a control node, said detection deviation signal having a voltage level according to said voltage deviation within a range from a voltage level of said internal node to said second voltage, a signal conversion circuit driving the voltage level of an output control signal to either one of said first and said second voltages according to the voltage level of said detection deviation signal, and an output current control circuit controlling said first current flow according to the voltage level of said output control signal, wherein said signal conversion circuit setting said output control signal to one of said first and said second voltages, which corresponds to a maximum value of said first current flow, when the voltage level of said detection deviation signal changes from said voltage level of said internal node to said second voltage over a predetermined threshold voltage corresponding to an average of said first and second voltages, and said signal conversion circuit setting said output control signal to the other one of said first and said second voltages, which serves to cut off said first current flow, when the voltage level of said detection deviation signal changes from said second voltage to said voltage level of said internal node over said predetermined threshold voltage.
- 2. The voltage generation circuit according to claim 1, wherein said signal conversion circuit drives the voltage level of said output control signal according to a comparison result between the voltage level of said detection deviation signal and said predetermined threshold voltage,wherein difference between said predetermined threshold voltage and the voltage level of said internal node is smaller than the difference between said predetermined threshold voltage and said second voltage.
- 3. The voltage generation circuit according to claim 1, wherein said signal conversion circuit includes a first inverter and a second inverter driven by said first and said second voltages,said first inverter receiving said detection deviation signal as an input, said second inverter inverting an output of said first inverter to provide said output control signal.
- 4. The voltage generation circuit according to claim 3, wherein said signal conversion circuit further includes a current control transistor electrically coupled between said first inverter and said first voltage, controlling a current flow supplied to said first inverter according to a current control signal received at its gate,wherein said first inverter includes a P type MOS transistor receiving said detection deviation signal at its gate, and electrically coupled between said current control transistor and an input node of said second inverter, and an N type MOS transistor receiving said detection deviation signal at its gate, and electrically coupled between said input node of said second inverter and said second voltage.
- 5. The voltage generation circuit according to claim 1, wherein said signal conversion circuit comprisesa level conversion circuit including a cross-coupled amplifier receiving said detection deviation signal and providing one of said first and said second voltages, and a main inverter inverting the voltage level output from said level conversion circuit to provide said output control signal.
- 6. The voltage generation circuit according to claim 5, whereinsaid cross-coupled amplifier includes a first transistor having a gate coupled to an input node of said main inverter, and electrically coupled between said first voltage and a signal node, and a second transistor having a gate coupled to said signal node, and electrically coupled between said first voltage and said input node of said main inverter; and said level conversion circuit further comprises a third transistor receiving said detection deviation signal at its gate, and electrically coupled between said second voltage and said input node of said main inverter, a fourth transistor electrically coupled between said signal node and said second voltage, and a sub inverter receiving said detection deviation signal as an input, and having an output node electrically coupled to a gate of said fourth transistor.
- 7. The voltage generation circuit according to claim 1, wherein said output current control circuit includes an output transistor receiving said output control signal at its gate, and provided to electrically couple said external power supply line and said internal power supply voltage node, andwherein said voltage conversion circuit further includes an integrating circuit coupled to said signal conversion circuit and said gate of said output transistor for dulling voltage level change of said output control signal, said integrating circuit including a capacitive element electrically coupled between said first voltage and the gate of said output transistor, and a resistance element coupled between said capacitive element and at least one of the gate of said output transistor and said signal conversion circuit.
- 8. The voltage generation circuit according to claim 7, wherein said capacitive element includes a parasitic capacitance formed between a gate electrode of said output transistor and an interconnection layer formed right above said gate electrode,said interconnection layer being coupled to said first voltage.
- 9. The voltage generation circuit according to claim 7, wherein said capacitive element includes an MOS transistor having a gate electrically coupled to the gate of said output transistor, and a source and drain coupled to said first voltage.
- 10. The voltage generation circuit according to claim 1, further comprising a sub voltage conversion circuit controlling a second current flow supplied from said external power supply line to said internal power supply voltage node for maintaining said internal power supply voltage at said target voltage,said sub voltage conversion circuit including a sub switch circuit coupled between said first voltage and a sub internal node, turned on according to said activation signal of said voltage generation circuit, a sub amplify circuit coupled between said sub internal node and said second voltage, generating a sub detection deviation signal having a voltage level according to said voltage deviation within a range from the voltage level of said sub internal node and said second voltage, and a sub output current control circuit controlling said second current flow according to the voltage level of said sub detection deviation signal.
- 11. The voltage generation circuit according to claim 1, further comprising a voltage fixing circuit disconnecting said control node from an input node of said signal conversion circuit, and coupling said input node with a predetermined voltage so as to set said output control signal to the other one of said first and second voltages which serves to cut off said first current flow, when said switch circuit is turned off in response to inactivation of said activation signal.
- 12. The voltage generation circuit according to claim 11, wherein said voltage fixing circuit connects said control node with said input node of said signal conversion circuit when said switch circuit is turned on.
- 13. A voltage generation circuit, comprising:an external power supply line supplying a first voltage; an internal power supply voltage node from which an internal power supply voltage is output; a voltage conversion circuit controlling a first current flow supplied from said external power supply line to said internal power supply voltage node to maintain said internal power supply voltage at a target voltage according to a voltage deviation of said internal power supply voltage from said target voltage, said voltage conversion circuit including a switch circuit coupled between said first voltage and an internal node, and turned on according to an activation signal of said voltage generation circuit, an amplify circuit coupled between said internal node and a second voltage, generating a detection deviation signal on a control node, said detection deviation signal having a voltage level according to said voltage deviation within a range from a voltage level of said internal node to said second voltage, a signal conversion circuit driving the voltage level of an output control signal to one of said first and said second voltages according to the voltage level of said detection deviation signal, and an output current control circuit controlling said first current flow according to the voltage level of said output control signal, said output current control circuit increasing said first current flow as the voltage level of said detection deviation signal changes from said voltage level of said internal node to said second voltage; and a voltage shift circuit generating a reference voltage set lower than said target voltage according to a level of said target voltage and a detection voltage set lower than said internal power supply voltage according to the level of said internal power supply voltage, said amplify circuit setting the voltage level of said detection deviation signal according to a voltage deviation of said detection voltage from said reference voltage.
- 14. The voltage generation circuit according to claim 13, wherein said voltage shift circuit comprisesa first transistor having a gate coupled to said target voltage, and electrically coupled between a first node from which said reference voltage is output and said first voltage, a first resistance element electrically coupled between said first node and said second voltage, a second transistor having a gate coupled with said internal power supply voltage node, and electrically coupled between a second node from which said detection voltage is output and said first voltage, and a second resistance element electrically coupled between said second node and said second voltage.
- 15. The voltage generation circuit according to claim 13, wherein said first voltage is higher than said second voltage,said output current control circuit includes an output transistor which is a P type MOS transistor electrically coupled between said external power supply line and said internal power supply voltage node, and receiving said output control signal at its gate, said switch circuit includes a current control transistor which is a P type MOS transistor electrically coupled between said first voltage and said amplify circuit, and receiving said activation signal at its gate, and wherein said amplify circuit comprises a first P type MOS transistor electrically coupled between said control node and said current control transistor, and having a gate receiving said reference voltage, a second P type MOS transistor electrically coupled between said current control transistor and a sub node, and having a gate receiving said detection voltage, a first N type MOS transistor electrically coupled between said second voltage and said control node, having a gate coupled to said sub node, and a second N type MOS transistor electrically coupled between said sub node and said second voltage, and having a gate coupled to said sub node.
- 16. The voltage generation circuit according to claim 13, further comprising:a first ripple removal circuit electrically coupled between said voltage shift circuit and said voltage conversion circuit for removing an alternating component of said reference voltage, and a second ripple removal circuit electrically coupled between said voltage shift circuit and said voltage conversion circuit for removing an alternating component of said detection voltage.
- 17. A voltage generation circuit, comprising:an external power supply line supplying a first voltage; an internal power supply voltage node from which an internal power supply voltage is output;. a voltage conversion circuit controlling a first current flow supplied from said external power supply line to said internal power supply voltage node to maintain said internal power supply voltage at a target voltage according to a voltage deviation of said internal power supply voltage from said target voltage, said voltage conversion circuits including a switch circuit coupled between said first voltage and an internal node, and turned on according to an activation signal of said voltage generation circuit, an amplify circuit coupled between said internal node and a second voltage, generating a detection deviation signal on a control node, said detection deviation signal having a voltage level according to said voltage deviation within a range from a voltage level of said internal node to said second voltage, a signal conversion circuit driving the voltage level of an output control signal to one of said first and said second voltages according to the voltage level of said detection deviation signal, and an output current control circuit controlling said first current flow according to the voltage level of said output control signal, said output current control circuit increasing said first current flow as the voltage level of said detection deviation signal changes from said voltage level of said internal node to said second voltage; and a voltage shift circuit generating a reference voltage and a detection voltage according to a voltage difference between said target voltage and said internal power supply voltage, said voltage shift circuit generating said reference voltage and said detection voltage such that the voltage difference between said reference voltage and said detection voltage becomes K times (K is a real number larger than 1) the voltage difference between said target voltage and said internal power supply voltage, said amplify circuit setting the voltage level of said detection deviation signal according to a voltage deviation of said detection voltage from said reference voltage.
- 18. The voltage generation circuit according to claim 17, wherein said voltage shift circuit comprisesa first transistor having a gate coupled to a first node from which said detection voltage is generated, and electrically coupled between said second voltage and said first node, a second transistor having a gate coupled to said first node, and electrically connected between a second node from which said reference voltage is generated and said second voltage, a third transistor having a gate to which said activation control signal is applied, and electrically coupled between said first voltage and a third node, a fourth transistor having a gate coupled to said target voltage, and electrically coupled between said second node and said third node, and a fifth transistor having a gate coupled to said internal power supply voltage node, and electrically coupled between said first node and said third node.
- 19. The voltage generation circuit according to claim 17, wherein said first voltage is higher than said second voltage,said output current control circuit includes an output transistor which is a P type MOS transistor receiving said output control signal at its gate and electrically coupled between said external power supply line and said internal power supply voltage node, said switch circuit includes a current control transistor which is a P type MOS transistor electrically coupled between said first voltage and said amplify circuit, and having a gate receiving said activation signal, and wherein said amplify circuit comprises a first P type MOS transistor electrically coupled between said control node and said current control transistor, and having a gate receiving said reference voltage, a second P type MOS transistor electrically coupled between said current control transistor and a sub node, and having a gate receiving said detection voltage, a first N type MOS transistor electrically coupled between said second voltage and said control node, and having a gate coupled to said sub node, and a second N type MOS transistor electrically coupled between said sub node and said second voltage, and having a gate coupled to said sub node.
- 20. The voltage generation circuit according to claim 17, further comprising:a first ripple removal circuit electrically coupled between said voltage shift circuit and said voltage conversion circuit for removing an alternating component of said reference voltage; and a second ripple removal circuit electrically coupled between said voltage shift circuit and said voltage conversion circuit for removing an alternating component of said detection voltage.
- 21. A semiconductor memory device that operates receiving a first voltage, comprising:a memory cell array including a plurality of memory cells arranged in a matrix; a sense amplifier circuit for amplifying data output from a selected memory cell; a plurality of peripheral circuits for controlling a data input/output operation with respect to said memory cell array; each circuit in said semiconductor memory device being divided into a plurality of circuit groups according to a current consumption pattern, a voltage generation circuit receiving said first voltage, and maintaining and supplying an operating voltage at a target voltage for one of said plurality of circuit groups in which said sense amplifier circuit is included, said voltage generation circuit including an external power supply line supplying said first voltage, an operating voltage supply node from which said operating voltage is generated, and a voltage conversion circuit controlling a current flow supplied from said external power supply line to said operating voltage supply node to maintain said operating voltage at said target voltage, said voltage conversion circuit including a switch circuit coupled between said first voltage and an internal node, and turned on according to an activation signal of said voltage generation circuit, an amplify circuit coupled between said internal node and a second voltage, generating a detection deviation signal on a control node, said detection deviation signal having a voltage level according to a voltage deviation of said operation voltage from said target voltage within a range from the voltage level of said internal node to said second voltage, a signal conversion circuit driving the voltage level of an output control signal to either one of said first and said second voltages according to the voltage level of said detection deviation signal, and an output current control circuit controlling said current flow according to the voltage level of said output control signal, wherein said signal conversion circuit setting said output control signal to one of said first and said second voltages, which corresponds to a maximum value of said current flow, when the voltage level of said detection deviation signal changes from said voltage level of said internal node to said second voltage over a predetermined threshold voltage corresponding to an average of said first and second voltages, and said signal conversion circuit setting said output control signal to the other one of said first and said second voltages, which serves to cut off said current flow, when the voltage level of said detection deviation signal changes from said second voltage to said voltage level of said internal node over said predetermined threshold voltage.
Priority Claims (1)
Number |
Date |
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Kind |
11-173044 |
Jun 1999 |
JP |
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RELATED APPLICATIONS
This application is a Continuation-In-Part of U.S. patent application Ser. No. 09/466,670, filed Dec. 20, 1999, incorporated herein by reference and now abandoned.
US Referenced Citations (12)
Foreign Referenced Citations (1)
Number |
Date |
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4-162289 |
Jun 1992 |
JP |
Non-Patent Literature Citations (1)
Entry |
Kiyoo ITO, “Ultra LSI Memory”, Nov. 5, 19094,BAIFUKAN, pp. 267-273. |
Continuation in Parts (1)
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Number |
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Parent |
09/466670 |
Dec 1999 |
US |
Child |
09/954218 |
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US |