The present invention relates to a constant voltage generator circuit such as a low-dropout regulator (hereinafter, referred to as LDO), for example, that operates even with a relatively low input-to-output voltage potential difference.
Conventionally, in a configuration of a power source circuit that switches between a plurality of modes according to polarities of an output voltage value, an output current value, or a terminal application voltage, when a reference voltage source is shared, a voltage potential of one or both of a drain and a source of a transistor connected to the reference voltage source fluctuates during the switching between the modes. During the switching, a parasitic capacitance of the transistor acts as a coupling capacitance, noise is superimposed on the reference voltage source, and a reference voltage changes before and after the switching. As a result, an output voltage of the power source circuit follows the reference voltage, and thus, a change in the output voltage or a change in an output current accompanying the change in the output voltage of the power source circuit occurs. There is such a problem that an unintended mode transition is induced by the change in the output voltage or the change in the output current accompanying the change in the output voltage of the power source circuit, and a malfunction that continues to transition between the modes occurs in the worst case.
As means for avoiding the above malfunction, a method using different reference voltage sources in a circuit in which voltage potential fluctuation occurs and the other circuit so as not to affect an operation of the other circuit is already known. In addition, a method for reducing the parasitic capacitance by reducing a size of the transistor connected to the reference voltage source in which the voltage potential of one or both of the drain and the source fluctuates during the mode switching in order to suppress an absolute value of the noise superimposed on the reference voltage source is also a known fact. Further, as a known technique, there is also a method for giving an offset to a differential amplifier such that the mode switching does not occur by the change in the output voltage of the power source circuit due to the presence of control in which the output voltage of the power source circuit follows the reference voltage when the reference voltage changes before and after the switching or the change in the output current accompanying the change in the output voltage.
For example, Patent Document 1 discloses a series regulator that includes a first amplifier that drives a first transistor connected between a power source and a load, a second amplifier that drives a second transistor connected in parallel to the first transistor, and an amplifier control circuit that controls each of the first amplifier and the second amplifier. In the series regulator, a current capability of the second transistor is set to be smaller than a current capability of the first transistor, and a current consumption of the second amplifier is set to be smaller than a current consumption of the first amplifier. The amplifier control circuit sets a first output current flowing through the first transistor to a zero value in a first load region where an output current flowing through a load is smaller than a predetermined amplifier switching threshold, and controls each of the first amplifier and the second amplifier such that a second output current flowing through the second transistor covers all the output currents. On the other hand, in a second load region where the output current is larger than the amplifier switching threshold, the second output current is set to a zero value or a fixed value smaller than the amplifier switching threshold. In addition, the first amplifier and the second amplifier are controlled such that the first output current covers all of the output currents or a difference obtained by subtracting the second output current from the output current.
However, as the method for avoiding the malfunction that continues to transition between the modes so far, the method using the different reference voltage sources leads to an increase in a chip area and deterioration in accuracy due to a difference in the output voltage between the modes due to a finish variation of the reference voltage source. In addition, in the method for reducing the transistor size, a mismatch between the transistors occurs, and a characteristic variation of a comparator or a differential amplifier increases. As a result, a difference in the output voltage generated between the modes increases, and thus, the accuracy of the output voltage deteriorates. Further, since the method for giving the offset to the differential amplifier requires giving an offset equal to or greater than the noise superimposed on the reference voltage source, there is such a problem that the accuracy of the output voltage deteriorates similarly to the above.
An object of the present invention is to solve the above problems and is to provide a constant voltage generator circuit capable of preventing the malfunction that continues to transition between a plurality of modes while suppressing deterioration in accuracy of the output voltage as compared with the prior art.
According to one aspect of the present invention, there is provided a constant voltage generator circuit including a transistor, a first amplifier circuit, a second amplifier circuit, a protection circuit, and a control circuit. The transistor is connected between a power source and a load, and controls an output current, the first amplifier circuit drives the transistor based on a reference voltage from the power source, and the second amplifier circuit is connected in parallel to the first amplifier circuit, operates at a speed higher than that of the first amplifier circuit, and drives the transistor based on the reference voltage from the power source. The protection circuit is configured to limit an output current flowing through the load from the transistor during a predetermined operation, and the control circuit configured to control an operation of the second amplifier circuit. The control circuit controls the second amplifier circuit not to operate until the output current increases from a current during a light load and reaches a predetermined second threshold current, and to operate when the output current is equal to or greater than the second threshold current, whereas the control circuit controls the second amplifier circuit to operate until the output current decreases from a current during a heavy load and reaches a predetermined first threshold current smaller than the second threshold current, and not to operate when the output current is equal to or less than the first threshold current. The second amplifier circuit further includes a first operation voltage potential fixing circuit that fixes an operation voltage potential of an internal node of the second amplifier circuit during non-operation of the second amplifier circuit.
Accordingly, in accordance with the constant voltage generator circuit according to the present invention, it is possible to suppress the change in the output voltage of the reference voltage source caused by the noise superimposition via the coupling capacitance. As a result, the offset voltage of the differential amplifier can be set to be small, and it is possible to prevent the malfunction in which the power source circuit continues to transition between the plurality of modes while suppressing the deterioration in the accuracy of the output voltage generated as the difference in the output voltage between the modes.
Hereinafter, an embodiment according to the present invention will be described with reference to the drawings. It is noted that, the identical or same constituent elements will be assigned the identical reference characters.
In the series regulator disclosed in Patent Document 1, it has been found that, when the switching of the operation mode occurs, the noise of the differential amplifier is superimposed on the output voltage from the reference voltage source having a high output resistance via the parasitic capacitance of the MOS transistor, and thus, a malfunction of a circuit called switching oscillation in which switching is performed between two operation modes occurs. The following embodiment is intended to prevent this malfunction.
Referring to
The constant voltage generator circuit 2 includes a reference voltage generator circuit 11, a monitoring target node 12, a protection execution circuit 13, a P-channel MOS transistor Q1, a current source 14, three differential amplifier circuits 21, 22, and 23, and a control circuit 10 that controls operations of the differential amplifier circuits 21 and 22.
The reference voltage generator circuit 11 converts the input voltage Vin into a predetermined reference voltage Vref, and outputs the reference voltage. The differential amplifier circuits 21 and 22 are, for example, “differential amplifier circuits with a voltage fluctuation suppression function” having the same circuit configuration, operate at an operation frequency of, for example, 10 MHz to several 100 MHz based on enable signals EN1 and EN2 from the control circuit 10, and operate at a higher speed and higher power consumption than those of the differential amplifier circuit 23. In this case, the differential amplifier circuits 21 and 22 operate in response to the enable signals EN1 and EN2 each having an H level from the control circuit 10, respectively, but do not operate in response to the enable signal EN1 having an L level. In this case, the differential amplifier circuit 21 is a main differential amplifier of the constant voltage generator circuit 2, generates a predetermined constant voltage, and supplies the predetermined constant voltage to the load 4. In addition, the differential amplifier circuit 23 is a sub-differential amplifier of the constant voltage generator circuit 2, generates a predetermined constant voltage, and supplies the predetermined constant voltage to the load 4.
In this case, the differential amplifier circuit 21 configures a main differential amplifier circuit that is dominant in control during a heavy load, and the differential amplifier circuit 22 configures a sub-differential amplifier circuit that is not dominant in control during the heavy load. That is, the two differential amplifier circuits 21 and 22 are operating during the heavy load, the differential amplifier circuit 21 having a large current consumption at this time is the main differential amplifier circuit, and the differential amplifier circuit 22 having a current consumption smaller than that the differential amplifier circuit 21 configures the sub-differential amplifier circuit.
Further, the differential amplifier circuit 22 detects, for example, a voltage of the monitoring target node 12 that changes in voltage in proportion to Vout, and configures a protection circuit that executes protection processing such as limitation of an output current Iout by using, for example, a known brick wall current limitation method or a fold-back current limitation method together with the protection execution circuit 13 including a differential amplifier.
The output terminals of the differential amplifier circuits 21 and 23 and the protection execution circuit 13 are connected to a gate of the MOS transistor Q1 that controls the output current Iout according to a gate voltage, and thus, the differential amplifier circuits 21 and 23 and the protection execution circuit 13 drive the MOS transistor Q1 to control the output current Iout flowing through the MOS transistor Q1. In addition, a positive electrode of the input voltage Vin is grounded via a source and a drain of the MOS transistor Q1 and the current source 14.
(1) As illustrated in
(2) As illustrated in
It is noted that, a relationship among the threshold currents Ith1 to Ith4 is set as follows:
In this case, as a “simple setting example of the threshold current”, the threshold currents may be set such that Ith1=Ith3 and Ith2=Ith4.
Referring to
The bias voltage generator circuit 31 includes a P-channel MOS transistor Q11, an N-channel MOS transistor Q12, and an N-channel MOS transistor Q13, and these MOS transistors Q11, Q12 and Q13 are connected in series. The power source voltage Vin is applied to a source of the MOS transistor Q11, and a gate of the MOS transistor Q11 is connected to a drain thereof. Gates of the MOS transistors Q12 and Q13 are connected to each other and connected to the terminal T5. A connection point P1 between a source of the MOS transistor Q12 and a drain of the MOS transistor Q13 is connected to a connection point P6 between a source of the MOS transistor Q22 and a drain of the MOS transistor Q23 in the differential amplifier 32 via the switch SW11. Further, a source of the MOS transistor Q13 is grounded via the current source 41 via a connection point P2. The connection point P2 is connected to a connection point P7 in the differential amplifier 32 via the switch SW12.
The bias voltage generator circuit 31 having the above-described configuration converts the reference voltage Vref to be applied to the terminal T5 into a predetermined bias voltage, and applies the predetermined bias voltage to the connection point P6 in the differential amplifier 32 via the switch SW11.
The differential amplifier 32 of
The gates of the MOS transistors Q32 and Q33 are connected to each other and are then connected to the terminal T2. The connection point P5 is connected to the gate of the MOS transistor Q34, and the gate of the MOS transistor Q34 is connected to the power source voltage Vin and the source of the MOS transistor Q34 via the switch SW14. A drain of the MOS transistor Q34 is grounded via a connection point connected to the terminal T3, the switch SW3, and the current source 43.
The enable signals EN1 and EN2 to be inputted to the terminal T4 are inputted to control terminals of the switches SW1 to SW3, and inverted enable signals/EN1 and/EN2 to be inputted to the inverter 33 and to be outputted from the inverter 33 are inputted to control terminals of the switches SW11 to SW14. When the enable signals EN1 and EN2 having the H level are inputted to the control terminals of the switches SW1 to SW3, the switches SW1 to SW3 are turned on, and when the enable signals EN1 and EN2 each having the L level are inputted, the switches SW1 to SW3 are turned off. In addition, when the inverted enable signals /EN1 and/EN2 having the H level are inputted to the control terminals of the switches SW11 to SW14, the switches SW11 to SW14 are turned on, and when the inverted enable signals/EN1 and/EN2 each having the L level are inputted, the switches SW11 to SW14 are turned off.
In each of the differential amplifier circuits 21 and 22 having the above-described configuration, when the enable signals EN1 and EN2 having the H level are inputted, the switches SW1 to SW3 are turned on and the switches SW11 to SW14 are turned off. At this time, the differential amplifier 32 enters an operation state in a state where the predetermined bias voltage from the bias voltage generator circuit 31 is not applied to the differential amplifier 32. Accordingly, the differential amplifier 32 subtracts the inverting input voltage INN to be inputted to the inverting input terminal T1 from the non-inverting input voltage INP to be inputted to the non-inverting input terminal T2, and outputs the output voltage obtained by amplifying the voltage of the subtraction result from the terminal T3. It is noted that, the terminal T3 of the differential amplifier circuit 21 is connected to the gate of the MOS transistor Q1 of
In addition, when the enable signals EN1 and EN2 each having the L level are inputted, the switches SW1 to SW3 are turned off and the switches SW11 to SW14 are turned on. At this time, the differential amplifier 32 enters such a non-operation state that the predetermined bias voltage from the bias voltage generator circuit 31 is applied to the differential amplifier 32. Accordingly, the differential amplifier 32 does not perform the differential amplification and is in a stop state without an output from the terminal T3. However, since the predetermined bias voltage is applied, the voltage fluctuations of the connection points P6 and P7 are suppressed, and thus, fluctuations in the gate voltages of the MOS transistors Q22 and Q23 via parasitic capacitances of the MOS transistors Q22 and Q23 are suppressed.
That is, each of the differential amplifier circuits 21 and 22 performs the differential amplification operation during the operation, and does not perform the differential amplification operation during the non-operation. However, at this time, since the predetermined bias voltage is applied to the internal nodes (connection point P6 or P7), it is possible to suppress a fluctuation in the reference voltage.
In a time interval T11 of
As described above, each of the differential amplifier circuits 21 and 22 is configured of the “differential amplifier circuit with the voltage fluctuation suppression function” as illustrated in
In the above embodiment, a stop control circuit that stops the operation of the differential amplifier circuit 22 used for the protection execution circuit 13 when the differential amplifier circuit 22 for the protection execution circuit 13 is in the stopped state, or the bias voltage generator circuit 31 that fixes the bias voltage of the differential amplifier circuit 22 is provided. The present invention is not limited thereto, and these functional circuits may be provided only in the differential amplifier circuit 21 and may not be provided in the differential amplifier circuit 22, or may not have a function of stopping the operation according to the output current by the enable signal EN2 from the control circuit 10.
In the above embodiment, the differential amplifier circuit 23 is configured of a normal differential amplifier circuit without any voltage fluctuation suppression function. The present invention is not limited thereto, and the differential amplifier circuit 23 may be configured of a differential amplifier circuit with the voltage fluctuation suppression function in a manner similar to that of each of the differential amplifier circuits 21 and 22.
In the above embodiment, the MOS transistors Q12 and Q13, the MOS transistors Q22 and Q23, and the MOS transistors Q32 and Q33 are cascode-connected. The present invention is not limited thereto, and may be configured to include only one MOS transistor Q13, one MOS transistor Q23, and one MOS transistor Q33 without any cascode connection.
In the above embodiment, although the differential amplifier circuits 21 and 22 used in the constant voltage generator circuit 2 have been described, first, second, and third modified embodiments of the differential amplifier circuits 21 and 22 will be described below. It is noted that, although differential amplifier circuits 21A, 21B, and 21C will be described below, these configurations may be similarly applied to the differential amplifier circuits 21 and 22.
Hereinafter, the differences will be described.
Referring to
The enable signal EN1 to be inputted to the terminal T4 is inputted to each of the control terminals of switches SW1 to SW3, and is inputted to each of the control terminals of switches SW13 to SW15 via an inverter 33.
In accordance with the differential amplifier circuit 21A having the above-described configuration, the change in the output voltage of the reference voltage source can be suppressed, by generating the bias voltage corresponding to the source voltage potential of the MOS transistor Q13 by the current mirror circuit CM1 during the non-operation, and outputting the bias voltage to the connection point P7 of the differential amplifier 32A.
Accordingly, the differential amplifier circuit 21B is configured to include the internal reference voltage generator circuit 50, the voltage generator circuit 60, and the differential amplifier 32AA. Hereinafter, the differences will be described.
Referring to
The voltage generator circuit 60 includes P-channel MOS transistors Q60 to Q62 and N-channel MOS transistors Q63 and Q64. In this case, the MOS transistors Q51 and Q60 configures a current mirror circuit CM2. In addition, the MOS transistors Q61 to Q64 configures a current mirror circuit. Accordingly, the voltage generator circuit 60 adjusts an output impedance of a constant voltage from the internal reference voltage generator circuit 50 by the current mirror circuit CM2, and outputs the constant voltage to the differential amplifier 32AA.
The enable signal EN1 to be inputted to a terminal T4 is inputted to each of the control terminals of the switches SW1 to SW3, and is inputted to each of the control terminals of the switches SW11, SW13, and SW14 via an inverter 33.
In accordance with the differential amplifier circuit 21B having the above-described configuration, the change in the output voltage of the reference voltage source can be suppressed by generating the bias voltage corresponding to the drain voltage potential of the MOS transistor Q51 by the current mirror circuit CM2 during the non-operation and outputting the bias voltage to the connection point P6 of the differential amplifier 32AA.
Hereinafter, the differences will be described.
The differential amplifier 32B includes switches SW3, SW13, SW14, and SW20, MOS transistors Q21, Q31, Q32, Q33, and Q34, and a current source 43. In this case, the MOS transistor Q34 and the current source 43 configures an output amplifier circuit.
The two parallel transistor circuits 70 and 80 are connected in series between the MOS transistor Q21 and the current source circuit 90. In this case, the parallel transistor circuit 70 includes two MOS transistors Q71 and Q72 and a switch SW21. In addition, the parallel transistor circuit 80 includes two MOS transistors Q81 and Q82 and a switch SW23. Further, the current source circuit 90 includes two current sources 91 and 92 and a switch SW25. Accordingly, when the switches SW21 to SW25 are turned off (during the non-operation of the differential amplifier 32B), a flowing current is smaller than that when the switches SW21 to SW25 are turned on (during the operation of the differential amplifier 32B). In particular, when the differential amplifier 32B is not operated, the small current is caused to flow from the current generator circuit to the internal nodes (the connection points P4, P6, and P7) of the differential amplifier 32B to fix an operation voltage potential. Thus, the change in the output voltage of the reference voltage source is suppressed.
It is noted that, the number of each of the MOS transistors connected to the switches in the parallel transistor circuits 70 and 80 is not limited to one, and may be a plurality of MOS transistors.
In the above-described embodiment and first and second modified embodiments, the predetermined bias voltages are applied from the bias voltage generator circuits 31 and 31A and the voltage generator circuit 60 to the internal nodes of the differential amplifiers 32, 32A, and 32AA, respectively, during the non-operations of the differential amplifiers 32, 32A, and 32AA. Thus, the voltage potential fluctuation of the reference voltage is suppressed by fixing operation voltage potentials of the differential amplifiers 32, 32A, and 32AA (configuring the operation voltage potential fixing circuit). On the other hand, in the third modified embodiment, when the differential amplifier 32B is not operated, a predetermined small current is caused to flow to the internal nodes (the connection points P4, P6, and P7) of the differential amplifier 32B (the current generator circuit) to fix the operation voltage potential (the operation voltage potential fixing circuit is configured), and thus, the voltage potential fluctuation of the reference voltage is suppressed.
In the above embodiment and modified embodiments, the switches SW1 to SW25 are provided. In this case, the switches SW1 to SW25 are configured of semiconductor switch elements made of MOS transistors, for example.
Although the differential amplifiers 32, 32A, and 32B are used in the above embodiment and modified embodiments, the present invention is not limited thereto, and an amplifier that amplifies an input voltage may be used.
As mentioned above in detail, in accordance with the constant voltage generator circuit according to the present invention, it is possible to suppress the change in the output voltage of the reference voltage source caused by the noise superimposition via the coupling capacitance. As a result, the offset voltage of the differential amplifier can be set to be small, and it is possible to prevent the malfunction in which the power source circuit continues to transition between the plurality of modes while suppressing the deterioration in the accuracy of the output voltage generated as the difference in the output voltage between the modes.
Filing Document | Filing Date | Country | Kind |
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PCT/JP2021/019626 | 5/24/2021 | WO |