Patent Grant
7928708
This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2007-120064, filed Apr. 27, 2007, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a constant-voltage power circuit, which supplies a stable voltage with respect to transient variations of a load current.
2. Description of the Related Art
A linear regulator circuit is a so-called constant-voltage power circuit. The linear regulator circuit is largely classified into two; namely, it is composed of a differential amplifier and an output amplifier. In a low drop-out type linear regulator circuit outputting a voltage close to a power supply voltage, a P-type MOS transistor is used as an output transistor in general. However, if the P-type MOS transistor is used as the output transistor, the following problem arises. Specifically, low drop-out is realized, but the output voltage varies with respect to variations of a load current. In order to prevent the foregoing output variations, a large-size capacitor is required as an output transistor. If the constant-voltage power circuit is applied to mobile terminals, circuits of latest mobile terminals are minimized; for this reason, it is desired to make the size of the capacitor small.
According to a first aspect of the present invention, there is provided a constant-voltage power circuit comprising:
a control voltage output circuit receiving a reference voltage and a divided voltage dividing an output voltage, and outputting a control voltage in accordance with the difference between the reference voltage and the divided voltage;
an output circuit receiving the control voltage to generate a stabilized output voltage from a high-potential-side power supply voltage;
a first P-type MOS transistor carrying a current from a node of the output voltage;
a capacitor connected between the node of the output voltage and a supply node of low-potential-side power supply voltage; and
a P-type MOS transistor current control circuit controlling a gate of the first P-type MOS transistor so that a current flowing through the first P-type MOS transistor becomes a constant value.
According to a second aspect of the present invention, there is provided a constant-voltage power circuit comprising:
a control voltage output circuit receiving a reference voltage and a divided voltage dividing an output voltage, and outputting a control voltage in accordance with the difference between the reference voltage and the divided voltage;
an output circuit receiving the control voltage to generate a stabilized output voltage from a high-potential-side power supply voltage;
a first N-type MOS transistor carrying a current into a node of the output voltage;
a capacitor connected between the node of the output voltage and a supply node of low-potential-side power supply voltage; and
an N-type MOS transistor current control circuit controlling a gate of the first N-type MOS transistor so that a current flowing through the first N-type MOS transistor becomes a constant value.
According to a third aspect of the present invention, there is provided a constant-voltage power circuit comprising:
a control voltage output circuit receiving a reference voltage and a divided voltage dividing an output voltage, and outputting a control voltage in accordance with the difference between the reference voltage and the divided voltage;
an output circuit receiving the control voltage to generate a stabilized output voltage from a high-potential-side power supply voltage;
a first P-type MOS transistor carrying a current from a node of the output voltage;
a first N-type MOS transistor carrying a current into a node of the output voltage;
a capacitor connected between the node of the output voltage and a supply node of low-potential-side power supply voltage;
a P-type MOS transistor current control circuit controlling a gate of the first P-type MOS transistor so that a current flowing through the first P-type MOS transistor becomes a constant value; and
an N-type MOS transistor current control circuit controlling a gate of the first N-type MOS transistor so that a current flowing through the first N-type MOS transistor becomes a constant value.
A constant-voltage power circuit according to the reference example will be hereinafter explained before various embodiments of the present invention will be described.
The constant-voltage power circuit shown in
Specifically, as shown in
Various embodiments of the present invention will be hereinafter described. In the following description, the same reference numerals are used to designate common portions over all drawings.
The constant-voltage power circuit according to this embodiment further has a P-type MOS transistor MP2, and a current control circuit (P-type MOS transistor current control circuit) 13. A source of the MOS transistor MP2 is connected to a node of an output voltage Vout, and a drain thereof is connected to ground.
The current control circuit 13 is composed of a constant-current source I1, two P-type MOS transistors MP3 and MP4. One terminal of the constant-current source I1 is connected to ground (supply node of low-potential-side power supply voltage). The foregoing MOS transistors MP3 and MP4 each have gate and drain mutually connected. A current path between source and drain is interposed in series between a supply node of power supply voltage VDD (supply node of high-potential-side power supply voltage) and the other terminal of the constant-current source I1. The gate of the MOS transistor MP2 is connected to the other terminal of the constant-current source I1. According to this embodiment, the current control circuit 13 is provided with two P-type MOS transistors MP3 and MP4. In this case, the current control circuit 13 may be provided with at least one P-type MOS transistor having gate and drain mutually connected.
The current control circuit 13 is a circuit, which generates a control voltage V3 used so that the P-type MOS transistor MP2 connected between the node of the output voltage Vout and ground always carries a constant current. A current value carried from the node of the output voltage Vout by the MOS transistor MP2 determines depending on a threshold voltage Vth (Vth is a negative value) of the MOS transistor MP2 and the gate-source voltage Vgs. If the threshold voltage of the MOS transistor MP2 becomes higher than a design value due to an influence of a manufacturing process (negative value increases), a current flowing through the MOS transistor MP2 is decreased compared with the design value. However, the threshold voltage Vth of the same P-type two MOS transistors MP3 and MP4 becomes high likewise (negative value increases). In order to carry a constant current to the constant-current source I1, a voltage between VDD-V3 becomes large, and thus, the control voltage V3 drops down. The control voltage V3 drops down, and thereby, the gate-source voltage Vgs of the MOS transistor MP2 becomes large, and thus, a current carried by the MOS transistor MP2 increases. Therefore, the threshold voltage Vth becomes high, and the gate-source voltage Vgs becomes high. This serves to offset increase and decrease of the current flowing through the MOS transistor MP2. As a result, the MOS transistor MP2 continues to carry a constant current regardless of variations of the threshold voltage Vth.
Conversely, if the threshold voltage Vth of the MOS transistor becomes lower than a design value (negative value decreases), a current flowing through the MOS transistor MP2 increases compared with the design value. However, in this case, the control voltage V3 drops up, and thus, increase and decrease of the current carried by the MOS transistor MP2 is offset. In other words, the current control circuit 13 controls the value of the control voltage V3 in accordance with variations of the threshold voltage Vth of the P-type MOS transistors MP2. Therefore, the current control circuit 13 can employ various configurations without being limited to the configuration shown in
The operation of the circuit of the first embodiment shown in
Now, when the load current Iload increases while the output voltage Vout drops, the gate-source voltage Vgs of the MOS transistor MP2 decreases. Thus, a current flowing through the MOS transistor MP2 decreases, and an increase of current of the load current Iload is offset. In this way, as seen from the solid line of
Conversely, when the voltage of the output voltage Vout increases while the load current Iload decreases, the gate-source voltage Vgs of the MOS transistor MP2 increases. A current carrying the MOS transistor MP2 increases, and thus, a decrease of the load current Iload flows through the MOS transistor MP2 in excess. In this way, even if the load current Iload decreases, as seen from the solid line of
When the load current Iload increases and a value of the output voltage is decreased less than Vout0, the current flowing through the MOS transistor MP2 decreases from IP20 as seen from
In the constant-voltage power circuit of the first embodiment, even if the output voltage Vout slightly drops down from the power supply voltage VDD, the MOS transistor MP2 turns on. Therefore, this serves to largely prevent variations of the output voltage Vout in transient response time while realizing low drop out. In addition, a capacitor Cload having a large value is not required; therefore, the circuit integration is easy.
The circuit of this embodiment further has an N-type MOS transistor MN1, and a current control circuit (N-type MOS transistor current control circuit) 14. The MOS transistor MN1 has a source connected to the node of the output voltage Vout, and a drain connected to a supply node of power supply voltage VDD.
The current control circuit 14 is composed of a constant-current source I2, two N-type MOS transistors MN2 and MN3. One terminal of the constant-current source I2 is connected to the supply node of power supply voltage VDD (supply node of high-potential-side power supply voltage). The foregoing MOS transistors MN2 and MN3 each have mutually connected gate and drain. A current path between source and drain is interposed in series between the other terminal of the constant-current source I2 and ground (supply node of low-potential-side power supply voltage). The gate of the MOS transistor MN1 is connected to the other terminal of the constant-current source I2. According to the second embodiment, the current control circuit 14 is provided with two N-type MOS transistors MN2 and MN3. In this case, the current control circuit 14 may be provided with at least one N-type MOS transistor having gate and drain connected.
The current control circuit 14 is a circuit, which generates a control voltage V4 used for controlling so that the N-type MOS transistor MN1 connected between the supply node of power supply voltage VDD and the node of the output voltage Vout always carries a constant current. A current value carrying into the node of the output voltage Vout by the MOS transistor MN1 determines by a threshold voltage Vth (positive value) of the MOS transistor MN1 and a gate-source voltage Vgs thereof. If the threshold voltage Vth of the MOS transistor MN1 becomes higher than a design value due to an influence of a manufacturing process (positive value increases), a current flowing through the MOS transistor MN1 decreases compared with the design value. However, the threshold voltage Vth of the same two N-type MOS transistors MN2 and MN3 becomes high likewise. Thus, a voltage between V4-GND becomes large to carry a constant current to the constant-current source I2, and therefore, the control voltage increases. When the control voltage V4 increases, the gate-source voltage Vgs of the MOS transistor Mn1 becomes large. Thus, a current flowing through the MOS transistor MN1 increases. Therefore, the threshold voltage Vth becomes high, and also, the gate-source voltage Vgs becomes high. This serves to offset increase and decrease of a current flowing through the MOS transistor MN1, and the MOS transistor MN1 continues to carry a constant current regardless of variations of the threshold voltage Vth.
Conversely, if the threshold voltage Vth becomes lower than a design value (positive value decreases), a current flowing through the MOS transistor MN1 increases more than the design value. But, in this case, the control voltage V4 drops down, and increase and decrease of a current carried by the MOS transistor MN1 is offset. In other words, the current control circuit 14 controls a value of the control voltage V4 in accordance with variations of the threshold voltage Vth of the N-type MOS transistor. Therefore, the current control circuit 14 is not limited to the configuration shown in
The operation of the circuit of the first embodiment shown in
Now, when the load current Iload increases while the output voltage Vout drops, the gate-source voltage Vgs of the MOS transistor MN1 increases. Thus, a current flowing through the MOS transistor MN1 increases, and an increase of current of the load current Iload is offset. In this way, as seen from the solid line of
Conversely, when the voltage of the output voltage Vout increases while the load current Iload decreases, the gate-source voltage Vgs of the MOS transistor MN1 decreases. A current carrying the MOS transistor MN1 decreases, and thus, a current flowing through the MOS transistor MN1 decreases by a decrease of the current of the load current Iload. In this way, even if the load current Iload decreases, as seen from the solid line of
When the load current Iload increases while a value of the output voltage decreases from Vout0, the current flowing through the MOS transistor MN1 increases from IN10 as seen from
In the circuit of the second embodiment, it is possible to considerably prevent variations of the output voltage Vout in transient response time as in the case of the circuit of the first embodiment shown in
The constant-voltage power circuit of this embodiment further has a P-type MOS transistor MP2, current control circuit (P-type MOS transistor current control circuit) 13 as in the case of
As described in the first and second embodiments, the current control circuit 13 controls a value of a control voltage V3 in accordance with variations of a threshold voltage Vth of the P-type MOS transistor. The current control circuit 14 controls a value of a control voltage V4 in accordance with variations of a threshold voltage Vth of the N-type MOS transistor. In addition, as described in the first and second embodiments, the foregoing current control circuits 13 and 14 may be each provided with at least one P- or N-type MOS transistor having gate and drain mutually connected.
The operation of the circuit of the first embodiment shown in
When the load current Iload increases while the value of the output voltage Vout decreases, a gate-source voltage Vgs of the P-type MOS transistor MP2 decreases. Thus, a current flowing through the P-type MOS transistor MP2 decreases. Likewise, a gate-source voltage Vgs of the N-type MOS transistor MN1 increases. Thus, a current flowing through the P-type MOS transistor MN1 increases. In the circuit of this embodiment, variations of the output voltage Vout when the load current Iload increases is small compared with the circuits of the first and second embodiments by mutually potentiating effect of the P-type MOS transistor MP2 and the N-type MOS transistor MN1.
Conversely, when the load current Iload decreases while the value of the output voltage Vout increases, a gate-source voltage Vgs of the P-type MOS transistor MP2 increases. Thus, a current flowing through the P-type MOS transistor MP2 increases. Likewise, a gate-source voltage Vgs of the N-type MOS transistor MN1 decreases. Thus, a current flowing through the N-type MOS transistor MN1 decreases. In the circuit of this embodiment, variations of the output voltage Vout when the load current Iload decreases is small compared with the circuits of the first and second embodiments by mutually potentiating effect of the P-type MOS transistor MP2 and the N-type MOS transistor MN1.
The constant-voltage power circuit of this embodiment realizes low drop-out characteristic and low power consumption, and considerably prevents variations of the output voltage in transient response time. In addition, a capacitor having a large value is not required as the capacitor Cload; therefore, circuit integration is easy.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-120064 | Apr 2007 | JP | national |
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|---|---|---|---|
| 5838145 | Poon et al. | Nov 1998 | A |
| 7221132 | Okubo et al. | May 2007 | B2 |
| 7221213 | Lee et al. | May 2007 | B2 |
| 7282902 | Chang et al. | Oct 2007 | B2 |
| 7336058 | Lo et al. | Feb 2008 | B1 |
| 7619396 | Chuang et al. | Nov 2009 | B2 |
| Number | Date | Country | |
|---|---|---|---|
| 20080265856 A1 | Oct 2008 | US |
