Patent Application
20140143289
Various products including hard disk drives and transmission systems utilize a read channel device to encode data, store or transmit the encoded data on a medium, retrieve the encoded data from the medium and decode and convert the information to a digital data format. Such read channel devices may include data processing circuits including encoder and decoder circuits or endecs to encode and decode data as it is stored and retrieved from a medium or transmitted through a data channel, in order to reduce the likelihood of errors in the retrieved data. It is important that the read channel devices be able to rapidly and accurately decode the original stored data patterns in retrieved or received data samples.
The encoded data may be constrained to follow one or more rules that reduce the chance of errors. For example, when storing data on a hard disk drive, it may be beneficial to avoid long runs of consecutive transitions, or long runs of 0's or 1's. As the amount of information to be stored or transmitted increases, designing endecs to encode data according to such constraints becomes increasingly difficult and can require complex circuitry using multiplier and divider circuits.
Various embodiments of the present invention provide apparatuses and methods for encoding and decoding data for constrained systems with reduced or eliminated need for hardware and time intensive arithmetic operations such as multiplication and division. In some embodiments, this includes generating a directed graph or digraph DG that characterizes the constraint set for a constrained system, having an approximate eigenvector AE. In order to alleviate the complexity associated with implementation of arithmetic multiplications and divisions for large integers, a representation to a subset of digraph DG is identified that supports codes for which multiplication and division operations take place on integers that are powers of 2. This allows an encoder and a decoder, or an endec, to use much simpler binary shift operations rather than the more complicated multiplication and division operations.
In some embodiments, this includes generating an approximation AE* to the approximate eigenvector AE, such that the number of 1's in the binary representations of AE* coordinates does not exceed a number K. In a stage 1 state splitting operation, digraph DG is split using AE* to generate digraph DG1 with approximate eigenvector AE1 having at most K times as many states as digraph DG, where the weight or coordinate of each state in digraph DG1 is a power of 2. A second stage of state splitting is then performed on digraph DG1 using AE1, yielding a digraph DG2 with approximate eigenvector AE2 having only weights 0 and 1. The encoder/decoder then generated based on digraph DG2 will use multiplication and division operations only on integers that are powers of 2, greatly simplifying the encoder/decoder.
This summary provides only a general outline of some embodiments according to the present invention. Many other objects, features, advantages and other embodiments of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.
A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals may be used throughout several drawings to refer to similar components. In the figures, like reference numerals are used throughout several figures to refer to similar components.
a and 7b depicts a digraph and corresponding 2nd power digraph illustrating another constrained system in accordance with various embodiments of the present inventions;
Various embodiments of the present invention provide apparatuses and methods for encoding and decoding data for constrained systems with reduced or eliminated need for hardware and time intensive arithmetic operations such as multiplication and division. Reducing or eliminating multiplication and division in a constrained system encoder greatly simplifies the hardware design of the encoder and may be achieved with little or no increase in latency.
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In addition, code generation system 300 includes a simulation integrated circuit 306. Simulation integration circuit 306 may be used to implement and test the multiplication and division free constrained system encoder and decoder, including encoding and decoding test data and providing data characterizing the performance of the encoder and decoder, such as incidence of error and latency information. Based upon the disclosure provided herein, one of ordinary skill in the art will appreciate a variety of distributions of work between computer 302 executing instructions and simulation integrated circuit 306.
Although an encoder and decoder generated as disclosed herein are not limited to use in any particular application, they may be used in a read channel of a storage device. Turning to
In a typical read operation, read/write head assembly 420 is accurately positioned by motor controller 412 over a desired data track on disk platter 416. Motor controller 412 both positions read/write head assembly 420 in relation to disk platter 416 and drives spindle motor 414 by moving read/write head assembly to the proper data track on disk platter 416 under the direction of hard disk controller 410. Spindle motor 414 spins disk platter 416 at a determined spin rate (RPMs). Once read/write head assembly 420 is positioned adjacent the proper data track, magnetic signals representing data on disk platter 416 are sensed by read/write head assembly 420 as disk platter 416 is rotated by spindle motor 414. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter 416. This minute analog signal is transferred from read/write head assembly 420 to read channel circuit 402 via preamplifier 404. Preamplifier 404 is operable to amplify the minute analog signals accessed from disk platter 416. In turn, read channel circuit 402 decodes and digitizes the received analog signal to recreate the information originally written to disk platter 416. This data is provided as read data 422 to a receiving circuit. As part of processing the received information, read channel circuit 402 processes the received signal using a multiplication and division free encoder and decoder. A write operation is substantially the opposite of the preceding read operation with write data 424 being provided to read channel circuit 402. This data is then encoded and written to disk platter 416. It should be noted that various functions or blocks of storage system 400 may be implemented in either software or firmware, while other functions or blocks are implemented in hardware.
Storage system 400 may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. Such a RAID storage system increases stability and reliability through redundancy, combining multiple disks as a logical unit. Data may be spread across a number of disks included in the RAID storage system according to a variety of algorithms and accessed by an operating system as if it were a single disk. For example, data may be mirrored to multiple disks in the RAID storage system, or may be sliced and distributed across multiple disks in a number of techniques. If a small number of disks in the RAID storage system fail or become unavailable, error correction techniques may be used to recreate the missing data based on the remaining portions of the data from the other disks in the RAID storage system. The disks in the RAID storage system may be, but are not limited to, individual storage systems such as storage system 400, and may be located in close proximity to each other or distributed more widely for increased security. In a write operation, write data is provided to a controller, which stores the write data across the disks, for example by mirroring or by striping the write data. In a read operation, the controller retrieves the data from the disks. The controller then yields the resulting read data as if the RAID storage system were a single disk.
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Encoding circuit 506 provides encoded data (i.e., original input encoded using the multiplication and division free encoder) to a transmission circuit 510. Transmission circuit 510 may be any circuit known in the art that is capable of transferring the received encoded data via medium 512. Thus, for example, where data processing circuit 500 is part of a hard disk drive, transmission circuit 510 may include a read/write head assembly that converts an electrical signal into a series of magnetic signals appropriate for writing to a storage medium. Alternatively, where data processing circuit 500 is part of a wireless communication system, transmission circuit 510 may include a wireless transmitter that converts an electrical signal into a radio frequency signal appropriate for transmission via a wireless transmission medium. Transmission circuit 510 provides a transmission output to medium 512.
Data processing circuit 500 includes a pre-processing circuit 514 that applies one or more analog functions to transmitted input from medium 512. Such analog functions may include, but are not limited to, amplification and filtering. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of pre-processing circuitry that may be used in relation to different embodiments of the present invention. Pre-processing circuit 514 provides a pre-processed output to a decoding circuit 516. Decoding circuit 516 includes a decoder that is capable of reversing the encoding process applied by encoding circuit 506 to yield data output 520.
A multiplication and division free code for constrained systems which may be encoded and decoded using binary shift operations in place of intensive arithmetic operations such as multiplication and division is generated using directed graphs, or digraphs, which characterize the system constraints. The constraints may, for example, prevent undesirable patterns for a particular storage or transmission medium, such as long runs of 0's or long runs of transitions. A labeled digraph DG=(V, A, L) consists of a finite set of states V=VDG, a finite set of arcs A=ADG where each arc e has an initial state σDG(e)εVDG and a terminal state τDG(e)εVDG, and an arc labeling L=LDG: A→H where H is a finite alphabet. A set of all finite sequences obtained from reading the labels of paths in a labeled digraph DG is called a constrained system, S. DG presents S, denoted by S=S (DG).
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Constraint sequences can be mapped to sequences generated by a labeled DG using symbolic dynamics. In this process, a connectivity matrix is generated for the labeled DG. For the labeled DG 600 of
where element 1,1 represents the connection 612 from state 1 602 to state 1 602, element 1,2 represents the connection 606 from state 1 602 to state 2 604, element 2,1 represents the connection 610 from state 2 604 to state 1 602, and the 0 in element 2,2 represents the lack of a connection from state 2 604 to state 2 604.
The highest rate code that can be designed from a labeled DG can be computed as log(λ), where λ is the largest real and positive eigenvalue of connectivity matrix. For an eigenvalue λ, there is a vector x that satisfies the equation A*x=λ*x, where A is the connectivity matrix, x is a vector, and λ is the eigenvalue number. If the matrix A is non-negative and real, meaning that there are no complex numbers in the connectivity matrix, and that it contains 0's or positive numbers, then λ is also a real, non-negative number that allows the computation of the highest rate code. If the input block length of the encoder is denoted L, and the output block length is denoted N, where N>L, the encoder can be designed to map the L input bits to N output bits in an invertible manner. Given L input bits, there are 2L input patterns to be mapped to outputs. Each of the N blocks are referred to as codewords in a codeword space, generally a subset of all the possible output patterns. The resulting encoder has a rate L/N, and the higher the rate, the greater the efficiency of the encoding.
The labeled DG characterizes the constraints and can be used to calculate the code rate, but does not define the mapping between inputs and outputs. The mapping can be performed using a power of a labeled DG. Turning to
To map input bits to output bits, a DG may be taken to a power based on the rate and on the number of output bits for each input bit. For example, in a ½ rate code, two output bits are produced for every input bit, and the 2nd power 750 of the DG 700 may be used for the mapping. The 2nd power DG 750 of the DG 700 has the same number of states, state i 752 and state j 754. There is an arc from state i 752 to state j 754 in the 2nd power DG 750 if there is a path of length two from state 1 702 to state 2 704 in DG 700. Because state 1 702 to state 2 704 in DG 700 can be reached in two steps on arcs 712 and 706, with labels 0 and 1, 2nd power DG 750 includes an arc 756 labeled 01 from state i 752 to state j 754. Based on the two-step paths in DG 700, 2nd power DG 750 also includes self-loop 760 labeled 01 from state j 754, arc 762 labeled 00 from state j 754 to state i 752, self-loop 764 labeled 00 from state i 752 and self-loop 766 labeled 10 from state i 752. These labels represent the outputs for each state transition from state i 752 and state j 754.
Input bits can be mapped to the paths in 2nd power DG 750 in any suitable manner, including in a somewhat arbitrary manner. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of mapping techniques that may be used to characterize a constrained code from a digraph. Each incoming bit is assigned to a path in 2nd power DG 750, for example assigning incoming bit 1 when received in state i 752 to self-loop 766, so that when a 1 is received in that state, a 10 is yielded at the output. (The notation 1/10 is used in the label for self-loop 766, with the incoming value before the slash and the outgoing value after the slash.) Incoming bit 0 is assigned when received in state i 752 to arc 756 so that when a 1 is received in state i 752, a 01 is output. At this point, with incoming bit values 0 and 1 having been mapped for state i 752, self-loop 764 is not needed. Incoming bit values 0 and 1 when received in state j 754 are assigned to self-loop 760 and arc 762, respectively.
The 2nd power DG 750 when labeled defines the encoder, because it describes fully how input bits are mapped to output bits at a rate 1:2, or code rate ½, in an invertible manner that satisfies the constraint of preventing consecutive 1's.
In this simple example, each state 752 and 754 had sufficient outgoing edges to map each possible input bit. However, given a DG and its powers, this is often not the case. For example, to design a ⅔ code rate encoder based on labeled DG 700, the labeled DG 700 is taken to the 3rd power, yielding connectivity matrix
for the 2nd power and connectivity matrix
for the 3rd power. This indicates that state 1 in the 3rd power DG will have 5 outgoing edges and state 2 in the 3rd power DG will have 3 outgoing edges. Given two input bits in the ⅔ code rate encoder, four outgoing edges are needed from each state, and state 2 has too few outgoing edges, preventing the simple mapping of input to output bits in a power of the original DG as in
State splitting may be used to manipulate the DG to produce another DG that generates the same sequences, but for which every state has at least the necessary number of outgoing edges so that the encoder can be designed by arbitrarily assigning input bits to outgoing edges. State splitting redistributes outgoing edges, taking them from states with an excess and redistributing them to states with insufficient edges until each state has at least the minimum number of outgoing edges to achieve the desired code rate. In general, because λ can be any real number, the x vector may also be a non-integral real number. Given a log(λ) that is at least slightly larger than the desired code rate, a non-negative integer approximate eigenvector can be found that satisfies the equation A*x≧λ*x, where x is a non-negative integer that enables the use of a state splitting algorithm.
In general, state splitting is performed by identifying the largest coordinates of vector x and splitting the corresponding state into a number of smaller states. The outgoing edges from the original state are partitioned into two or more subsets, each of which are assigned to a new state. Each of the new smaller states have the same input as the original state. The resulting digraph thus has more states than the original digraph, with a new approximate eigenvector. In some embodiments, the end result of the state splitting operation is an approximate eigenvector in which every state has a coordinate or weight of 1 or 0, with the number of states equaling the sum of the coordinates of vector x.
If the constraints result in an approximate eigenvector where the sum of the coordinates is a very large number, the resulting encoder can be very complicated, using many multipliers and dividers, which greatly increases hardware complexity. Thus, even when state splitting provides sufficient edges from each state to map input bits to output bits at the desired code rate, traditional mappings may require arithmetic divisions and multiplications for large integers in the encoder. To avoid this, a representation is found for a subset DG* of digraph DG that supports codes that require no multiplication or division, except by powers of 2 that can be performed with binary shift operations.
To identify the subset DG*, the approximate eigenvector AE is generated for digraph DG according to Equation 1:
T(DG)*AE(DG)′≧2L*AE(DG)′ (Eq 1)
where T(DG) is the connectivity matrix for digraph DG and AE(DG)′ is an approximate Eigenvector in row vector form corresponding to digraph DG, transposed to yield a column vector. The left side of Equation 1 is a matrix multiplied by a column vector, resulting in a column vector The right side of Equation 1 is a column vector.
If possible, an approximate eigenvector AE is found that satisfies Equation 2:
T(DG)*AE(DG)′>P+2L*AE(DG)′ (Eq 2)
where P is a real number. Where the largest eigenvector is already 2L, the inequality cannot be satisfied when a real positive number P is added, however, this is uncommon. Because log(λ) is most often a real irrational number, there will be a rational approximation that permits the addition of P.
An approximation AE* to approximate eigenvector AE is identified that satisfies Equation 3:
T(DG)*AE*(DG)′>P*+2L*AE*(DG)′ (Eq 3)
such that the number of 1's in the binary representation of AE*(i) coordinates does not exceed K for all i states, where K is the maximum number of ones in the binary representation of the coordinates of the approximate eigenvector used in the first stage of the state splitting operation. The coordinates of AE* are integers which, when represented in binary, do not have more than K 1's. P* may be smaller than P due to the approximation performed in finding AE*.
State splitting is applied to digraph DG in two stages. In the first stage, digraph DG is split using AE* such that the approximate eigenvector AE1 of resulting digraph DG1 has an Eigenvector coordinate that is a power of 2. More specifically, each state i in digraph DG is split into at most K states having AE1(state(i,j))=λ(i,j), where λ(i,j) is a power of 2. K is equal to 8 in some embodiments but is not limited to any particular value. As shown in
The value for K may be established by selecting a value, splitting every state of digraph DG to up to that selected number of states, and finding the largest eigenvector of the resulting digraph, and if it is large enough to satisfy Equation 4, K is large enough, otherwise, K is increased and the process is repeated. Again, in the first stage state splitting digraph DG is split using AE* such that the approximate eigenvector AE1 of resulting digraph DG1 has an Eigenvector coordinate that is a power of 2:
T1(DG1)*AE1*(DG1)′≧P1*+2L*AE1*(DG1)′ (Eq 4)
where T1 is the connectivity matrix associated with DG1.
More specifically, the first stage state splitting is performed starting with AE*(i)=λ(i). Letting b denote the base 2 representation of λ(i), b=[b(k) b(k−1) b(k−2) . . . b(2) b(1) b(0)], where b's are binary. The location of 1's in b are specified by j's, where j1>j2> . . . >jq for q≦K. States are split from state i with the following weights or AE1 values:
In the second stage of state splitting, the resulting digraph DG1 may be split using AE1 in any suitable manner, such as with a traditional state splitting algorithm, to yield digraph DG2 with approximate eigenvector AE2, where the weights or coordinates of AE2 are all 0's or 1's. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of state splitting algorithms that may be used in relation to different embodiments of the present inventions to split DG1 using AE1 to yield digraph DG2 with approximate eigenvector AE2, where the weights or coordinates of AE2 are all 0's or 1's.
Because the second stage of state splitting begins with an approximate eigenvector AE1 in which all coordinates are powers of 2, multiplication and division operations needed to implement the code in the resulting encoder and decoder will be performed on integers that are powers of 2. This allows binary shift operations to be used rather than multiplication and division operations, greatly simplifying the encoder and decoder.
The encoder and decoder may then be generated in any suitable manner based on DG2, for example using the mapping of inputs to outputs disclosed above with respect to
In general, satisfying Equation 3 is straightforward if P* is large enough, and a large P value promotes a large P*. If Equation 3 is satisfied with K=1, then AE1 can be considered to be another approximate eigenvector for DG. Because Equation 2 uses a greater than inequality, the last step of state splitting will have extra edges that are not needed for encoding, due to the approximation of AE in AE*. Each time edges are discarded in a state splitting operation, there is a danger that too many edges will be discarded and there will be insufficient edges remaining to result in the desired code rate. However, K can be increased to a sufficient level to prevent this outcome, and complexity in the implementation of the encoder and decoder due to K is substantially linear. The value P is a measure of the cushion in the extra edges, and if it gets too small as edges are discarded the design will fail. If an AE* is found with a large P*, there will be a relatively larger number of extra edges that can be discarded during the design process, and this can enable the use of a smaller K.
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In one embodiment of the method for generating a constrained systems endec, DG has 67 states such that the connectivity matrix is a 67×67 integer matrix and each arc is labeled by a 36 bit binary sequence in order to design a rate 34/36 code based on DG. An approximate integer eigenvector AE is set forth in Table 1:
Referring to Equation 2, the value of P for the AE in Table 1 is 0.0249, which is too small to result in the desired code rate. One way to increase P is the following:
Starting from Equation 2: T(DG)*AE(DG)′>P+2L*AE(DG)′
1) let q=(T(DG)*AE(DG)′−2L*AE(DG)′)/2L
2) find a location j in q such that q(j)>1
3) modify AE(DG,j)=AE(DG,j)+1
Repeat step 1 until minimum of q is large enough. Then P equals 2L times the minimum of q.
By increasing P to 67 to provide a larger cushion in the number of edges that can be discarded during the design process, the approximate eigenvector AE is changed to that set forth in Table 2:
In this case, the DG and corresponding approximate eigenvector AE does not have an immediate approximate eigenvector AE* for which coordinates are a power of 2 and satisfying Equation 1 with N=34. Therefore, the first stage state splitting is performed. Although in this case any integers greater than or equal to 7 are candidates for K, and K=8 is selected for ease in state splitting DG to yield DG1. The resulting approximate eigenvectors AE* and AE1 are characterized as follows:
for 1≦i≦67, and 1≦j≦8. Notably, if JB(i,j)=0, there is no state (i,j).
JB(i,j) is given in Table 3, specifying the position of the 1's in AE*(i). Again, the number of 1's in the binary representation of AE*(i) does not exceed K for all i states, in this case in all 8 states.
The location of the 1's in AE*(i) is specified by 2̂35−j. Thus, for state i=1, j=1, Table 3 indicates that the first 1 in state 1 is at 2̂(35−1), or 2̂34. The second 1 in state 1 is at position 2̂(35−4) or 2̂31.
The digraph DG is then split using AE* in a second stage state splitting operation as disclosed above to yield DG1. If P* in Equation 3 is greater than or equal to K, the splitting from DG to DG1 can be performed in one round of state splitting. Thus, because P≧8, the splitting from DG to DG1 can be performed in one round of state splitting, although it is not necessary that this condition be satisfied.
The desired encoder/decoder is then generated by applying the second stage of state splitting from DG1 to DG2, followed by generating the encoder/decoder based on DG2. The resulting 34/36 code can be applied in the encoder and decoder using binary shift operations rather than multiplication and division operations, greatly simplifying the hardware design or computer execution of the encoder and decoder.
It should be noted that the various blocks discussed in the above application may be implemented in integrated circuits along with other functionality. Such integrated circuits may include all of the functions of a given block, system or circuit, or only a subset of the block, system or circuit. Further, elements of the blocks, systems or circuits may be implemented across multiple integrated circuits. Such integrated circuits may be any type of integrated circuit known in the art including, but are not limited to, a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit. It should also be noted that various functions of the blocks, systems or circuits discussed herein may be implemented in either software or firmware. In some such cases, the entire system, block or circuit may be implemented using its software or firmware equivalent. In other cases, the one part of a given system, block or circuit may be implemented in software or firmware, while other parts are implemented in hardware.
In conclusion, the present invention provides novel apparatuses and methods for encoding and decoding data for constrained systems with reduced or eliminated need for hardware and time intensive arithmetic operations such as multiplication and division. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.
The present application claims priority to (is a non-provisional of) U.S. Pat. App. No. 61/728,798, entitled “Constrained System Endec”, and filed Nov. 20, 2012 by Karabed et al, the entirety of which is incorporated herein by reference for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 61728798 | Nov 2012 | US |
