Patent Application
20070023859
The present invention is directed, in general, to fuses for use in integrated circuits.
Fuses are being incorporated with increasing frequency to improve manufacturing yield or to design application specific integrated circuits. Fuses are selectively blown, or programmed, to allow redundant components to replace defective components in the circuit, or to adapt an integrated circuit to perform a specific operation. To program the integrated circuit for a specific task, fuses embedded in the circuit are either kept intact to maintain a conduction path, or blown to create an open circuit, according to a predefined design.
Large numbers of fuses are presently used to implement increasingly sophisticated integrated circuit programming. The implementation of a particular design can require the blowing of thousands of fuses on an integrated circuit die. To obtain high numbers of properly programmed devices, the fuses must be blown with extremely high yield (e.g., 99.99%). Continuing refinements in the materials and process used to fabricate integrated circuits with increasingly smaller and faster transistor components present constant new challenges to fuse designs.
For instance, fuses are typically constructed of the same materials as used to fabricate transistors or other active or passive device components. Changes in the type of polysilicon or metal silicide, or in their thicknesses, doping of other parameters used for transistor fabrication, and hence fuse device fabrication, can dramatically decrease one's ability to blow fuses in high yields. In some cases a high blow yield can be restored by changing the amount or timing of power applied to the fuse. In other cases a different fuse structure must be designed. Both of these measures increase manufacturing costs and delay integrated circuit production.
Accordingly, what is needed in the art is a semiconductor device fuse that can be reliably programmed independent of changes made in transistor manufacturing materials and processes.
To address the above-discussed deficiencies of the prior art, the present invention provides in one embodiment, a semiconductor fuse device. The fuse device comprises a first semiconductor layer that electrically couples the metal layer to a fuse layer. The fuse layer is spaced apart from the metal layer. The fuse device also comprises a second semiconductor layer that forms a blow junction interface with the fuse layer. The blow junction interface is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer to the fuse layer.
Another aspect of the present invention is a method of manufacturing a semiconductor fuse device. First and second semiconductor layers are formed over a substrate. A fuse layer is deposited over the substrate, a portion of the fuse layer being on the first semiconductor layer. The fuse layer forms the above-described blow junction interface with the second semiconductor layer. A metal layer is deposited over the first semiconductor layer, wherein the metal layer is electrically coupled to the fuse layer through the first semiconductor layer and the metal layer is separated from the fuse layer.
Still another embodiment of the present invention is an integrated circuit. The integrated circuit comprises the above-described semiconductor device fuse and microelectronic devices. The semiconductor device fuse is configured to be programmed to interconnect the microelectronic devices and form an operative device.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the scope of the invention.
For a more complete understanding of the present invention, reference is now made to the following detailed description taken in conjunction with the accompanying figures. It is emphasized that various features may not be drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion. In addition, it is emphasized that some circuit components may not be illustrated for clarity of discussion. Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
As part of the present invention it was discovered that incorporating a metal contact into a fuse device results in a fuse that can be blown with high reliably. Moreover such a fuse is robust to variations in transistor manufacturing processes provided that the construction of the metal contact remains substantial unaltered. There remains a concern, however, that blowing a metal contact directly connected to a metal layer could compromise the metal layer, with resulting negative consequences.
For instance, blowing a metal contact directly coupled to a barrier-lined metal layer might disrupt a tantalum barrier layer of the metal layer. A disrupted barrier could allow free copper in the metal layer to diffuse into the silicon substrate or silicon-containing intrametal or interlayer dielectrics, with resultant degradation in the long-term reliablity of active devices in the integrated circuit. The present invention obviates these concerns by providing a semiconductor device fuse that leverages the reliable blow properties of a metal contact while reducing the risk that blowing the fuse could damage the metal layer.
One embodiment of the present invention is a semiconductor device fuse.
The semiconductor device fuse 100 further comprises a second semiconductor layer 120 that forms a blow junction interface 125 with the fuse layer 115. The blow junction interface 125 is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer 120 to the fuse layer 115. One of ordinary skill in the art would be familiar with how to select the appropriate power to transmit so that the energy density of the blow junction interface 125 is exceeded with consequent melting or vaporization.
In some cases the metal layer 105 preferably comprises a copper layer surrounded by a tantalum barrier layer. One of ordinary skill in the art would be familiar with other suitable materials for the metal layer 105. For instance the metal layer 105 could alternately comprise an aluminum layer surrounded by a titanium-tungsten or titanium-nickel barrier layer. Other embodiments of the metal layer 105 can comprise gold or platinum.
It is advantageous for the first semiconductor layer 110 to be located between the metal layer 105 and the fuse layer 115 so that applying power to the fuse layer 115 does not cause excessive heating of the metal layer 105. In the context of the present invention excessive heating is defined as an increase in temperature that is sufficient to alter the structure of the metal layer 105. Melting a barrier layer of the metal layer 105 is one example of how excessive heating could alter the structure the metal layer 105. The first and second semiconductor layers 110, 120 can be made of the same or different semiconductor materials. Examples of suitable materials for the semiconductor layers 110, 120 comprise doped silicon or polysilicon; other suitable materials would be readily apparent to those of ordinary skill in the art. Preferably the first and second semiconductor layers 110, 120 are electrically isolated from each other, for example by being separated from each other.
Preferred embodiments of the fuse layer 115 comprise tungsten. However, the fuse layer 115 can also comprise tungsten alloys or other metals conventionally used to form conventional metal contacts in an integrated circuit. The blow junction interface 125 refers to the location where the fuse layer 115 contacts the second semiconductor layer 120. A suitable power is transmitted through the second semiconductor layer 120 to the fuse layer 115 to melt or vaporize portions of the second semiconductor layer 120 or fuse layer 115 at the interface 125, resulting in the formation of an open circuit between the fuse layer 115 and the second semiconductor layer 120.
To help ensure that an open circuit is formed at the blow junction interface 125, it is desirable to configure the resistances of all interfaces of the various components of the fuse 100 to be lower than that of the blow junction interface 125. In some advantageous embodiments, a lower resistance is achieved by making the area of these interfaces greater than the area of the blow junction interface 125. As an example, it is preferable for an area of the blow junction interface 125 to be less than an area of an interface 130 between the first semiconductor layer 110 and the fuse layer 115. More preferably the area of the blow junction interface 125 is at least about five times lower than the area of the interface 130. Preferably there are metal contacts 135 between the first semiconductor layer 110 and the metal layer 105, and between the second semiconductor layer 120 and an additional metal layer 140. To lower their resistance, it desirable for areas of interfaces 145 between the first and second semiconductor layers 110, 120 and the metal contacts 135 to be larger, and preferably at least about five times larger, than the area of the blow junction interface 125. Analogous relative area considerations apply to the interfaces 150 between the metal contacts 135 and metal layers 105, 140.
Some preferred embodiments of the semiconductor device fuse of the present invention further comprise redundant features, such as additional metal layers, and metal contacts between the metal layers and the semiconductor layers. These and other advantageous features are illustrated in
In some cases such as illustrated in
As illustrated in
As further illustrated in
As illustrated in
Similar to that discussed above, to ensure that the open circuit is formed at the blow junction interface 125, it is desirable to minimize the resistances between the metal layer 140 and second semiconductor layer 120 and any metal contacts 135 located there-between. For example, in some preferred embodiments of the fuse device 100, the area of the blow junction interface 125 is less than the area of the interfaces 230, 232 (or total area of the interfaces 230, 232 when a plurality of contacts 135 are used) between the metal contacts 135 and the additional metal layer 140 and second semiconductor layer 120.
To increase the areas of these interfaces 230, 232, it is advantageous for the fuse device 100 to comprise redundant features such as the additional metal layer 140 and a matching additional metal layer 235, coupled to the second semiconductor layer 120 and a matching semiconductor layer 240, respectively. In some preferred embodiments the additional metal layer 235 is coupled to a power source 245 configured to transmit or not transmit a predefined power through the matching semiconductor layer 240 to the fuse layer 115 (
As further illustrated in
Such symmetrical configurations beneficially reduce the likelihood that the area of the blow junction interface 125 will be altered by slight misalignments between the semiconductor layers 110, 120, 215, 240 and the fuse layer 115 during fuse fabrication. Device-to-device variation in the area of the blow junction interface 125 is undesirable because this could alter the amount of power required to form an open circuit, thereby reducing the yield of blowing a plurality of device fuses 100 when programming an integrated circuit.
In some preferred embodiments, such as shown in
For example, consider a scenario where the fuse device 200 is formed such that the fuse layer 115 is not exactly centered over the contiguous semiconductor layer 250. So long as the fuse layer 115 still overlaps with the narrow portion 250, the area of the blow junction interface 125 will not be affected by the misalignment.
Additionally, as illustrated in
Another aspect of the present invention is a method of manufacturing a semiconductor fuse device. Any of the above-discussed semiconductor fuse devices can be manufactured by the method.
Turning first to
The substrate 525 can comprise any conventional semiconductor substrate material used in semiconductor device fabrication. For instance, in certain preferred embodiments, the substrate 525 is a silicon wafer, such as single-crystalline silicon. In other instances the substrate 525 can comprise various layers such as insulating layers to electrically or thermally insulate the fuse device 200 from other components in an integrated circuit (not shown).
Referring to
As further illustrated in
With continuing reference to
As illustrated in
As discussed above, the blow junction interface 125 is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer 120 to the fuse layer 115. Also as discussed above, to ensure that the open circuit is formed at the blow junction interface 125, it is preferable to make the area of the blow junction interface 125 smaller than the area of the portion 705 of the fuse layer 115 that is on the first or other semiconductor layers 110, 215.
As further illustrated in
Turning now to
The metal layer 105 is electrically coupled to the fuse layer 115 through the first semiconductor layer 110, and the metal layer 105 is separated from the fuse layer 115. In some preferred embodiments such as depicted in
As further shown in
Turning now to
Turning to
As further depicted in
As further illustrated in
As illustrated in
Yet another aspect of the present invention is an integrated circuit.
The integrated circuit 1300 comprises a substrate 1302 over which are formed microelectronic devices 1305 and one or more semiconductor device fuse 1310. As illustrated in
Any of the above-described semiconductor fuse devices and their method of manufacture can be incorporated into the construction of a plurality of semiconductor device fuses 1310 of the integrated circuit 1300. Each device fuse 1310 comprises a metal layer 1315 and a first semiconductor layer 1320 that electrically couples the metal layer 1315 to a fuse layer 1325, wherein the fuse layer 1325 is spaced apart from the metal layer 1315.
The device fuse 1300 further comprises a second semiconductor layer 1330 that forms a blow junction interface 1335 with the fuse layer 1325. The blow junction interface 1335 is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer 1330 to the fuse layer 1325. To promote forming the open circuit at the blow junction interface 1335, it is preferable that an area of the blow junction interface 1335 is less than an area of an interface 1337 between the first semiconductor layer 1320 and the fuse layer 1325.
As further illustrated in
As discussed previously, some preferred embodiments of the semiconductor device fuse 1300 comprise a second metal layer 1350 that is electrically coupled to the fuse layer 1325 through the second semiconductor layer 1330. In other preferred embodiments, to facilitate electrical coupling, one or more metal contacts 1355 are located between the first semiconductor layer 1320 and metal layer 1315 or between the second semiconductor layer 1330 and second metal layer 1350. Of course the integrated circuit 1300 can further comprise additional metal contacts 1360 and metal layer 1365 to interconnect the microelectronic devices 1305 and form an operative device.
Each semiconductor device fuse 1310 is configured to be programmed to thereby interconnect the microelectronic devices 1305 to form an operative device, such as a programmed read-only memory (PROM) device. For instance, in some embodiments, the metal layer 1315 and second metal layer 1350 comprise portions of a first layer of metallization in the integrated circuit 1300. In such cases, the metal layer 1315 and second metal layer 1350 are configured to interconnect the microelectronic devices 1305. Of course, the semiconductor device fuse 1310 can also be located at higher layers of metallization and insulation of the integrated circuit, if desired.
In some instances, the semiconductor device fuse 1300 is programmed by leaving the blow junction interface 1335 intact, thereby maintaining the interconnection between the microelectronic devices 1305. In other instances the semiconductor device fuse 1300 is programmed by sending a pulse of power to the blow junction interface 1335 to form an open circuit, thereby breaking the interconnection between the microelectronic devices 1305.
Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the scope of the invention in its broadest form.
