Claims
- 1. A method of forming a contact on an n-type III-V semiconductor comprising the steps of:(a) depositing Al on the n-type III-V semiconductor to provide a base layer; then (b) depositing Ti on said base layer to provide a first barrier layer; then (c) depositing Pt on said first barrier layer to provide a second barrier layer; then (d) depositing Au on said second barrier layer to provide a top layer, whereby said base layer, said first barrier layer, said second barrier layer, and said top layer form a stack on the n-type semiconductor; and then (e) annealing said n-type III-V semiconductor with said stack thereon.
- 2. A method as claimed in claim 1 wherein said annealing step is performed at about 400-600° C.
- 3. A method as claimed in, claim 2 wherein said annealing step is performed for between about 1 minute and about 10 minutes.
- 4. A method as claimed in claim 2 wherein said annealing step is performed for about 3 minutes.
- 5. A method as claimed in claim 4 wherein said annealing step is performed at about 500° C.
- 6. A method as claimed in claim 1 wherein said first barrier layer is at least about 300 Å thick.
- 7. A method as claimed in claim 6 wherein said first barrier layer is about 390 Å to about 410 Å thick.
- 8. A method as claimed in claim 6 wherein said deposited Al is between about 190 Å to about 210 Å thick.
- 9. A method as claimed in claim 6 wherein said second barrier layer is about 490 Å to about 510 Å thick.
- 10. A method as claimed in claim 6 wherein said top layer is at least about 6000 Å thick.
- 11. A method as claimed in claim 1 wherein said n-type semiconductor is a nitride compound semiconductor.
- 12. A method as claimed in claim 1 wherein said n-type semiconductor is a pure nitride compound semiconductor.
- 13. A method as claimed in claim 11 wherein said n-type semiconductor is a gallium nitride based semiconductor.
- 14. A method as claimed in claim 11 wherein said n-type semiconductor is GaN.
- 15. A method as claimed in claim 1 wherein said Al/Ti/Pt/Au contact has a contact resistance of less than about 10−5 ohm-cm2.
- 16. A method as claimed in claim 1 wherein said base layer is about 20 nm thick.
- 17. A method as claimed in claim 1 wherein said base layer is less than about 50 nm thick.
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application claims benefit of U.S. Provisional Patent Application No. 60/238,221, filed Oct. 5, 2000, the disclosure of which is hereby incorporated by reference herein. The present application is also a continuation-in-part of U.S. patent application Ser. No. 09/692,953 Oct. 20, 200, the disclosure of which is hereby incorporated by reference herein.
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Date |
Kind |
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A |
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A |
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Non-Patent Literature Citations (1)
Entry |
Lin et al., “Low Resistance Ohmic Contacts on Wide Bank Cap GaN,” 64(8) Applied Physics Letters, Feb. 1994, pp. 1003-1005. |
Provisional Applications (1)
|
Number |
Date |
Country |
|
60/238221 |
Oct 2000 |
US |
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09/692953 |
Oct 2000 |
US |
Child |
09/971965 |
|
US |