Patent Application
20080007365
Various embodiments and aspects of the invention are described in detail below with reference to the accompanying figures. It is to be appreciated that the accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. In the drawings:
According to aspects and embodiments of the invention, there is provided a frequency synthesizer capable of wideband operation and that may include a method of gain compensation that may not require external calibration sequences, as well as a method of fast VCO band selection. To facilitate wideband operation, embodiments of the frequency synthesizer may include switchable independent loop filters that may allow the frequency synthesizer to accommodate significant changes in bandwidth. In addition, there are disclosed methods of gain compensation and VCO band selection, as well as a fast, wideband programmable divider configuration that may be used in embodiments of frequency synthesizers according to the invention.
It is to be appreciated that this invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways, and the invention is not limited to the examples presented unless specifically recited in the claims. In addition, it is to be appreciated that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of the words “including,” “comprising,” “having,” “containing,” or “involving,” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
Referring to
In one embodiment, the frequency synthesizer may further include a sigma-delta modulator 150 for modulating a data signal (containing data to be transmitted) onto a carrier frequency generated by the frequency synthesizer. A carrier signal produced by the frequency synthesizer, herein referred to as Fvco on line 154, may be directly modulated by providing a path for data modulation through the Sigma-Delta modulator 150. By summing (either in a summer 156 or in the sigma-delta modulator itself) properly formatted and clocked data on line 158 (referred to as data path one) with a constant frequency control word provided on line 160, the data signal can be superimposed on the carrier signal at the frequency synthesizer output. This may have the benefit of being a relatively simple method of modulation, which may reduce the overall complexity (by reducing the number of component blocks) of, for example, a transmitter in which the frequency synthesizer may be used. Fewer components may reduce the overall power consumption of the device, which may also be desirable. The frequency control word may be supplied, for example, by a microcontroller (not shown) that may be coupled to the frequency synthesizer.
According to one embodiment, the frequency synthesizer may use Two-Point Modulation, in which the same data signal is also fed to the VCO 138 via a second data path (data path two). The digital data signal on line 162 may pass through a digital-to-analog converter 164 to be converted to an analog signal that may be fed, via a variable gain amplifier 166, to the VCO 138. As discussed above, by using two data paths, one with a low pass filter response (i.e., the path that passes through the loop filter 146 of the phase locked loop) and a second path with a high pass filter response (data path two), the superposition of the signals from both data paths onto the carrier signal generated by the frequency synthesizer can yield a flat wideband response for the modulated data on the carrier signal at the frequency synthesizer output. In order for the overall frequency response of the data modulating the carrier frequency to remain flat, (i.e. undistorted), the variable gain G of the variable gain amplifier should meet the requirement: G=Fref/Kv2, where Kv2 is the value of the gain (in units of MHz/V) of the auxiliary VCO port 170 in data path two. Kv2 is a quantity that may experience variations due to changes in circuit operating conditions, for example, fluctuations in temperature and supply voltage. It may therefore be desirable that the value of G continuously tracks Kv2 to account for any such variations.
According to one embodiment of the invention, there is provided a frequency synthesizer that may involve no extra calibration sequences and takes advantage of the realization that all the information necessary for continually adjusting the gain of data path two may be already present in the system. Under ideal system conditions, where the gain G is perfectly calibrated, introducing a data signal into both data paths, as discussed above, may result in a signal at the primary VCO control port 172 having a gain setting Kv1, which may be perfectly flat. If, however, there is a mismatch between the setting of the gain G, and the value of Fref/Kv2, there will be some residual data signal observable on the main control port 172 of the VCO 138. If the gain G is too small, the residual signal on the main control port 172 may exhibit a directly proportional correlation with the input data. Alternatively, if the gain G is too large, then the residual signal on the main control port 172 may exhibit an inversely proportional correlation with the input data. Based on this information and knowledge of the input data, a feedback control system can be developed that monitors this correlation and corrects the gain of the data path until there is zero correlation (or nearly zero correlation) between the observed signal on the main control port and the input data.
Referring to again
As an alternative, according to another embodiment, the residual data signal of the main loop may be directly sensed at the main control port 172 of the VCO 138. However, it should be noted that direct sensing of the main VCO control port could potentially be disruptive if any switch transients occur while tracking the sign of the input data. These transients, which may develop through capacitive coupling or switch charge injection, could be integrated by the loop filter 146 and undesirably affect the performance of the main loop. Therefore, in at least some embodiments, the above-described method in which no direct sensing of the main control port 172 of the VCO 138 is required may be preferable.
As discussed above, another embodiment of the invention may be directed to a method of VCO band selection/calibration that may allow the frequency synthesizer to achieve faster locking times by reducing the time taken to select and appropriate VCO frequency band. In particular, predetermined initial settings may be used to limit the number of frequency ranges over which a search algorithm may be performed to find the desired operating frequency band, as discussed below.
Referring to
According to one embodiment, the inductors L1 and L2 may be implemented as bondwires that may be used to couple various circuit components to a semiconductor substrate. Each bondwire may have associated with it a certain inductance that may be dependent on the length of the bondwire, the cross-sectional area of the bondwire, and the spacing between adjacent bondwires (which affects mutual inductive coupling between the bondwires). At a given operating frequency, the inductance associated with the bondwires may be approximated by a fixed inductance, which is the inductance represented by L1 and L2 in
Referring again to
According to one embodiment, a six-bit switched metal on metal (MOM) capacitor array may be used for band selection. In this example, the capacitor bank 200 may include six pairs of capacitors C01 and C02 to Cn1 and Cn2, where (in this example) n=6. Of course it is to be appreciated that the invention is not limited to a six-bit case, and other values of n may be used, for example, a four-bit or eight-bit design. In addition, each bit need not correspond to a pair of capacitors, but may instead control one or multiple capacitors. A digital control word, referred to herein s the VCO band-select control signal, may be issued (for example, by a microcontroller) to activate switches 202a . . . 202b, and 202c. In one example, this control word may be a binary word that may include a bit to control each of the switches. For example, in the illustrated six-bit case, bit 0 may control switch 202a, bit 5 may control switch 202b and bit 6 may control switch 202c. The other intervening bits may control additional switches not shown in
Once a frequency band has been selected, the desired center frequency Fc may be tuned within this band, for example, by controlling a variable capacitance (e.g., a varactor diode) that also forms part of the capacitive element of the resonating structure. Referring to
One example of the effective relationship between the bands that may be selected by controlling the bank of fixed capacitors, a control voltage that tunes the variable capacitance, and the VCO output frequency is illustrated in
Table 1 below illustrates some examples of frequency band selection for three different VCOs that can be realized with a six bit binary pattern 0-63. It is to be appreciated that the frequency band values given for each VCO are exemplary only and not intended to be limiting. The actual band values for a given implementation may depend on the values of the capacitors 200, the inductance values provided by inductor 198, the reference frequency value (see, for example,
The desired operating center frequency Fc may fall in any one of the operating frequency bands of the VCO 138. In the absence of supply voltage changes, temperature fluctuations, and manufacturing process and parameter variations, one may have a priori knowledge as to which frequency band it would be appropriate to set the VCO to in order to maintain the desired frequency Fc. However, the aforementioned changes in operating conditions may have the undesired effect of shifting the bands to higher or lower frequencies, as illustrated in
As discussed above, there are prior art methods of VCO calibration, such as the race-counter method. However, these methods may suffer the disadvantage that they take too long to settle to a final selection of the appropriate band, particularly if the number of bands starts approaching values of 32 or 64 (as would be the case for 5- or 6-bit VCO band control, which may be common for a multi-band frequency synthesizer). Therefore, according to aspects of the invention, there may be provided a method of VCO band calibration that may vastly reduce the settling time by using predetermined initial settings for which bands should be used for which desired center frequencies.
In some applications it may be highly desirable that the speed at which the VCO frequency band is determined be very fast. This may require very fast synthesizer locking times. An example of such an application is the GSM cellular standard for mobile handsets for which locking times may need to be as fast as 100 μs. Often, it may be very difficult to meet such a fast locking time even without any consideration of VCO band selection. If a VCO band needs to be selected before the routine of acquiring a frequency lock in the phase-locked loop can be begun, it may become even more difficult to obtain a lock quickly enough to comply with standards such as the GSM. Therefore, some embodiments of the invention are directed to a method that may reduce the amount of time needed for VCO band selection, thereby allowing maximum time for the frequency synthesizer to obtain a lock. In particular, methods according to embodiments of the invention may allow minimal overhead time between switching synthesizer frequencies from one desired operating frequency to another.
According to one embodiment of the invention, there may be provided a method for VCO band calibration in which an intelligent initial band selection may be used to set the VCO band very close to the appropriate band of operation. A modified binary search algorithm may then be used to search bands above or below the initial setting in such a manner that only a few iterations of a count and compare cycle may need to be repeated. In at least one embodiment, these methods may reduce the lock time in half compared to the 12.6 μs taken by some prior art designs, as discussed above.
Referring to
As discussed above, in a conventional race-counter design, the comparison of the counters may be repeated for a number of times equivalent to the number of band select bits. The size, M, of the counters may be a function of the accuracy desired for the final band decision and the reference frequency (Fref) selected for the synthesizer. In addition, the desired accuracy may be a function of the amount of overlap between the frequency bands of the VCO. For example, a GSM synthesizer using a reference frequency of 52 MHz and a VCO having 6 bands to select from, an accuracy (Faccuracy) of 500 kHz would be needed. As mentioned above, since, an example value of Fref=50 MHz would require a counter value of 105. Counting 105 cycles of a 50 MHz signal takes about 2.1 μs, and to do this for each bit of a six bit band selection therefore takes 12.16 μs. Generally, the calibration time may then be calculated from the equation:
Tcal=[(1/Faccuracy)+(1/Fref)]*VCO—bands. (2)
where Faccuracy=Fref/(M−1) and M is the size of the counters.
According to one embodiment, a method for VCO band calibration can reduce this calibration time in half by using predetermined initial settings for which bands should be used for which frequencies. An intelligent initial selection setting may set the VCO band initially very close to an appropriate band of operation. Referring again to
Tcal=[(1/Faccuracy)+(1/Fref)]*3 (3)
where 3 is fewer than the number of VCO bands. As can be seen from the above equation, this method may significantly reduce the time taken to locate the appropriate frequency band, thereby allowing the frequency synthesizer to lock to a desired center frequency more quickly.
In a frequency synthesizer designed to accommodate a number of different communication standards across many different frequency bands, the VCO 138 desirably should be capable of producing a large range of output frequencies. Likewise, the fractional-N divider 140 desirably should be capable of a large range of division ratios in order to divide the VCO frequency (Fvco) to match the reference frequency (Fref) for frequency calibration. Also, in some embodiments of a multi-standard system, the VCO 138 may be likely to oscillate at very high frequencies, and the programmable divider 140 may therefore need to interface to the VCO at these very high frequencies.
Some prior art solutions avoid the need to design a divider capable of operating at the same frequency as the VCO by placing a so-called prescaler, having a division value M, in front of the programmable divider to reduce the frequency at which the programmable divider needs to operate. One example of such a design is disclosed in a paper by Ahmed, et al. (“CMOS VCO-prescaler cell-based design for RF PLL frequency synthesizers,” 2000 IEEE Proceedings ISCAS, Geneva, Volume 2, May 2000, pp. 737-740), which is herein incorporated by reference. A drawback of this solution is that quantization noise that may be produced by the sigma-delta modulator in the frequency synthesizer (see
According to some embodiments of the invention, there is provided a programmable divider with a very wide range of programmable division ratios. In addition, the programmable divider may be capable of operating at very high frequencies and at low power by interfacing directly to the VCO. In one embodiment, this may be achieved through the use of an alternative source-coupled logic approach for the design of cascaded divider blocks that allows for the use of a low voltage power supply, for example, by using a reduced number of stacked MOS devices.
Referring to
Referring to
For maximum reconfigurability in light of changes in VCO frequency and reference frequency Fref, a programmable divider 140, implemented, for example, as discussed above, may accommodate a wide range of divide values. For example, for a VCO output of 900 MHz and a reference frequency of 104 MHz, the division value is 8.65. In a fractional-N synthesizer, such a divide ratio has two parts: the integer part 8 and the fractional part 0.65. Since a frequency divider circuit may only be capable of dividing by an integer amounts, an averaging technique may be used to achieve an approximation of the fractional divide ratio over a long term. For example, the frequency divider may divider the signal it receives by an integer value every clock cycle. Considering, for example, 100 clock cycles, then to achieve a long-term approximation of a divide ratio of 8.65, a division by 8 may be performed 35 times (i.e., for 35 clock cycles) and a division by 9 may be performed for 65 clock cycles. This may result in an effective average divide ratio over the 100 clock cycles of 8.65, as shown by the equation:
In a sigma-delta modulated fractional-N synthesizer, such as used in at least some embodiments of the invention, the sigma-delta modulator may control effecting the desired division ratio. For example, the sigma-delta modulator may add a number from the set {−4, −3, −2, −1, 0, 1, 2, 3, 4} to the nominal integer divide ratio on a cycle-to-cycle basis, such that the average effective divide ratio over many clock cycles is approximates a desired fractional divide ratio. As another example, consider a VCO output of 2.5 GHz and a reference frequency of 13 MHz. In this example, the division ratio would be 192.308. Therefore, the nominal integer divide ratio may be 192, and the fractional portion may be approximated by changing increasing or decreasing the integer value 192 by up to plus or minus 4 each clock cycle, such that the long-term average is approximately 192.308. A programmable divider capable of accommodating both of these examples may easily and simply be implemented using the above-described design with an appropriate number of bits n.
One embodiment of a circuit implementation of one of the fractional divider blocks 212 is illustrated in
According to another embodiment, the frequency synthesizer may be configured to accommodate significant changes in bandwidth by including two independent loop filters. As discussed above, if the bandwidth of the data signal to be modulated onto the carrier generated by the frequency synthesizer is larger than the bandwidth of the loop filter, some signal distortion can occur. This can, at least in part, be compensated for by the use of Two-Point Modulation as discussed above. In addition, if two or more loop filters are provided, with a mechanism for switching between them depending on an operating frequency range of the VCO, even wider, non-distorted frequency synthesizer bandwidth may be achieved. Referring to
Referring to
In summary, aspects and embodiments of the invention are directed to a frequency synthesizer, and elements thereof, that may be particularly well-suited to use in a multi-band, multi-standard transmitter or radio transceiver. In particular, the frequency synthesizer may allow wideband operation by accommodating multiple switchable loop filters and a method of fact VCO band calibration to accommodate many different operating frequency bands, and may include a programmable divider designed to allow the use of reduced power supply voltage. In addition, the frequency synthesizer may allow continuous gain compensation, without directly sensing the VCO output and therefore without disrupting VCO operation.
Having thus described several aspects and embodiments of the invention, modifications and/or improvements may be apparent to those skilled in the art and are intended to be part of this disclosure. It is to be appreciated that the invention is not limited to the specific examples described herein and that the principles of the invention may be applied to a wide variety applications. The above description is therefore by way of example only, and includes any modifications and improvements that may be apparent to one of skill in the art. The scope of the invention should be determined from proper construction of the appended claims and their equivalents.
