This application claims priority from Indian patent application No. 2026/Del/2006, filed Sep. 12, 2006, which is incorporated herein by reference.
Embodiments of the present invention relate to common-mode feedback (CMFB) circuits and more specifically to a wide swing, continuous time common-mode feedback (CMFB) circuit providing a good linearity with wide bandwidth and low systematic offsets.
Common-mode feedback circuits stabilize the common mode voltage of differential outputs by adjusting the common mode bias currents. The two differential output voltages are averaged to form a common-mode voltage. The common-mode voltage is compared with a designated reference common-mode voltage. The difference is then amplified and converted into a common-mode output current to adjust the common-mode voltage. Most commonly used common mode feedback circuits fall into the following three categories: (a) Switched Capacitor CMFB, (b) Resistor averaged CMFB, (c) Differential Difference amplifier CMFB.
In another approach an operational amplifier having differential inputs and differential outputs with a predetermined common-mode output voltage independent of common-mode input voltage and an input voltage variation is provided. D.C. common-mode feedback is utilized to provide a differential amplifier having a precise common-mode output voltage, which is similar to the CMFB circuit 300 as illustrated in
Therefore, there is a need for a novel continuous time common-mode feedback (CMFB) module that can provide a wider swing and a good linearity and which provides a wide bandwidth and a low systematic offset.
Embodiments of the present invention provide a common mode feedback module which operates within a wider voltage range of inputs in continuous time and provide a common mode feedback module providing a good linearity and a low input capacitance and high output impedance.
According to one embodiment of the present invention a common mode feedback module includes a common-mode resolver receiving a first input signal and a second input signal for generating a common mode current, and a control voltage generating module operatively coupled to the common mode resolver for generating a common-mode feedback voltage.
Another embodiment of the present invention provides an operational amplifier including one or more stages of differential amplifier for generating differential output voltages, and a common-mode feedback module operatively coupled to the one or more stages of differential amplifier receiving a first input signal and a second input signal for providing a common-mode feedback voltage.
According to another embodiment of the present invention a method for generating a common-mode feedback voltage in a common-mode feedback module with a wide swing and a good linearity includes providing a first input signal and a second input signal, generating a common mode current through a first transistor, a second transistor, a first resistor, and a second resistor, generating a reference current through a fifth transistor and a third resistor, comparing the common mode current and the reference current, and generating a common-mode feedback voltage based on a proportional difference of the common mode current and the reference current.
The aforementioned embodiments and other features of the present invention will be explained in the following description, taken in conjunction with the accompanying drawings, wherein:
The following discussion is presented to enable a person skilled in the art to make and use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
The common mode feedback module 500 includes the common mode resolver 402 and the control voltage generating module 404. The common mode resolver 402 includes multiple transistors such as 502, 504, and 506 and multiple resistors such as R1, R2 coupled to each other to provide a common mode current. The control voltage generating module 404 includes multiple transistors, such as 508, 510, 512, and 514 and a resistor R3 to provide a common mode feedback voltage. A first transistor 502 is connected between a first node N1 and a second node N2 through a first resistor R1 and receives the first input signal INP at a gate terminal. The first resistor R1 is connected between a second supply voltage AGND through the second node N2, and to a source terminal and to a bulk terminal of the first transistor 502. The bulk terminal of the first transistor 502 can alternatively be connected directly to the second supply voltage AGND for compromising a swing. A second transistor 504 is connected between the first node N1 and the second node N2 through a second resistor R2 for receiving the second input signal INM at a gate terminal. The second resistor R2 is connected between the second supply voltage AGND through the second node N2, and to a source terminal and to a bulk terminal of the second transistor 504. The bulk terminal of the second transistor 504 can alternatively be directly connected to the second supply voltage AGND for compromising a swing. A third transistor 506 has a gate terminal and a drain terminal connected to the first node N1, and a source terminal and a bulk terminal connected to a third node N3 for receiving a first supply voltage AVDD.
A fourth transistor 508 has a gate terminal connected to the gate terminal of the third transistor 506, a drain terminal connected to a fourth node N4, and a source terminal and a bulk terminal connected to the third node N3 for receiving the first supply voltage AVDD. A fifth transistor 510 is coupled between the fourth node N4 and the second node N2 through a third resistor R3 and receives a reference common mode voltage VCM at a gate terminal. The third resistor R3 is connected between the second supply voltage AGND through the second node N2, and to a source terminal and a bulk terminal of the fifth transistor 510. The bulk terminal of the fifth transistor 510 can alternatively be directly connected to the second supply voltage AGND for compromising a swing.
A sixth transistor 512 has a gate terminal and a drain terminal connected to the fourth node N4, and a source terminal and a bulk terminal connected to the third node N3 for receiving the first supply voltage AVDD. In an embodiment, the gate terminal and the drain terminal are connected to the fourth node N4 and VCNTRL node respectively but not connected to each other. A seventh transistor 514 having a source and a bulk terminal connected to the second node N2 for receiving the second supply voltage AGND, a gate terminal for receiving a bias current signal IBIAS to the common mode feedback module 500 and a drain terminal connected to the fourth node N4 for generating a common-mode feedback voltage VCNTRL. In an embodiment of the present invention, the first transistor 502, the second transistor 504 and the fifth transistor 510 are n-channel metal oxide semiconductor (MOS) transistors and the third transistor 506, the fourth transistor 508 and the sixth transistor 512 are p-channel metal oxide semiconductor (MOS) transistors.
In an embodiment of the common mode feedback module 500, a first pair of NMOS transistors 502, 504 receives differential output voltages OUTP, OUTM from differential outputs of 500, as described in
A first active element 702 is connected between a first port M1 and a second port M2 and receives a first input signal INP at a gate terminal. A second active element 704 is connected between the second port M2 and a third port M3 and receives a second input signal INM at a gate terminal. A third active element 706 has a drain terminal connected to the third port M3, and a source terminal and a bulk terminal connected to a fourth port M4 and receives a common-mode feedback voltage VCNTRL at a gate terminal through a fifth port M5. A fourth active element 708 has a drain terminal connected to the first port M1, and a source terminal and a bulk terminal connected to the fourth port M4 and receives the common-mode feedback voltage VCNTRL at a gate terminal through the fifth port M5. A fifth active element 710 has a gate terminal connected to the third port M3, a drain terminal connected to a sixth port M6, and a source terminal and a bulk terminal connected to the fourth port M4 for generating the second input signal INM at the sixth port M6. A sixth active element 712 has a gate terminal connected to the first port M1, a drain terminal connected to a seventh port M7, and a source terminal and a bulk terminal connected to the fourth port M4 for generating the first input signal INP at the seventh port M7.
A seventh active element 714 has a drain terminal connected to the second port M2, and a source terminal and a bulk terminal connected to a eighth port M8 and receives a bias current signal IBIAS at a gate terminal. An eighth active element 716 has a drain terminal connected to the sixth port M6, and a source terminal and a bulk terminal connected to the eighth port M8 for receiving the bias current signal IBIAS at a gate terminal. A ninth active element 718 has a drain terminal connected to the seventh port M7, and a source terminal and a bulk terminal connected to the eighth port M8 and receives the bias current signal IBIAS at a gate terminal. The common-mode feedback module 400 is connected between the fifth port M5, the sixth port M6, the seventh port M7 and a reference common-mode voltage (VCM) terminal for providing the common-mode feedback voltage VCNTRL at the fifth port M5. The module 400 is connected between the fourth port M4, the eighth port M8 and a bias (IBIAS) terminal for initializing and then bringing the module 400 into a steady state condition.
An operational amplifier in general contains two or more differential amplifier stages, using conventional symbols. In an embodiment, the amplifier 700 is a two stage fully differential input/output class A output stage operational amplifier. Transistors 702, 704 forms the differential pair input stage. MOSFETs 714, 716, 718 establishes bias currents and MOSFETs 706, 708 provide active load for input stage and transistors 710, 712 provide active load for the outputs. The differential output signals V1+, V1− of differential input stage are the drain terminals of active load of the MOSFETs 706, 708 respectively. The class A output stage comprises active load MOSFETs 710, 712 and current mirrors 716, 718 respectively. As in the first stage of the operational amplifier in which both inputs and outputs are fully differential the common mode feedback module (CMFB) required to set the common mode voltage of the first stage outputs to a particular reference voltage level, when a differential input voltage is applied to the inputs of the first stage.
In an embodiment of the present invention, the operation is described using
Drain current of transistor 502,
IP≈(VINP−VTHN)/R (VTHN is threshold voltage of NMOS)
Drain current of transistor 504,
IN≈(VINM−VTHN)/R
Drain current of transistor 510,
ICM≈(VVCM−VTHN)/R (1)
IP+IN≈(VINP+VINM−2×VTHN)/R (2)
Drain current of transistor 506,
IM3≈IP+IN
Equation (2) states that the IM3 has no sensitivity to differential input voltage hence common mode feedback loop.
Drain current of the transistor 508 is IM3/2 because of their geometric ratio, therefore from (1) and (2) we get
VVCM−VTHN=(VINP+VINM−2×VTHN)/2
VVCM=(VINP+VINM)/2 (3)
The closed loop equation (3) is a steady state condition if a drain current of the transistor 514 is equal to drain current through the transistor 512 and the VCNTRL is such that currents through transistors 512, 510 and 506 are matched according to their geometric ratios.
If common mode voltage of inputs of 500 is different from VCM then IM4 will differ from ICM and extra current will flow through the transistor 512 hence the VCNTRL will change to the correct common mode voltage. If the common mode voltage is greater than the VCM then IM4 will be greater than ICM and current through the transistor 512 will be reduced resulting in increase of the VCNTRL which will tend to reduce the common mode voltage. Similarly, a decrease of the common mode voltage will be restored as equation (2) has no first order dependence on a differential input voltage. There are other possibilities like a gain can be increased by breaking the gate-drain of diode connected the NMOS 512 of the CMFB 500 and if an offset to the reference voltage VCM is affordable then the transistors 512 and 514 can be removed.
Common-mode feedback modules according to the described embodiments have a wider swing of inputs, because bias currents are decided by resistors and a minimum input voltage is decided by VT of NMOS input pairs. Second, the novel modules provide high input impedance and a low input capacitance, so as OPAMP outputs are loaded minimal. Third, the modules provide controlling of linearity by increasing resistance values and aspect ratio of input MOS transistors. Fourth, the modules have no need of compensation network for phase margin of a CMFB loop since it's a low gain stage.
Operational amplifiers including CMFB modules according to embodiments of the present invention may be utilized in a variety of different types of electronic circuits and systems, such as portable devices like cell phones and personal digital assistants (PDAs), as well as in computer systems, communications and control systems, and so on.
From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.
Number | Date | Country | Kind |
---|---|---|---|
2025/DEL/2006 | Sep 2006 | IN | national |
Number | Name | Date | Kind |
---|---|---|---|
4573020 | Whatley | Feb 1986 | A |
5039954 | Bult et al. | Aug 1991 | A |
5748040 | Leung | May 1998 | A |
5764101 | Archer | Jun 1998 | A |
6114907 | Sakurai | Sep 2000 | A |
6177838 | Chiu | Jan 2001 | B1 |
6353361 | Sun | Mar 2002 | B1 |
6362688 | Au | Mar 2002 | B1 |
6411165 | Delano | Jun 2002 | B1 |
6529070 | Nagaraj | Mar 2003 | B1 |
6985038 | Miwa et al. | Jan 2006 | B2 |
Number | Date | Country | |
---|---|---|---|
20080074189 A1 | Mar 2008 | US |