Patent Application
20250192792
This application claims priority under 35 U.S.C. § 119 to Indian patent application Ser. No. 20/234,1083007, filed 6 Dec. 2023, the contents of which are incorporated by reference herein.
The present disclosure relates to continuous-time pipeline ADC. Furthermore, the present disclosure relates to a method of calibrating a digital filter of a continuous-time pipeline ADC.
In a continuous-time pipeline (CTP) ADC, the digital outputs of various stages are combined to give the final ADC output signal. This reconstruction requires estimating digital filters for various stages. This digital reconstruction needs to match a sampled analog system. The digital filter needs to match an analog path, wherein mismatch degrades the overall performance of the CTP ADC.
According to a first aspect, a continuous-time analog-to-digital converter circuit includes:
It is assumed, that a delay of an ADC-DAC path is already tuned/programmed by any other method, wherein the digital filter of the proposed CTP ADC circuit only matches the analog path. This advantageously allows to increase a gain of the analog filter block, resulting in an improved performance of the CTP ADC circuit.
According to a further aspect, a method for calibrating a digital filter of a continuous-time analog-to-digital converter circuit, includes:
In one or more embodiments, filter coefficients of said digital filter are provided by a calibration device.
In one or more embodiments, the CTP ADC circuit further comprises a signal source being configured to feed its signal to the calibration device, wherein the output is applied to the calibration device, wherein the calibration device is configured to update the filter coefficients of the digital filter.
According to one or more embodiments, the signal source is configured to generate one of the following: pseudo random signal, sine wave signal. Advantageously, even more alternative kinds of signal sources are possible to be used.
According to one or more embodiments, the digital filter is one of the following: adaptive IIR-filter, adaptive FIR filter.
According to one or more embodiments, the CTP ADC circuit comprises switches which are configured to set the ATP ADC circuit into a calibration mode and into normal operation mode.
According to one or more embodiments, the CTP ADC circuit further comprises a gain stage between the sub ADC and the digital filter and/or a gain stage between the first summation node and the continuous-time filter, wherein at least one of said gain stages is bypassed in the calibration mode.
According to one or more embodiments, a calibration algorithm running on the calibration device is a normalized LMS algorithm. The normalized LMS provides a fast way of implementing the calibration procedure of the digital filter.
According to one or more embodiments, a number of calibration cycles of the calibration algorithm is known in advance, wherein after having performed the calibration the filter coefficients have converged within a specified tolerance. The number of cycles can be determined in advance, e.g. by means of a simulation process (e.g. MATLAB).
According to one or more embodiments, the signal source and the calibration device are on-chip or off-chip. An on-chip signal source is easy to implement. Furthermore, also the calibration device is preferably implemented on-chip in order to perform calibration when temperature varies.
According to one or more embodiments, the CTP ADC circuit further comprises a DC blocker functionally coupled between an output of the second summation node and the calibration device. In this way, DC components can be filtered from digital error data, i.e. an offset may be removed or at least reduced.
According to one or more embodiments, the CTP ADC circuit is one of the following: IIR-filter, CIC-filter, FIR-filter.
According to one or more embodiments, a value of the sampling rate of the output of the continuous-time filter is equal or smaller than a value of the sampling rate of the sub DACs.
The above discussion/summary is not intended to describe each embodiment or every implementation of the present disclosure. The drawings and detailed description that follow also exemplify various embodiments. The aspects defined above and further aspects of the present disclosure are apparent from the examples of embodiment to be described hereinafter with reference to the appended drawings, which are explained with reference to the examples of embodiment. However, needless to say, that the disclosure is not limited to the examples of embodiments.
All illustrations in the drawings are schematical. It is noted that in different figures, similar or identical elements or features are provided with the same reference signs or with reference signs that are different from the corresponding reference signs only within the first digit. In order to avoid unnecessary repetitions, elements or features which have already been elucidated with respect to a previously described embodiment are not elucidated again at a later position of the description.
Various example embodiments may be more completely understood in consideration of the following detailed description in connection with the accompanying drawings, in which:
While various embodiments discussed herein are amenable to modifications and alternative forms, aspects thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure including aspects defined in the claims. In addition, the term “example” as used throughout this application is only by way of illustration, and not limitation.
It is proposed to note that the two sub-paths are inherently subtracted at the output signal v. If a signal is injected at the input of the sub DAC 12 (with vin=0), then the output signal v=0 (ignoring quantization noise of the back-end ADC 41), if the two paths match. This observation is used to apply Least Mean Square (LMS) to the “error” v and adaptively update the digital filter 40 to match the desired response.
A principal working mechanism is shown in
Initial value of the digital filter 40 (e.g. implemented aa an adaptive FIR filter) are all set to zero (can be set to nominal value also). The input 1 is disconnected and analog-delay path is connected to common-mode or zero. Gain stages 43, 44 can be implemented as a multiplier and are also bypassed in the calibration mode.
In the calibration mode the following steps are done:
The gain of the ADC1-DAC1 path is reduced to not saturate the continuous-time loop filter 30. This is done by either setting the “Gain” of analog-filter & digital-filter path to 1 or some low value.
Changes in this DC-gain can be avoided by having DAC with bit large number of levels (with reduced step-size) than ADC and extra levels are used only during calibration mode. In this case amplitude of test-signal is reduced to ensure backend ADC doesn't saturate.
A signal (e.g. pseudo random source signal, even sine or another signal) of a signal source 60 is applied as an input of the sub DAC 12. There is no strict requirements as regards the type of the signal source 60. A calibration device 50 (e.g. running an LMS algorithm) updates the filter weights FW based on the “error” of the output signal v. After the convergence of the filter weights FW, calibration can be stopped, and normal ADC conversion start (calib=0). The calibration device 50 tries to minimize the error signal err, which corresponds to the output signal v of the second summation node 42. Once the error is zero, it is known that this is the condition that the digital filter 40 is matched to the continuous-time analog filter 30. It is known in advance after how many cycles the filter coefficients have converged.
The signal delay td of the delay element 10 should be matched to the ADC-DAC path delay to minimize the residue r(t). The better the delay matching, the smaller the residue r(t), which allows to keep larger gain in the continuous-time filter 30, which relaxes the back-end ADC requirement.
w1 . . . filter parameter.
Based on the analog continuous-time filter 30, whose transfer function is given in the denominator of the above formula, we achieve certain FIR filter coefficients as shown in the second part of the formula.
The digital filter 40 may be an infinite impulse response filter (IIR filter), however, its impulse response dies down after few samples. For ease of implementation, the digital filter 40 can be approximated by an FIR-filter (finite impulse response filter). It is intended to implement a digital filter 40, whose response matches with the response of the continuous-time analog filter 30.
The following table shows a comparison of exemplary ideal filter weights FW vs. obtained filter weights FW after LMS-convergence:
The second columns shows the expected values of the filter coefficients and the third columns shows that values are close to the expected values in the second column and have been obtained after convergence.
A value of the sampling rate fs of the output of the continuous-time filter 30 is equal to a value of the sampling rate fs of the sub DACs 11, 12. In an alternative, the value of the sampling rate fs of the output of the continuous-time filter 30 can also be smaller than a value of the sampling rate of the sub DACs 11, 12. As a result, this means that a value of the sampling rate fs of the backend ADC 41 can be same or smaller than the sampling rate of the sub DACs 11, 12.
The diagram of
If the calibration is enabled, the filter weights are updated after LMS convergence, the ADC performance is restored.
A sequential method is described in the following. The second stage is calibrated by making the signal calib2=1. Once the filter coefficients of the second digital filter 40b converge, calibration is stopped. Gain of the second stage is by-passed to prevent loop saturation.
Afterwards, the first stage is calibrated by making the signals calib1=1 and calib2=0. As before, gain stage is by-passed. Once the filter coefficients of the first digital filter 40a converge, calibration is stopped, and normal ADC conversion of the CTP ADC circuit 100 can start.
Referring to
variant of the parallel configuration is performed. One recognizes, that in this case some switches of the second stage are not required, because they are always on or always off:
Of course, also filter coefficients of digital filters of CTP ADC circuits 100 with more than two stages (not shown) can be calibrated in the above described manner.
In further alternative embodiments of the proposed CTP ADC circuit 100 a “DC-blocker” (not shown) may be added in a so called “error-path” functionally coupled between the second summation node 42 and the calibration device 50 to the LMS loop which may block DC (hence remove offset) from digital error data. The DC-blocker can be implemented by minimum possible stages of IIR-, CIC-, or FIR-filter. Any other possible structures can be used to filter out DC component from the digital error data.
Possible sources or offsets are e.g. the first summation nodes 20a, 20b. Any gain-mismatch after the first stage is naturally taken care as loop which will tried to be corrected as well.
To include a gain-mismatch error of the first stage, gain-bypass can be removed (calib1=0) and multi-level sub-DAC can be used with reduced amplitude of a test signal (ideally “Full-scale/Gain”). More number of sub DAC levels supports that a small test signal is still bit larger than a step-size of the sub DAC.
In a step 200 the continuous-time analog-to-digital converter circuit (100) is set into a calibration mode.
In a step 210 a calibration input signal is applied to an input 1.
In a step 220 the calibration input signal is delayed by means of a delay element 10 with a specified time delay td, the delay element 10 functionally connected between the input 1 and a first summation node 20.
In a step 230 the calibration input signal is digitized and the digitized signal is reconverted to analog domain and to subtract it at the first summation node 20.
In a step 240 an output of the first summation node 20 is filtered by means of a continuous-time filter 30 and clocking the output of the continuous-time filter 30 with a specified sampling rate fs.
In a step 250 the clocked output of the continuous-time filter 30 is digitized by means of a backend ADC 41 and applied to a second summation node 42.
In a step 260 an output signal v of the continuous-time analog-to-digital converter circuit 100 is provided by summing up the output of the backend ADC 41 with an output of a digital filter 40 being connected to a sub ADC being connected to the input 1.
In a step 270 a replica of a transfer function of the sampled output of the continuous-time filter 30 is provided in the digital domain by means of the digital filter 40.
The proposed CTP ADC circuit can be used for applications requiring high speed ADC. The proposed architecture also has anti-aliasing properties, which can help remove anti-aliasing filter or greatly relax its design. The proposed scheme can be implemented on-chip for foreground calibration. Signal required to feed input for DNCF estimation can be easily implemented as “digital waveform generator”.
The proposed method implements a so called “foreground calibration” only which doesn't need very specific type of test-signal of the signal source 60. It can be multi-tone sine-wave, ramp-wave, chirp or even random input. As per our calibration, it's not necessary to feed digital test signal, even analog signal at the ADC input can be fed during calibration.
The proposed method is to find the DNCF in a adaptive filter manner which starts from the most inner-loop (last stage) and sequentially finding all stage filters. All the stage filters can also be tuned simultaneously using LMS/NLMS but it seem to take bit longer time than sequential estimation. Our proposal also requires bit of change in the filter-dc-gain (set to 1) during calibration.
In the foregoing description various specific details have been set forth to describe specific examples presented herein. It should be apparent to one skilled in the art, however, that one or more other examples and/or variations of these examples may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same reference signs may be used in different diagrams to refer to the same elements or additional instances of the same element. Also, although aspects and features may in some cases be described in individual figures, it will be appreciated that features from one figure or embodiment can be combined with features of another figure or embodiment even though the combination is not explicitly shown or explicitly described as a combination.
As examples, the specification describes and/or illustrates aspects useful for implementing the claimed disclosure by way of various circuits or circuitry which may be illustrated as or using terms such as blocks, modules, device, system, unit, controller, etc. and/or other circuit-type depictions. Such circuits or circuitry are used together with other elements to exemplify how certain embodiments may be carried out in the form or structures, steps, functions, operations, activities, etc. As examples, wherein such circuits or circuitry may correspond to logic circuitry (which may refer to or include a code-programmed/configured CPU, in one example the logic circuitry may carry out a process or method (sometimes “algorithm”) by performing such activities and/or steps associated with the above-discussed functionalities. In other examples, the logic circuitry may carry out a process or method by performing these same activities/operations.
For example, in certain of the above-discussed embodiments, one or more modules are discrete logic circuits or programmable logic circuits configured and arranged for implementing these operations/activities. In certain embodiments, such a programmable circuit is one or more computer circuits, including memory circuitry for storing and accessing a program to be executed as a set (or sets) of instructions (and/or to be used as configuration data to define how the programmable circuit is to perform), and an algorithm or process as described above is used by the programmable circuit to perform the related steps, functions, operations, activities, etc. Depending on the application, the instructions (and/or configuration data) can be configured for implementation in logic circuitry, with the instructions (whether characterized in the form of object code, firmware or software) stored in and accessible from a memory (circuit). As another example, where the specification may make reference to a “first” type of structure, a “second” type of structure, where the adjectives “first” and “second” are not used to connote any description of the structure or to provide any substantive meaning; rather, such adjectives are merely used for English-language antecedence to differentiate one such similarly-named structure from another similarly-named structure.
Based upon the above discussion and illustrations, those skilled in the art will readily recognize, that various modifications and changes may be made to the various embodiments without strictly following the exemplary embodiments and applications illustrated and described herein. For example, methods as exemplified in the Figures may involve steps carried out in various orders, with one or more aspects of the embodiments herein retained, or may involve fewer or more steps.
It should be noted that the term “comprising” does not exclude other elements or steps and “a” or “an” does not exclude a plurality. Also elements described in association with different embodiments may be combined. It should also be noted, that reference signs in the claims should not be construed as limiting the scope of the claims.
The discloses devices, apparatuses, units, elements, systems and methods described herein may at least partially be embodied by a computer program or a plurality of computer programs, which may exist in a variety of forms both active and inactive in a single computer system or across multiple computer systems. For example, they may exist as software program(s) comprised of program instructions in source code, object code, executable code or other formats for performing some of the steps. Any of the above may be embodied on a computer readable medium, which may include storage devices and signals, in compressed or uncompressed form.
It is noted that the embodiments above have been described with reference to different subject-matters. In particular, some embodiments may have been described with reference to method-type claims whereas other embodiments may have been described with reference to apparatus-type claims.
However, a person skilled in the art will gather from the above that, unless otherwise indicated, in addition to any combination of features belonging to one type of subject-matter also any combination of features relating to different subject-matters, in particular a combination of features of the method-type claims and features of the apparatus-type claims, is considered to be disclosed with this document.
It has to be noted that embodiments have been described with reference to different subject matters. In particular, some embodiments have been described with reference to method type claims whereas other embodiments have been described with reference to apparatus type claims.
However, a person skilled in the art will gather from the above and the following description that, unless other notified, in addition to any combination of features belonging to one type of subject matter also any combination between features relating to different subject matters, in particular between features of the method type claims and features of the apparatus type claims is considered as to be disclosed with this application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202341083007 | Dec 2023 | IN | national |
