This invention relates to a control and safety circuit for gas delivery valves, in particular for boilers for domestic use, according to claim no. 1. Through this invention the risk of delivering undesired gas is minimised, while at the same time the relative cost of the circuit is kept low.
According to current regulations the safety measures to which gas delivery valve control boards, and more particularly the electrical control circuits which energise/de-energise valves through which combustible gas is delivered, are subjected are particularly stringent regulations. Among others these regulations apply to the boilers present for example in domestic heating systems.
In particular many “redundant” systems and devices to prevent the undesired delivery of gas if any component in the valve control circuit should fail or no longer function correctly must be provided within such circuits in order to comply with the reference regulations.
In general, in existing control circuits a microcontroller capable of controlling an actuator, for example a relay, to open/close a combustible gas delivery valve is often present. Because faults are also possible in the microcontroller itself, another control circuit must preferably “replace” the circuit included in the microcontroller if the latter should fail. In a possible embodiment this second control circuit may also include a supervisory element, such as a microcontroller, to control opening and closing of the valve through a separate signal delivered to the actuator (or to a separate actuator) so that the valve can open and deliver gas only in the situation where both the signals reach the actuator, which is then controlled in such a way as to permit the delivery of gas. If one of the two microcontrollers should fail, and if both should fail simultaneously, the valve will remain closed.
One of then disadvantages of this technical solution lies in the fact that because it is necessary to make these control circuits relatively economical so that they can be competitive in the market in question the presence of two microcontrollers results in an excessive increase in the final cost of the board controlling the valve.
British patent application GB 2229841 describes a fuel-heated device, for example a water heater, which has at least one fail-safe device which blocks delivery of fuel to the equipment's burner in the event of a fault, which is fed with electrical current and can only be deliberately unlocked through a control. In order to be able to maintain and use the fault information in this fail-safe device if there should be a power cut, the electronic fail-safe device is connected to a device which records the length of a power cut and which according to a preferred embodiment of the equipment comprises a non-volatile read-only semiconductor memory (EEPROM) which can be cancelled electrically.
The object of this invention is therefore that of providing a control and safety circuit for gas delivery valves in which opening of the valve depends on—at least—the delivery of two signals which are substantially independent of each other to control an actuator in order to control the delivery of gas in a manner which is quite safe.
The object of this invention is to provide such a circuit having a simplified structure, high safety and low cost, which at the same time is able to overcome the limitations mentioned with reference to the cited known art.
This and other objects which will be more apparent below are achieved by the invention through a control and safety circuit constructed according to the following claims.
Further features and advantages of the invention will be more apparent from the following detailed description of a preferred embodiment illustrated by way of indication and without limitation with reference to the appended drawings in which:
Initially with reference to
The valve (also not shown, in
Control circuit 1 can control actuator control 50 and as a consequence control opening/closing of the valve.
In greater detail, actuator 50 (which in a different preferred embodiment may also be more than one in number) can be energised, that is receive an electrical current, through switching on at least two switches, referred to respectively as first and second switches 2, 3, for example a first and a second transistor. When one of the two switches is off (and obviously also when both the switches are off) the actuator is not energised and the valve to which it is connected is closed. The switches may be two or more in number, and also other types of static switches, not only transistors, may be used. Furthermore, according to the invention it is possible for only the second switch to be present, the first being present for further safety.
The two switches 2, 3 are connected together in such a way that both must be switched on by two separate signals, referred to below as “on-signals” in order to energise relay 50. In the configuration in
Control circuit 1 comprises a control unit 100, for example a microcontroller, connected to a first switch 2 and capable of generating a first voltage signal V1 from its outlet 100V1 which is sent as an input to the base of first switch 2. Signal V1 is a static signal of the on/off type, that is a step signal which is alternately equal to zero when no signal is present or a voltage signal which is substantially constant over time. Delivery of such signal V1 therefore sets first switch 2 to on, that is first signal V1 is a signal to “switch on” switch 2, which in the absence of such signal remains off.
Control unit 100 is also capable of generating a second voltage signal V2 from an output 100V2, for example a square wave, and a clock signal CK, from an outlet 100CK, which is also a square wave, which together switch on second switch 3 in a manner described below. Signals CK and V2 are dynamic signals, for example they are signals having a frequency of 30 and 5 KHz respectively and a maximum amplitude of 5 V and 0 V respectively.
Between control unit 100 and second switch 3 there is a memory 5, which includes an input 51, an output 5U separate from input 5I, and a further input 5CK for the clock signal. Memory 5 is connected to control unit 100 in such a way that signal V2 is delivered to input 5U and the clock signal CK is sent to input CK of memory 5. Clock signal CK and voltage signal V2 can reach the memory unchanged (that is as emitted by control unit 100), or may be processed, filtered, etc.
Memory 5 is able to emit an on-signal V3, the second signal switching on circuit 1 through output 5U, signal V3 which is a function of input signal V2, and the clock signal CK. On-signal V3 is then sent as an input to switch 3 to switch it on.
If the valve has to remain closed, signal V2 sent by control unit 100 may for example be of the type “0 0 0 0 0 0 0 0 0” (that is no voltage signal is emitted from the output of the microprocessor), or alternatively, in the case where the valve has to be opened by energising relay 50 on-signal V2 may be of the type “1 0 1 0 1 0 1 0” (square wave).
In reality signal V2 does not directly switch on switch 5, that is its presence is not sufficient to switch on switch 3, because it does not directly generate on-signal V3 whose generation requires the further presence of the clock signal CK as detailed below, the actual on-signal is signal V3. This signal is preferably substantially similar to input signal V2 which comes from control unit 100, more preferably it is identical to the signal from the microprocessor. Signal V2 and clock signal CK are two independent signals generated independently of each other by the microprocessor.
Preferably, memory 5 comprises a register 7, more preferably an internal sliding register, in which data from the communication line between microprocessor 100 and memory 5 come together, that is signal V2 reaches register 7. Each bit of signal V2 replaces one bit present in register 7 and at the same time on the other side of the register a corresponding bit is emitted as an output signal V3 of memory 5.
Input clock signal CK therefore has a safety function, while signal V3 (a signal which as described in this preferred example is identical to V2 “shifted” along the length of register 7, although signal V2 may be processed in other ways by memory 5, and furthermore signal V3 may also be different from signal V2) reaches second switch 3 and switches it on only if clock signal CK is present, and more particularly only if the correct combination between clock signal CK and input signal V2 reaches memory 5 as an input. For each clock pulse the devices unit 100 and memory 5 which are in communication emit a bit from their internal register replacing it by another bit, in the case of memory 5 a bit of register 7 is replaced by a bit of the V2 signal originating from microprocessor 100. In the case therefore where a clock signal is not emitted and/or this does not reach the memory, this replacement of the bit in register 7 does not take place and on-signal V3 is not emitted correctly, thus preventing switch 3 from being switched on, for example it will be not switched on if a signal of the 0 0 0 0 0 type is emitted.
Control unit 100 is therefore only able to switch on the gas delivery valve under particular conditions, that is when both on-signals V2 and CK are sent to memory 5, and more preferably for greater safety when V1 and V3 are sent to the two switches 2 and 3 at the same time. If only one of these signals V2 and CK is absent, switch 3 will not switch on and therefore relay 50 cannot be energised, while for further safety, preferably if only one of these signals V3 and V1 is missing, one of the two switches 2, 3 will not switch on and relay 50 will also not be capable of being energised in this situation.
Memory 5 is preferably a slave SPI; that is communication between control unit 100 and memory 5 is provided according to the SPI communication standard in which unit 100 is the master and memory 5 is the slave. Thus the clock signal sent by unit 100 to memory 5 is the serial clock signal providing the timing for the emission and reading of bits on data lines. The data line, that is the line on which the data reach memory 5, is the connection between the microprocessor and the memory along which signal V2 is transmitted.
Memory 5 may for example be an EEPROM memory.
According to a variant of the invention signal V3 does not reach the base of transistor 3 directly, but through a module 8 in which it is transformed into a static signal V3′, similar to signal V1. Module 8 includes for example a plurality of condensers.
Sliding register 7 is responsible for output signal V3 from the memory: substantially input signal V2 is re-emitted signal V3 from memory 5 after a certain number of clock cycles if a clock signal is correctly emitted at the right frequency.
Memory 5 is connected to second switch 3, that is in particular to the base of transistor 3, so when signal V3 reaches the base of transistor 3, in the case where transistor 2 is also on (i.e. signal V1 reaches its base), then current can flow from the first transistor to earth and therefore relay 50 is energised and the gas delivery valve consequently opens.
If there is any fault, for example if signal V1 is not emitted or is not correctly emitted the relay is not energised because both switches 2 and 3 must be on so that current can pass.
In addition to this, according to a preferred example, control circuit 1 also comprises a further switch, transistor 4, again controlled by control unit 100, as a result of which a further signal V4 has to be emitted (also for example a static step signal similar to V1) so that the relay can only be energised if switch 4 is also on through a properly-emitted voltage signal V4. Thus if several faults occur, or in the case in which V1 is emitted correctly in error, there is the further safety of the need for V4 to also be present.
Similarly it is not sufficient for an erroneous V2 signal to be sent to memory 5, and it is not sufficient for an on-signal to be sent to the memory instead of an off-signal provided that the correct clock signal should be sent at the same time, or the proper combination between clock signal and V2 must be emitted from microprocessor 100 for the memory to emit output on-signal V3 and therefore switch on second transistor 3.
Number | Date | Country | Kind |
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PD2011A000090 | Mar 2011 | IT | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/EP2012/054333 | 3/13/2012 | WO | 00 | 9/23/2013 |