Patent Application
20130088903
The present invention is related to active rectifiers, and in particular to control architectures for active rectifiers.
In contrast with passive rectifiers that rely on diodes to rectify an alternating current (AC) input to a direct current (DC) output, active rectifiers employ solid-state switching devices that are selectively turned On and Off to convert an AC input to a DC output. Operation of the active rectifier is controlled by a controller that generates control signals provided to each of the plurality of solid-state switching devices within the active rectifier. Benefits of the active rectifier include the ability to regulate the output voltage of the active rectifier, reduce current harmonics and provide improved power factor correction.
The performance of the active rectifier relies, in part, on the ability of the controller to accurately determine the phase and frequency of the AC input voltage. For example, power factor correction relies on shaping the AC input current drawn by the active rectifier to be in-phase with the AC input voltage. It is therefore important to be able to accurately measure the phase (i.e., position) of the AC input voltage.
The present invention is a control architecture for a three-level active rectifier. The control architecture monitors the AC input voltage provided to the active rectifier at a sampling rate grater than the frequency of the AC input voltage and calculates, in response, a phase estimate associated with the monitored AC input voltage that is updated with each new sample of the AC input voltage. Based on the phase and frequency estimates, along with monitoring of the AC input current and DC output voltage, the control architecture calculates voltage commands that are used to generate the pulse-width modulation (PWM) controls signals for provision to solid-state switching devices in the active rectifier.
The control architecture of the present invention controls the operation of a multi-level rectifier by sampling the AC input at a sampling frequency significantly higher than the frequency of the AC input voltage. This higher sampling rate minimizes the error in the calculated phase and frequency. Calculation of pulse width modulation (PWM) control signals generated by the control architecture can be synchronized with calculated phase information such that each calculation of PWM control signals is based on a most recent update of calculated phase information. With improved phase information, the control architecture is able to reduce harmonics, which provide improved power factor correction that in turn improves power quality and reduces the electromagnetic interference (EMI) associated with the active rectifier.
In the embodiment shown in
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Current regulator 22 monitors the AC currents ia, ib, ic provided to active rectifier 12, and receives phase information θ and frequency information w provided by phase/frequency detector 18. Current regulator 22 provides power factor correction by monitoring current ia, ib, ic supplied to active rectifier 12, and generating control signals provided to PWM 20 to control the DC output voltage (based on the input provided by voltage regulator 24) and to ensure that the monitored currents ia, ib, ic are in-phase with the monitored voltage as indicated by the phase and frequency information provided by phase/frequency detector 18. In particular, phase information θ is employed by current regulator 22 to transform the monitored currents from the three-phase abc reference frame to a two-phase dq reference frame. Frequency information w is employed by current regulator 22 to decouple the dq phase currents as part of the dq proportional-integral (P-I) control loops provided within current regulator 22. In response to these inputs, current regulator 22 calculates duty cycle voltage commands (provided with respect to the two-phase dq reference frame, Vq, Vd) for provision to PWM 20. Improved accuracy of phase information θ provided by phase/frequency detector 18 improves the power factor correction provided by current regulator 22, thereby reducing the EMI associated with active rectifier 12.
As discussed above, pulse width modulator (PWM) 20 receives duty cycle command instructions (Vq, Vd) from current regulator 22, and in response generates PWM signals that are supplied to each of the plurality of solid-state switching devices S1, S2, S3 included within active rectifier 12. The conversion of duty cycle command instructions Vq, Vd from the two-phase dq reference frame to the three-phase abc reference frame Vs1, Vs2, Vs3 is based, in part, on the accuracy of the phase information θ provided by phase/frequency detector 18. By improving the accuracy of phase information θ, the magnitude of current harmonics (e.g., 2nd, 3rd, 4th, etc.) is reduced. Minimizing the current harmonics results in improved power quality, which in turn, improves EMI performance of active rectifier 12.
As discussed above, the update rate or frequency of PWM 20 does not need to be the same as the update rate or frequency of phase/frequency detector 18. However, PWM 20 may be synchronized with phase/frequency detector 18 to ensure that each duty cycle command instruction calculated by PWM 20 is based on a most recent estimate of position. For example, the sample rate or update rate of phase/frequency detector may be some multiple of the update rate of PWM 20, such that phase/frequency detector 18 is synchronized with PWM 20, yet the update or sample rate of each may be selected independent of one another. In this way, the sampling frequency employed by phase/frequency detector 18 and the PWM frequency employed by PWM 20 can be selected independent of one another to meet the desired EMI and power quality requirements of a particular application.
In the embodiment shown in
sin(x−y)=sin(x)*cos(y)−cos(x)*sin(y) Equation 1
As discussed above, the phase of the monitored AC input voltage when converted from the abc reference frame to the αβ reference frame is related to the phase of the AC input voltage (e.g., α=Va, β=0.57735*(Vb−Vc)). Equation 1 is based on the assumption that the sampling rate is great enough that phase advancement between the current phase estimate and the phase of the monitored AC input voltage is relatively small (i.e., x≈y).
The calculated error between the monitored AC input and the current phase estimate is provided to proportional-integral (PI) controller 38 to generate an output that acts to drive the difference between the monitored error to zero. The output of PI controller 36 is combined with the current position estimate θ at summer block 40 to generate a new position estimate θ. Wrapping block 42 provides wrapping (if necessary) of the new position estimate if it extends beyond a desired range (i.e., wraps the estimate back around within a desired range, e.g., 0-360 degrees), and provides the new position estimate θ to control processor 14.
The new position estimate θ is also provided in feedback to correct subsequent estimates of the monitored position. The position estimate θ is held in memory by block 44 so that this value may be used in the next software cycle by summer block 40. In addition, summer block 46 adds an offset 48 of −90 degrees to align the phase of the software algorithm with the hardware sensors. The resultant phase-lock loop signal (PLL_angle) is provided to sine function 50 and cosine function 52 to generate sine and cosine wave functions based on the new position estimate. The embodiment shown in
In one embodiment, the sample rate (i.e., the rate at which AC voltages are sampled) is much greater than the frequency of the AC input voltage (e.g., 100 times greater than the AC input frequency). In this way, the phase estimate θ provided to control processor 14 is continuously updated. This is in contrast with typical zero cross systems in which the phase is updated only at zero cross of the monitored AC input. For example, if the AC input voltage is provided at 800 Hz, the position estimate θ is updated at a frequency of 1600 Hz (representing two zero-cross events during each cycle). In the present invention, the phase estimate θ may be updated at a sampling rate much greater than that of the AC input voltage (e.g., 100 KHz). The higher sampling rate decreases the error in the position estimate and thereby reduces harmonics in the active rectifier, thereby reducing EMI. In addition, the sampling rate of the present invention may be selected based on the particular harmonics to be reduced. Therefore, the sampling rate may change based on the frequency of the AC input voltage or the particular harmonics to be minimized.
While the invention has been described with reference to an exemplary embodiment(s), it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment(s) disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
