Patent Application
20110317323
1. Technical Field
The present disclosure relates to a control circuit and particular to an electronic device using a control circuit.
2. Description of Related Art
When voltage supplied to a SDRAM (synchronous dynamic random access memory) module is less than 2.0V, data stored in the SDRAM may change. Therefore, when the electronic device decodes the changed data information in the SDRAM, erroneous information is provided thereto.
Therefore, there is room for improvement in the art.
Many aspects of the embodiments can be better understood with references to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout two views.
The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.
Referring to
The electronic device 100 includes a power supply 10, a control circuit 20 and storage unit 30. The power supply 10 provides a voltage to the storage unit 30 via the control circuit 20. The storage unit 30 is a SDRAM. The storage unit 30 defines a working voltage such as 2.0V.
The control circuit 20 includes a filter unit 201 and a protection unit 203. The filter unit 201 filters noise from the power supply 10, and provides the filtered voltage to the protection unit 203.
The protection unit 203 generates a control signal to the storage unit 30 to protect the storage unit 30. The protection unit 203 also provides an output voltage to the storage unit 30. If the output voltage of the protection 203 is less than the working voltage, the protection unit 203 generates a first control signal. If the output voltage of the protection 203 is at least the working voltage, the protection unit 203 generates a second control signal. In the embodiment, the first control signal is a low level signal and the second control signal is a high level signal.
The storage unit 30 is disabled in response to the first control signal, and enabled in response to the second control signal.
Referring to
The protection unit 203 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first node A1, a second node A2, a third node A3, a first transistor Q1 and a second transistor Q2. The first resistor R1 is connected between the power supply 10 and the first node A1 and the second resistor R2 is connected between the first node A1 and ground. The third resistor R3 is connected between the power supply 10 and the second node A2. The fourth resistor R4 is connected between the power supply 10 and the third node A3. A base of the transistor Q1 is connected to the first node A1. A collector of the first transistor Q1 is connected to the second node A2. An emitter of the first transistor Q1 is grounded. The first transistor Q1 is a npn type bipolar junction transistor. A gate of the second transistor Q2 is connected to the second node A2. A drain of the second transistor Q2 is connected to the third node A3. A source of the second transistor Q2 is grounded. The second transistor Q2 is an n-channel enhancement type metal oxide semiconductor field effect transistor.
The storage unit 30 includes a port P1 to receive the control signal of the protection unit 203. The port P1 is electrically connected to the third node A3. When the port P1 receives the first control signal, the storage unit 30 is disabled, when the port P1 receives the second control signal, the storage unit 30 is enabled.
Resistors R1 and R2 forms a voltage divider circuit and when the voltage of the power supply 10 is less than 2.0V, the difference in voltage between the first node A1 and the emitter of the second transistor Q1 is less than 0.7V. The transistor Q1 is turned off. The voltage at A2 will be at the same voltage as the power supply 10 voltage. The difference in voltage between the second node A2 and the source of the second transistor Q2 exceeds 0.7V. The second transistor Q2 is turned on. The voltage of the third node A3 is pulled to ground. The protection unit 203 generates the first control signal. The storage unit 30 is disabled according to the first control signal.
When the voltage of the power supply 10 is at least 2.0V, the difference in voltage between the first node A1 and the emitter of the second transistor Q1 exceeds 0.7V. The transistor Q1 is turned on. The voltage of the second node A2 is pulled to ground. The second transistor Q2 is turned off. The voltage of the third node A3 will be at the same voltage as the power supply 10 voltage. The protection unit 203 generates the second control signal. The storage unit 30 is enabled according to the second control signal.
As described, when the output voltage of the protection unit 203 is less than the working voltage, the storage unit 30 is disabled; and when the output voltage of the protection unit 203 is at least the working voltage, the storage unit 30 is enabled. Therefore, data information is stored in the storage unit 30 only when the output voltage of the protection unit 203 is at least the working voltage, and thus remains intact.
It is to be understood, even though information and advantages of the present embodiments have been set fourth in the foregoing description, together with details of the structures and functions of the present embodiments, the disclosure is illustrative only; and that changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the present embodiments to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201010209758.8 | Jun 2010 | CN | national |
