Control circuit and method for maintaining high efficiency over broad current ranges in a switching regulator circuit

Abstract

A circuit and method for controlling a switching voltage regulator having (1) a switch including one or more switching transistors and (2) an output adapted to supply current at a regulated voltage to a load including an output capacitor. The circuit and method generates a control signal to turn said one or more switching transistors OFF under operating conditions when the voltage at the output is capable of being maintained substantially at the regulated voltage by the charge on the output capacitor. Such a circuit and method increases the efficiency of the regulator circuit particularly at low average current levels.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a switching regulator circuit. More particularly, the present invention relates to a control circuit and method for maintaining high efficiency over broad current ranges in a switching regulator circuit.

The purpose of a voltage regulator is to provide a predetermined and constant output voltage to a load from a poorly-specified and fluctuating input voltage source. Generally, there are two different types of regulators: series regulators and switching regulators.

The series regulator employs a pass element (e.g., a power transistor) coupled in series with a load and controls the voltage drop across the pass element in order to regulate the voltage which appears at the load. In contrast, the switching regulator employs a switch (e.g., a power transistor) coupled either in series or parallel with the load. The regulator controls the turning ON and turning OFF of the switch in order to regulate the flow of power to the load. The switching regulator employs inductive energy storage elements to convert the switched current pulses into a steady load current. Thus, power in a switching regulator is transmitted across the switch in discrete current pulses, whereas in a series regulator, power is transmitted across the pass element as a steady current flow.

In order to generate a stream of current pulses, switching regulators typically include control circuitry to turn the switch on and off. The switch duty cycle, which controls the flow of power to the load, can be varied by a variety of methods. For example, the duty cycle can be varied by either (1) fixing the pulse stream frequency and varying the ON or OFF time of each pulse, or (2) fixing the ON or OFF time of each pulse and varying the pulse stream frequency.

Which ever method is used to control the duty cycle, switching regulators are generally more efficient than series regulators. In series regulators, the pass element is generally operated in its linear region where the pass element conducts current continuously. This results in the continuous dissipation of power in the pass transistor. In contrast, in switching regulators, the switch is either OFF, where no power is dissipated by the switch, or ON in a low impedance state, where a small amount of power is dissipated by the switch. This difference in operation generally results in reduced amounts of average power dissipation in switching regulators.

The above difference in efficiency can be more apparent when there is a high input-output voltage difference across the regulator. For example, it would not be unusual for a series regulator to have an efficiency of less than 25 percent when a switching regulator could perform an equivalent function with an efficiency of greater than 75 percent.

Because of their improved efficiency over series regulators, switching regulators are typically employed in battery-operated systems such as portable and laptop computers and hand-held instruments. In such systems, when the switching regulator is supplying close to the rated output current (e.g., when a disk or hard drive is ON in a portable or laptop computer), the efficiency of the overall circuit can be high. However, the efficiency is generally a function of output current and typically decreases at low output current. This reduction in efficiency is generally attributable to the losses associated with operating the switching regulator. These losses include, among others, quiescent current losses in the control circuitry of the regulator, switch losses, switch driver current losses and inductor/transformer winding and core losses.

The reduction in efficiency of a switching regulator at low output current can become important in battery-operated systems where maximizing battery lifetime is desirable.

In view of the foregoing, it would be desirable to provide a high efficiency switching regulator.

It would also be desireable to provide a control circuit and method for maintaining high efficiency over broad current ranges, including low output currents, in a switching regulator circuit.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a high efficiency switching regulator.

It is also an object of the present invention to provide a control circuit and method for maintaining high efficiency over broad current ranges, including low output currents, in a switching regulator circuit.

In accordance with these and other objects of the invention, there is provided a circuit and method for controlling a switching voltage regulator having (1) a switch including one or more switching transistors and (2) an output adapted to supply current at a regulated voltage to a load including an output capacitor. The circuit and method generates a control signal to turn the one or more switching transistors OFF under operating conditions when the voltage at the output is capable of being maintained substantially at the regulated voltage by the charge on the output capacitor (e.g., during low output currents). During such periods of time, the load does not consume power from the input power source. Therefore, the regulator efficiency is increased. If desired, other components in the switching regulator, in addition switching transistors, can also be intentionally held OFF to conserve additional power. This additional feature of the present invention can further increase the efficiency of the overall regulator circuit.

The circuit and method of the present invention can be used to control various types of switches in switching regulator circuits, including switches that use either one or more power transistors. Additionally, the circuit and method can be used to control switches in various types of switching regulator configurations, including voltage step-down, voltage step-up and polarity-inversing configurations.

Additionally, the circuit and method of the present invention can vary the OFF time of the switching transistor in response to the input and output voltages of the switching regulator. This feature of the present invention reduces the emission of audible noise from the switching regulator during low input voltage conditions. It also reduces the potential for current runaway during short circuits in the output voltage for some regulator configurations.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and advantages of the present invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

FIG. 1 is a schematic block diagram of a typical prior art switching regulator circuit employing a switch including a pair of synchronously-switched MOSFETs in a step-down configuration;

FIG. 2 is a schematic block diagram of a switching regulator circuit incorporating a first embodiment of the high-efficiency control circuit of the present invention to drive a switch including a pair of synchronously-switched MOSFETs in a step-down configuration;

FIG. 3 is a schematic block diagram of a switching regulator circuit incorporating a second embodiment of the high-efficiency control circuit of the present invention to drive a switch including a switching MOSFET and a switching diode in a step-down configuration;

FIG. 4 is a schematic block diagram of a switching regulator circuit incorporating a "user-activated" embodiment of the high-efficiency control circuit of the present invention to drive a switch including a pair of synchronously-switched MOSFETs in a step-down configuration;

FIG. 5 is a schematic block diagram of a switching regulator circuit incorporating the variable OFF-time control circuit of the present invention;

FIG. 6 is a detailed schematic diagram of an embodiment of the variable OFF-time control circuit of FIG. 5;

FIG. 7 is a detailed schematic block diagram of an exemplary switching regulator circuit incorporating both the variable OFF-time feature and the high-efficiency control circuit of the present invention to drive a switch including a pair of synchronously-switched MOSFETs in a step-down configuration;

FIG. 8 is a schematic block diagram of a switching regulator circuit incorporating a circuit of the present invention for preventing reversals in the polarity of the current in the output inductor of the regulator from drawing power from the load;

FIG. 9 is a schematic block diagram of a switching regulator circuit incorporating the high-efficiency control circuit of the present invention in a step-up configuration; and

FIG. 10 is a schematic block diagram of a switching regulator circuit incorporating the high-efficiency control circuit of the present invention in a polarity-reversing configuration.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic block diagram of a typical prior art switching regulator circuit employing a push-pull switch in a step-down configuration.

Referring to FIG. 1, circuit 10 is used to provide a regulated DC output voltage V.sub.OUT at terminal 12 (e.g., 5 volts) for driving load 14 which, for example, may be a portable or laptop computer or other battery-operated system. Circuit 10 operates from an unregulated supply voltage V.sub.IN coupled to terminal 14 (e.g., a 12 volt battery). Circuit 10 includes push-pull switch 15, driver circuit 20, output circuit 30 and control circuit 35.

Driver circuit 20 is used to drive push-pull switch 15 which includes two synchronously-switched power MOSFETS 16 (p-channel) and 17 (n-channel) stacked in series between supply rail V.sub.IN and ground. Push-pull switch 15 in conjunction with driver circuit 20 is typically referred to as a "half-bridge" configuration. MOSFETS 16 and 17 are used to alternately supply current to output circuit 30 which includes inductor 32 (L1) and output capacitor 34 (C.sub.OUT). Output circuit 30 smooths the alternating supply of current so that load 12 is provided a regulated voltage V.sub.OUT. In order to supply the alternating current, MOSFETS 16 and 17 are respectively driven by P-channel driver 26 and N-channel driver 27, which in turn are both controlled by control circuit 35.

Control circuit 35 includes one-shot circuit which provides an OFF pulse of constant duration (e.g., 2 to 10 microseconds) during which time MOSFET 16 is held OFF and MOSFET 17 is held ON by drivers 26 and 27, respectively. Otherwise, one-shot circuit 25 provides an ON pulse during which time MOSFET 16 is held ON and MOSFET 17 is held OFF. Therefore, one-shot circuit 25 alternately turns MOSFETS 16 and 17 ON and OFF to provide an alternating supply of current to (output circuit 30. The duty cycle of the one-shot circuit 35 is in turn controlled by current amplifier 39.

Control circuit 35 monitors the output voltage V.sub.OUT through resistor-divider network R.sub.1 /R.sub.2 (36A/36B) to provide a feedback voltage V.sub.FB proportional to the output voltage V.sub.OUT. Control circuit 35 also monitors the current I.sub.L through inductor L1 to provide a feedback current I.sub.FB proportional to inductor current I.sub.L. Circuit 10 operates by controlling inductor current I.sub.L so that the feedback voltage V.sub.FB is regulated to be substantially equal to a reference voltage V.sub.REF provided by reference circuit 37. With feedback voltage V.sub.FB being regulated, the output voltage V.sub.OUT is in turn regulated to a higher voltage by the ratio of (R.sub.1 +R.sub.2) to R.sub.2.

Transconductance amplifier 38 is used to compare the feedback voltage V.sub.FB to a reference voltage V.sub.REF. Circuit 10 regulates the output voltage V.sub.OUT as follows. During each cycle when switch 15 is "ON", P-MOSFET 16 is turned ON and the current I.sub.L in inductor L1 ramps up at a rate dependent on V.sub.IN -V.sub.OUT. When I.sub.L ramps up to a threshold level set by output 38A of transconductance amplifier 38, current comparator 39 trips and triggers the one-shot OFF pulse, initiating the "OFF" cycle of switch 15. During the "OFF" cycle, one-shot circuit 25 holds P-MOSFET 16 OFF and turns N-MOSFET 17 ON. This in turn causes the current I.sub.L in inductor L1 to ramp down at a rate dependent on V.sub.OUT. Thus, the duty cycle of the periodic turning OFF of switch 15 is controlled so the current I.sub.L produces a regulated output voltage V.sub.OUT at terminal 12.

As the output load current increases, the voltage drop across R.sub.2 resistor 36B will decrease. This translates into a small error voltage at input 38B of transconductance amplifier 38 that will cause output 38A to increase, thus setting a higher threshold for current comparator 39. Consequently, current I.sub.L in inductor L1 is increased to the level required to support the load current.

Since the OFF time (t.sub.OFF) of one-shot circuit 25 is constant, switching regulator circuit 10 has a constant ripple current in inductor L1 (for constant output voltage V.sub.OUT), but has a frequency which varies with V.sub.IN. The ripple oscillation frequency is given by the equation:

f.sub.RIP =(1/t.sub.OFF) [1-(V.sub.OUT /V.sub.IN)] One disadvantage of circuit 10 in FIG. 1 is that the ripple oscillation frequency f.sub.RIP may decrease to an audible level with low input voltages V.sub.IN. This could occur, for example, when a battery powering the switching regulator circuit is nearly discharged. Inductor L1 may then generate and emit noise that can be objectionable to a user of the device employing the regulator circuit.

An additional disadvantage of prior art circuit 10 is that the inductor current I.sub.L is not well controlled when the output voltage V.sub.OUT is shorted to ground. The basic relationship between inductor current and voltage is given by the equation di/dt=V/L. This means that the rate at which current I.sub.L in inductor L1 decays during the OFF-time depends on the voltage across inductor L1, which is the sum of V.sub.OUT and the drain to source voltage, V.sub.DS, of N-MOSFET 17. During a short, V.sub.OUT approaches zero while V.sub.DS is also very low, resulting in very little decay of current I.sub.L in inductor L1 during t.sub.OFF. However, following each OFF cycle, P-MOSFET 16 is turned back ON until current comparator 39 again trips one-shot constant OFF time control circuit 25. Even for the minimum time that P-MOSFET 16 is ON, the current I.sub.L in inductor L1 may increase by more than it can decrease during t.sub.OFF. This may result in a runaway condition in which the short circuit current may reach destructive levels.

A further disadvantage of prior art circuit 10 results from the constant ripple current in inductor L1. During t.sub.OFF, current I.sub.L in inductor L1 always ramps down by the same amount regardless of the output current of the regulator. At low output currents this can cause the current in inductor L1 to reverse polarity and, thus, pull power from the load. During the following ON cycle, this current again ramps positive such that the average inductor current equals the load current Losses associated with this constant ripple current, along with switching losses due to the charging and discharging of switch 15's MOSFET gates, can produce large reductions in efficiency at low output currents. This will be especially the case if the current in inductor L1 reverses and power is pulled from the load to ground through N-MOSFET 17.

A still further disadvantage of prior art circuit 10 concerns the gate drives to P-MOSFET 16 and N-MOSFET 17. Delays are generally incorporated into drivers 26 and 27 to ensure that one power MOSFET turns OFF before the other turns ON. If there is insufficient deadtime between the conduction of the two MOSFETs (due to, for example, device, circuit processing, or temperature variations), current will be passed directly from input supply V.sub.IN to ground. This "shoot-through" effect can dramatically reduce efficiency, and in some circumstances, can overheat and destroy the power MOSFETs.

FIG. 2 is a schematic block diagram of a switching regulator circuit incorporating a first embodiment of the high-efficiency control circuit of the present invention for driving a switch including a pair of synchronously-switched MOSFETs in a step-down configuration.

Switching regulator circuit 50 includes push-pull switch 15, driver circuit 20 and output circuit 30 similar to those of FIG. 1. Circuit 50 also includes an embodiment 70 of the high-efficiency control circuit of the present invention.

Control circuit 70 includes one-shot circuit 25, current comparator 39 and amplifier 38 similar to those of FIG. 1. However, in addition to those components, control circuit 70 also includes constant current source I.sub.1 72 and hysteretic comparator 74 for providing high efficiency operation at low average current levels.

As will be discussed in greater detail below, constant current source I.sub.1 72 and comparator 74 allow push-pull switch 15 to go into a state of operation where both MOSFETS 16 and 17 are simultaneously OFF under conditions where the output voltage V.sub.OUT can be maintained substantially at the regulated voltage V.sub.REG by output capacitor C.sub.OUT. This state of operation is referred to herein as a "sleep mode." The ability of push-pull switch 15 to go into such a sleep mode is in contrast to the regulator circuit of FIG. 1 where one of the two MOSFETs 16 and 17 is substantially ON at all times. This feature of the present invention reduces the regulator circuit power consumption since push-pull switch 15 does not dissipate power or allow power to be pulled from load R.sub.L to ground in sleep mode.

Furthermore, if desired, while push-pull switch 15 is in the above-described sleep mode, the regulator circuit can turn OFF other circuit components which are not needed while the regulator is in sleep mode. For example, for the embodiment of the present invention shown in FIG. 2, one-shot circuit 25, current comparator 39, current source I.sub.1 72 and amplifier 38 can also be turned OFF in sleep mode. This feature of the present invention allows the regulator circuit to operate at even higher efficiencies than otherwise possible if only push-pull switch 15 were maintained in a sleep mode.

At high load current levels (e.g., greater than 20 percent of the maximum rated output current) control circuit 70 operates similar to control circuit 35 of FIG. 1. In FIG. 2, the current feedback I.sub.FB is again provided to the non-inverting input of current comparator 39. Offset V.sub.OS 76, which preferably is built into amplifier 38, level-shifts feedback voltage V.sub.FB slightly below reference voltage V.sub.REF, thus keeping the output of hysteretic comparator 74 high during high current conditions. When the feedback current I.sub.FB exceeds the current supplied to the inverting input of current comparator 39, the output of comparator 39 goes HIGH so as to initiate the switch "OFF" cycle.

During the "OFF" cycle, output 25A of one-shot circuit 25 is HIGH, which turns P-MOSFET 16 OFF and N-MOSFET 17 ON. After a constant time set by one-shot circuit 25, output 25A goes LOW, thus initiating the next "ON" cycle where P-MOSFET 16 ON and N-MOSFET 17 OFF.

In accordance with the present invention, regulator circuit 50 goes into sleep mode at low output current levels as follows. Hysteretic comparator 74 monitors the feedback voltage V.sub.FB and goes LOW when V.sub.FB exceeds a predetermined voltage value in excess of the reference voltage V.sub.REF. Such a condition is indicative of the output voltage V.sub.OUT exceeding a predetermined voltage value in excess of the regulated voltage V.sub.REG. This over voltage condition is intentionally induced at low average output currents by providing a constant current source I.sub.1 72 coupled in parallel with amplifier 38. During the over voltage condition both MOSFETS 16 and 17 are maintained OFF by way of AND gate 66 and NAND gate 68.

Constant current source I.sub.1 sets a minimum feedback current threshold for current comparator 39. This sets a minimum current required in inductor L1 during each ON cycle to trip comparator 39. In accordance with the present invention, current comparator 39 is intentionally forced to remain ON at current levels that would otherwise cause it to trip. Thus, more current is supplied to inductor L1 than is necessary to maintain the output voltage V.sub.OUT at the regulated voltage V.sub.REG. As a result, V.sub.OUT will begin to increase beyond the regulated voltage V.sub.REG, causing the feedback voltage V.sub.FB to trip hysteretic comparator 74 at a predetermined voltage value in excess of V.sub.REF. When comparator 74 trips, its output goes LOW to turn both MOSFET 16 and 17 OFF to put the regulator circuit into sleep mode.

In the above-described state of operation (i.e., "sleep model") where MOSFETs 16 and 17 are both simultaneously OFF, the output load 14 is supported substantially by output capacitor C.sub.OUT. Hysteretic comparator 74 monitors the feedback voltage V.sub.FB and when V.sub.OUT falls such that V.sub.FB has decreased by the amount of the hysteresis in comparator 74, driver circuit 20 is taken out of sleep mode (where MOSFETS 16 and 17 are both driven OFF) so that a new ON cycle is initiated to supply current to load 14. If the load current remains low, C.sub.OUT will recharge to a voltage level in excess of V.sub.REG and the feedback voltage V.sub.FB will again trip comparator 74 after only a few cycles.

Thus, during light loads, control circuit 70 is adapted to turn both MOSFET 16 and MOSFET 17 OFF when they are not needed to maintain the output voltage substantially at the regulated voltage level if the output capacitor C.sub.OUT is capable of doing so. When the output voltage falls below the regulated voltage level in such a mode, control circuit 70 is adapted to briefly turn switch 15 ON to recharge the output capacitor C.sub.OUT back to a voltage level in excess of the regulated voltage. Therefore, V.sub.OUT will oscillate between upper and lower thresholds separated by the comparator 74 hysteresis voltage multiplied by the ratio of (R.sub.1 +R.sub.2) to R.sub.2. The rate at which the regulator "wakes up" to recharge output capacitor C.sub.OUT will automatically adapt to the load current, maintaining high efficiencies even at low output currents.

In accordance with the present invention, control circuit 70 maintains MOSFETS 16 and 17 OFF over periods of time when the output current is low enough to allow the output capacitor C.sub.OUT to maintain the output voltage substantially at the regulated voltage. Typically, such periods of OFF time, wherein both MOSFETS 16 and 17 are maintained OFF even though the switching regulator is providing a regulated voltage, can extend from less than 100 microseconds to over a few seconds (respectively corresponding to a few switch cycles to over one-hundred-thousand switch cycles for a switching frequency of 100 kiloHertz). Such OFF times typically allow high efficiency to be obtained (e.g., over 90%) over an output current range in excess of 100:1. Because other components in addition the switching transistors can also be maintained OFF during such periods, even higher efficiencies can typically be obtained.

Control circuit 70 of switching regulator 50 shown in FIG. 2 is used to drive a synchronously-switched switch including MOSFETs 16 and 17. As used herein, the term "synchronously-switched switch" refers to a switch including two switching transistors that are driven out of phase to supply current at a regulated voltage to a load. FIG. 3 shows a second embodiment of the high-efficiency control circuit of the present invention adapted to drive a switch including a switching transistor and a switching diode in a step-down configuration.

As shown in FIG. 3, switching regulator circuit 100 includes switch 115 including P-MOSFET 116 and diode 118. Switch 115 is driven by driver 120 including P-driver 126. The turning-ON and turning-OFF of switch 115 is controlled by control circuit 125. Because control circuit 125 is used to only drive one MOSFET (in contrast to control circuit 70 of FIG. 2), it only has one output terminal 125A (taken from the output of NAND gate 68).

Control circuit 125 includes current comparator 39, amplifier 38, hysteretic comparator 74 and one-shot circuit 25, similar to those shown in control circuit 70 of FIG. 2. As discussed above with respect to FIG. 2, at low average output current levels, constant current source I.sub.1 72 is used to intentionally overdrive the current supplied to inductor L1 so as to cause the output voltage V.sub.OUT to increase beyond the regulated voltage level V.sub.REG where the output can be supported substantially by output capacitor C.sub.OUT for extended periods of time. During these extended time periods, P-MOSFET 116 is maintained OFF in a sleep mode so as to increase circuit efficiency.

As discussed above, control circuits 70 and 125 of FIGS. 2 and 3, respectively, provide high-efficiency operation at low average output current levels. Such operation adapts automatically to the output current level. For example, at high output current levels during a first state of operation the switch continually alternates between an ON state and an OFF state to maintain the output voltage V.sub.OUT at the regulated voltage level V.sub.REG. At low output current levels during a second state of operation, where circuit efficiency would otherwise be low, the output voltage V.sub.OUT is able to be maintained substantially at the regulated voltage level V.sub.REG by output capacitor C.sub.OUT without continuously turning the switch ON and OFF. Thus, the control circuit automatically identifies such a condition and allows the regulator circuit to go into a "sleep" mode where a minimal number of circuit components are required to be ON.

In accordance with another feature of the present invention, a regulator circuit can also incorporate a "user activated" embodiment of the control circuit of the present invention where a user input controls whether the regulator circuit is in a "sleep" mode or not. FIG. 4 is a schematic block diagram of a switching regulator circuit incorporating such a "user-activated" embodiment of the high-efficiency control circuit of the present invention for driving a switch including a pair of synchronously-switched MOSFETs in a step-down configuration.

Switching regulator circuit 150 in FIG. 4 includes push-pull switch 15, driver 20, output circuit 30 similar to those in circuit 50 of FIG. 2. Control circuit 170 of regulator circuit 150 includes one-shot circuit 25, current comparator 39 and amplifier 38 also similar to those in circuit 50 of FIG. 2. In contrast to FIG. 2, switch 175 (including switches 176 and 178) is used to manually switch regulator circuit 150 into a sleep mode through user input 175A, which may be a control signal from some other type of control circuit (not shown). Upon the closing of switch 175, switches 176 and 178 both close.

Switch 176 is used to turn N-driver 27 OFF in sleep mode by grounding input 66A of AND gate 66 (which normally is held HIGH by resistor 67 coupled to a positive supply). Switch 178 is used to introduce positive feedback, and therefore hysteresis, into amplifier 38 so as to allow control circuit 170 to maintain the output voltage V.sub.OUT substantially at the regulated voltage level V.sub.REG in sleep mode. (Resistor R.sub.HYS, coupled between reference circuit 37 and the non-inverting input of transconductance amplifier 38, is used to assist in feeding back the output of amplifier 38 into the non-inverting input of amplifier 38.)

Switch 178 allows amplifier 38 to overdrive the supply of current to inductor L1 (through P-MOSFET 16) so as to intentionally drive the output voltage V.sub.OUT to a predetermined level in excess of the regulated voltage level V.sub.REG. After being driven to such voltage level, the hysteresis in amplifier 38 maintains P-driver 26 OFF until the feedback voltage V.sub.FB falls by at least the hysteresis voltage. At that point, output 39A of current amplifier 39 goes HIGH to trigger one-shot circuit 25 so that P-MOSFET 16 is turned ON to recharge the output capacitor C.sub.OUT to the predetermined voltage level in excess of the regulated voltage level V.sub.REG.

As discussed above, control circuit 170 periodically wakes up during sleep mode to turn P-MOSFET 16 ON to recharge the output capacitor C.sub.OUT. It will be apparent to those of ordinary skill in art that although N-MOSFET 15 is maintained OFF during such wake-up periods, this does not have to be the case. For example, while control circuit 170 is recharging output capacitor C.sub.OUT , such recharging could be accomplished by alternately turning the switching transistors OFF so as to vary the duty cycle and thereby recharge the output capacitor C.sub.OUT .

Thus, regulator circuit 150 operates to increase efficiency at low current levels as in regulator circuit 50 of FIG. 2 if a user manually activates a switch. However, in contrast to regulator circuit 50 of FIG. 2, regulator circuit 150 does not automatically adapt to the output current levels. For example, circuit 150 does not take itself out of sleep mode as the average output current increases--it relies upon user deactivation.

As discussed above, the embodiments of the control circuits of the present invention shown in FIGS. 2-4 include one-shot circuit 25. In accordance with another feature of the present invention, the one-shot circuit could be replaced with other types of circuits that control the duty cycle of the power switch. For example, one-shot circuit 25 could be replaced with a pulse-width modulator circuit that provides a pulse-width modulated signal in response to a control signal. Of course, other types of circuits could be used as well.

In accordance with another feature of the present invention, one-shot circuit 25, which provides a constant OFF-time signal, could be replaced with a one-shot circuit that provides a variable OFF-time control signal dependent upon the output voltage (V.sub.OUT) and the input voltage (V.sub.IN). This feature of the present invention can be used to reduce the generation and emission of audible noise from inductor L1 at low input voltages. As discussed above, such noise is associated with oscillation in the inductor current. Furthermore, this feature of the present invention can also be used to control the short circuit current if the output is short circuited.

FIG. 5 is a schematic block diagram of an exemplary switching regulator circuit incorporating the variable OFF-time control circuit of the present invention.

Switching regulator circuit 200 includes push-pull switch 15, driver circuit 20, current feedback circuit 210, voltage feedback circuit 220, feedback control circuit 230 and variable OFF-time circuit 240. Feedback control circuit 230 monitors the output current and output voltage through inputs 232 and 234, respectively, and provides a trigger signal at terminal 236 to initiate the OFF cycle of switch 15. Variable OFF-time circuit 240 is used to control the OFF time as follows.

Circuit 240 includes one-shot generator 245 which is triggered by feedback control circuit 230 through terminal 236. One-shot generator 245 includes an additional terminal 245A coupled to control capacitor (C.sub.CON) 246 whose voltage is monitored by generator 245. In accordance with the present invention, OFF-time control circuit 250 controls the discharging of capacitor C.sub.CON, and thus the capacitor voltage, so as to in turn control the OFF time of generator 245. OFF-time control circuit 250 monitors the input and output voltages (V.sub.IN and V.sub.OUT) and, depending upon their values, adjusts the OFF time accordingly.

In accordance with the present invention, if the input voltage V.sub.IN decreases so that the inductor L1 oscillation frequency f.sub.RIP discussed above falls into an audible range, the OFF time is decreased so that f.sub.RIP will accordingly increase out of an audible range. Also, if the output voltage V.sub.OUT decreases due to a short circuit so that the voltage across inductor L1 is too low to allow adequate decay in inductor current during the OFF cycle, the OFF time is increased so as to avoid a current runaway condition.

In the present embodiment the discharging of control capacitor C.sub.CON is regulated by controlling the magnitude of control current I.sub.CON. For example, at low input voltages I.sub.CON is increased by OFF-time control circuit 250 so that the voltage on control capacitor C.sub.CON rapidly falls. When the control capacitor voltage falls below a predetermined value, the ON cycle of switch 15 is initiated. Additionally, at low output voltages I.sub.CON is decreased by OFF-time control circuit 250 so that the voltage on control capacitor C.sub.CON slowly decays to lengthen the OFF time.

Although switching regulator circuit 200 shown in FIG. 5 relies upon a particular circuit for discharging a capacitor to control the OFF time, it is apparent that other circuits for performing this same function in response to the input and output voltages can also be used. For example, if desired, an operational amplifier could be used to control the OFF-time.

Thus, a one-shot circuit has been discussed which provides a variable OFF-time control signal that adapts to the input and output voltage levels. This feature of the present invention is used to reduce the generation and emission of audible noise from the regulator circuit at low input voltage levels (i.e., reduce t.sub.OFF at low input voltages) and to limit the short circuit current if the output is short circuited (i.e., increase t.sub.OFF at low output voltages).

FIG. 6 is a detailed schematic diagram of an exemplary embodiment of the variable OFF-time control circuit of FIG. 5.

OFF-time control circuit 250 accepts as inputs V.sub.IN and V.sub.OUT at terminals 252 and 254, respectively, and provides an output I.sub.CON at terminal 256. As discussed above, I.sub.CON provides for the controlled discharging of a control capacitor C.sub.CON coupled to terminal 256. Control circuit 250 controls the magnitude of I.sub.CON, and therefore controls the time it takes control capacitor C.sub.CON to discharge. Control circuit 250 includes current source 260 (for providing current I.sub.CN2), current source 270 (for providing current I.sub.CN1), current compensation circuit 280 and current mirror output circuit 295. Control circuit 250 works as follows.

Current mirror output circuit 295 is a current mirror circuit including transistor 296 and transistor 298 (having its gate 298A connected to its drain 298B). Circuit 295 accepts a controlled reference current I.sub.CREF at input 295A and provides a proportional output current I.sub.CON related to the aspect ratios of transistor 296 and 298 (as in conventional current mirror circuits). In accordance with the present invention, I.sub.CREF will be equal to either I.sub.CN1 or (I.sub.CN1 +I.sub.CN2) depending upon voltages V.sub.IN and V.sub.OUT on input terminals 252 and 254, respectively.

When V.sub.IN -V.sub.OUT is greater than 1.5 volts, transistor 262 conducts sufficient current (from transistor 264 and current supply I.sub.6) to hold transistor 266 OFF. With transistor 266 OFF, current I.sub.CN2 will be zero and current I.sub.CREF will therefore be equal to current I.sub.CN1 provided at output terminal 270A of current source 270.

Current I.sub.CN1 is supplied by a current mirror circuit composed of transistor 272 and transistor 274 (having its gate 274A connected to its drain 274B). In accordance with the present invention, the reference current I.sub.CN1REF flowing from transistor 274 will be equal to either I.sub.CN1A or (I.sub.CN1A +I.sub.CN1B), depending upon whether transmission gate 282 is open or closed, respectively.

Transmission gate 282 is controlled by comparator 284 and will be OPEN when V.sub.OUT is less than V.sub.TH3. Under OPEN conditions, I.sub.CN1REF will be equal to I.sub.CN1A which goes to the collector of transistor 276. This current is derived by dividing V.sub.OUT by the output divider (composed of resistors 271 and 273) to produce voltage V.sub.FB1 (at the base of transistor 279). Voltage V.sub.FB1 is then level shifted up by the base-emitter voltage of transistor 279 and then down by the base-emitter voltage of transistor 276 where it appears across emitter resistor 278. The resulting transistor 276 collector current is then proportional to the output voltage V.sub.OUT, causing control capacitor C.sub.CON to be discharged at a rate which is proportional to the discharge rate of the current in inductor L1.

Thus, when the output voltage V.sub.OUT is low, such as during a fault or start-up condition, t.sub.OFF will be lengthened to allow the additional time required for the current to ramp down in inductor L1.

When the output voltage V.sub.OUT is greater than V.sub.TH3, the output of comparator 284 closes transmission gate 282 to couple an additional compensation current I.sub.CN1B to the drain of transistor 274 to provide current compensation through current compensation circuit 280. Compensation current I.sub.CN1B is equal to current I.sub.TRIM minus the drain current of transistor 286. Transistors 286 and 288 serve to mirror the collector current in transistor 290 (which is derived in a similar manner to the collector current in transistor 276 discussed above, except that voltage V.sub.REF is used instead of voltage V.sub.FB1).

Compensation current I.sub.CN1B has two purposes: 1) to serve as a trimming current to set a desired control current I.sub.CON when the output voltage V.sub.OUT is substantially at its regulated level, and 2) to maintain a substantially constant control current I.sub.CON over a wide range of operating temperatures. During typical circuit manufacturing, variations in the resistance of resistor 278 would normally cause control current I.sub.CON to be larger or smaller than desired. By trimming I.sub.TRIM while in production, compensation current I.sub.CN1B can be adjusted to add or subtract from the collector current (I.sub.CN1A) of transistor 276 as required to provide a predetermined control current I.sub.CON. Additionally, if resistors 278 and 292 are matched (i.e., designed and fabricated similarly), then control current I.sub.CON variations due to the temperature variation of the resistance of resistor 278 will be substantially cancelled by a corresponding change in the resistance of resistor 292.

If the output voltage V.sub.OUT is less than voltage V.sub.TH3, the output of comparator 284 opens transmission gate 282 and thus inhibits current compensation. This ensures that control current I.sub.CON will approach zero as the output voltage V.sub.OUT approaches zero, thus guaranteeing control of the inductor current I.sub.L during an output short circuit.

When V.sub.IN falls to the point that V.sub.IN -V.sub.OUT is less than 1.5 volts, the current in transistor 262 no longer holds transistor 266 OFF. As V.sub.IN decreases further, transistor 266 adds additional current (I.sub.CN2) into current mirror output circuit 295, thereby increasing control current I.sub.CON and, thus, reducing t.sub.OFF. This in turn stabilizes the operating frequency as V.sub.IN decreases, reducing potential audibility problems. Current source I.sub.7 determines the maximum current that transistor 266 adds to control current I.sub.CON.

Thus, when V.sub.IN falls so that V.sub.IN -V.sub.OUT is less than 1.5 volts (e.g., when a battery is nearly discharged), t.sub.OFF will be reduced to increase the oscillation frequency of the regulator circuit so that the generation and emission of audible noise is reduced.

Although variable OFF-time control circuit 250 was discussed above with respect to a regulator circuit which includes push-pull switch 15 and driver 20, it will be apparent that the variable OFF-time feature of the present invention could be used in other regulators as well. For example, this feature could also be used in the regulator circuits of FIGS. 3 and 4 and other circuits that employ one-shot generators to provide a regulated voltage.

FIG. 7 is a detailed schematic block diagram of an exemplary switching regulator circuit incorporating both the variable OFF-time feature and the high-efficiency control circuit of the present invention to drive a switch including a pair of synchronously-switched MOSFETs in a step-down configuration.

Switching regulator 300 includes push-pull switch 15, driver 20, output circuit 30 and control circuit 350. Control circuit 350 includes one-shot generator 245, variable OFF-time control circuit 250 for controlling the OFF cycle time and comparator 74 for providing high-efficiency operation at low average output current levels. Switching regulator 300 works as follows.

When the load current exceeds, for example, approximately 20 percent of the maximum output current, the loop operates in a continuous mode wherein comparator 74 does not override output 245A of one-shot generator 245. With V.sub.IN -V.sub.OUT greater than 1.5V, operation is substantially similar to that described for FIG. 1. The inductor current is sensed by means of the voltage drop across resistor R.sub.SENSE, and the threshold for the current comparator 39 is set by the voltage drop across resistor R.sub.3. Built-in offset V.sub.OS (e.g., about 10 mv) levelshifts feedback voltage V.sub.FB slightly below reference voltage V.sub.REF, thus keeping the output of comparator 74 HIGH in this mode. When the voltage across resistor R.sub.SENSE exceeds the threshold across resistor R.sub.3, the output of comparator 39 goes HIGH and the RBAR input of RS flip-flop 310 goes LOW, resetting RS flip-flop 310, and thus, initiating the switch OFF cycle.

During the OFF cycle, switch signal V.sub.SWB is HIGH, which turns P-MOSFET 16 OFF, N-MOSFET 17 ON and allows I.sub.CON to discharge control capacitor C.sub.CON. The OFF time, t.sub.OFF, is in turn determined by the time it takes control capacitor C.sub.CON to discharge from its initial voltage to V.sub.TH1, coupled to the non-inverting input of comparator 312. When control capacitor C.sub.CON discharges to voltage V.sub.TH1, the output of comparator 312 goes LOW, thus setting RS flip-flop 310 and initiating the next ON cycle. Voltage V.sub.TH1 is higher than voltage V.sub.TH2, thus causing the output of comparator 315 to remain LOW in the continuous mode.

In accordance with present embodiment, the OFF time is controlled by variable OFF-time control circuit 250 described above with respect to FIGS. 5 and 6. Accordingly, circuit 250 includes inputs 252 and 254 coupled to V.sub.IN and V.sub.OUT, respectively, to monitor those voltages.

Current source I.sub.1 sets a minimum voltage threshold across resistor R.sub.3 for current comparator 39. This sets a minimum current required in inductor L1 during each ON cycle to trip comparator 39. If the resulting average inductor current flowing to the output is greater than the load current, then output voltage V.sub.OUT will begin to increase, causing feedback voltage V.sub.FB to trip the hysteretic comparator 74. Of course, the inductance of inductor L1 and OFF time t.sub.OFF are preferably chosen so that the inductor ripple current is not below zero when such tripping occurs. When comparator 74 trips, its output goes LOW and overrides the Q output of RS flip-flop 310, immediately switching switch signal V.sub.SWB high. As discussed above, this automatically initiates the beginning of the "sleep" mode of operation.

In sleep mode, capacitor C.sub.CON discharges as before, but does not initiate a new switch ON cycle when comparator 312 trips. As discussed above, this is because until feedback voltage V.sub.FB has fallen by the amount of hysteresis in comparator 74, the LOW at output 74A forces switch signal V.sub.SWB to remain HIGH through NAND gate 316. Accordingly, control capacitor C.sub.CON continues to discharge below voltage V.sub.TH2, causing output 315A of comparator 315 to go HIGH. This in turn causes the N-MOSFET 17 as well as the P-MOSFET 16 to be turned OFF. In addition, unused circuit components such as amplifier 38 and comparators 39 and 312 are also turned OFF when the regulator circuit is in sleep mode. As discussed above, this decreases bias currents substantially during sleep mode, further increasing efficiency at low output current levels.

During the extended off times in sleep mode, much of the regulator and both MOSFETS 16 and 17 are turned off, and the output load is supported substantially by output capacitor C.sub.OUT. However, when the output voltage V.sub.OUT falls such that the feedback voltage V.sub.FB has decreased by the amount of hysteresis in comparator 74, all circuit components are again turned on and a new ON cycle is initiated to supply current to the output. If the load current remains low, output capacitor C.sub.OUT will recharge, and the feedback voltage V.sub.FB will again trip comparator 74 after only a few switch cycles. Thus, during light load conditions, the output voltage V.sub.OUT will oscillate between upper and lower thresholds values, as discussed above.

Whenever P-MOSFET 16 is ON, its gate-to-source voltage also appears across MOSFET 334, turning MOSFET 334 ON. This pulls the drain of MOSFET 334 HIGH, and inhibits N-drive 27. Following a LOW-to-HIGH V.sub.SWB transition, the voltage on the gate of P-MOSFET 16 must rise to a level where MOSFET 334 is conducting less than current source 335 before the drain voltage of MOSFET 334 falls and allows the N-MOSFET 17 to be turned ON. Current I.sub.M1 is purposely made small so that the gate of MOSFET 334 must rise to within 2 volts of the input voltage V.sub.IN before the drive is enabled, ensuring that the P-MOSFET is completely OFF when N-MOSFET 17 turns ON. In a similar manner, MOSFET 332 and current source I.sub.M2 333 ensure that the N-MOSFET 17 is completely OFF when the P-MOSFET 16 turns ON. This prevents simultaneous conduction regardless of the driver speeds or MOSFET sizes, ensuring maximum possible efficiency. This feature of the present embodiment is discussed in more detail in copending commonly-assigned U.S. patent application Ser. No. 07/893,523, filed Jun. 4, 1992, now U.S. Pat. No. 5,365,118 which is hereby incorporated by reference in its entirety. If desired, the control circuit of the present invention can also include circuitry for accommodating transient switch signals as described in copending commonly-assigned U.S. patent application Ser. No. 08/035,423, filed concurrently herewith, now U.S. Pat. No. 5,408,150, which is also hereby incorporated by reference in its entirety.

Schottky diode D2 coupled across N-MOSFET 17 shown in FIG. 7 only conducts during the deadtime between the conduction of MOSFETS 16 and 17. Diode D2's purpose is to prevent the body diode of N-MOSFET 17 from turning on and storing charge during the deadtime, which could reduce efficiency (e.g., by approximately 1 percent) in some cases. Diode D2 preferably is selected with a forward voltage of less than about 0.5 volts when conducting the maximum output current.

In accordance with the present invention, the control circuit shown in FIG. 7, when incorporated into a 5-volt synchronous step-down switching regulator, is capable of achieving over 90 percent efficiency (for an input voltage of approximately 10 volts) while the output current varies over two orders of magnitude (e.g., 20 mA to 2 A). Under some operating conditions (e.g., for an input voltage of 6 volts) efficiencies of over 95 percent can be maintained over such current levels. Such a control circuit is particularly useful in notebook and palm-top computers, portable instruments, battery-operated digital devices, cellular telephones, DC power distributions systems and GPS systems.

As discussed above with respect to FIG. 1, a disadvantage of prior art control circuit 10 is that at low output currents the current in inductor L1 may reverse polarity if during t.sub.OFF the current ramps down too much. This may result in power being pulled from the load to ground, through N-MOSFET 17, with an associated reduction in circuit efficiency. In accordance with a still further feature of the present invention, the control circuit can include a circuit for turning OFF the N-MOSFET to prevent such power from being pulled from the load if the inductor current reverses polarity.

FIG. 8 is a schematic block diagram of an exemplary switching regulator circuit incorporating a circuit of the present invention for preventing reversals in the polarity of the current in the output inductor of the regulator from drawing power from the load.

Switching regulator 400 includes push-pull switch 15, driver circuit 20 and output circuit 30 similar to those of FIG. 1. Circuit 400 also includes an embodiment 470 of the high-efficiency control circuit of the present invention for preventing reversals in the polarity of output inductor L1 current from drawing power from the load.

Control circuit 470 includes one-shot circuit 25, current comparator 39 and transconductance amplifier 38 similar to those of FIG. 1. In addition to those components, control circuit 470 also includes comparator 471 and gate 472 for preventing reversals in inductor current polarity from drawing power from the load at low average current levels. Control circuit 470 works as follows.

When output 25a of one-shot circuit goes HIGH to turn P-MOSFET 16 OFF and N-MOSFET 17 ON, the inductor current I.sub.L begins to ramp down. During low average output currents, this current may ramp down towards zero and, eventually, may go negative. Control circuit 470 works by monitoring the inductor current I.sub.L, through current feedback signal I.sub.FB2, and turns N-MOSFET 17 OFF before such current reversals can occur. This prevents N-MOSFET 17 from drawing power from the load to ground.

Comparator 471 includes an input 471a adapted to monitor inductor current I.sub.L by way of current feedback signal I.sub.FB2. When current feedback signal I.sub.FB2 falls below current I.sub.4 applied to input 471b of comparator 471, comparator output 471c goes LOW and, therefore, turns N-MOSFET 17 OFF by way of NAND gate 472. The turning OFF of N-MOSFET 17 prevents current reversals in inductor current I.sub.L from drawing power from load 14 to ground through N-MOSFET 17.

After N-MOSFET 17 is turned OFF, it will again be allowed to turn ON as soon as feedback current I.sub.FB2 exceeds current I.sub.4 to cause comparator output 471c to go HIGH. Generally, comparator output 471c will again go HIGH after one-shot circuit 25 turns P-MOSFET 16 ON, which, in turn, causes the inductor current I.sub.L to again ramp up. Such ramping up will allow current feedback signal I.sub.FB2 to exceed I.sub.4 and, therefore, cause comparator output 471c to go HIGH. While comparator 471c is HIGH, one-shot circuit 25 solely controls the turning ON of N-MOSFET 17.

Thus, control circuit 470 includes circuitry for intentionally holding N-MOSFET 17 OFF during periods when current reversals would otherwise allow power to be drawn from the load. This feature of the present invention can increase circuit efficiency at low average output current levels when current reversals are most like to occur.

It will be apparent to those of ordinary skill in the art that although comparator 471 monitors the inductor current I.sub.L through feedback current I.sub.FB2, other means of detecting current reversals in the inductor current I.sub.L could be used as well. For example, comparator 471 could monitor current feedback signal I.sub.FB1 just as well so that only one type of current feedback signal is employed in control circuit 470. Additionally, many others means of generating a feedback signal indicative of current reversal in inductor current I.sub.L could be used as well (see, e.g., resistor R.sub.SENSE in FIG. 7).

The high-efficiency control circuit of the present invention was discussed above with respect to FIGS. 1-8 wherein the switching regulator was configured in a voltage step-down configuration. It will be apparent that the control circuit of the present invention could be used in other configurations as well. For example, FIG. 9 shows a schematic block diagram of a switching regulator circuit incorporating the high-efficiency control circuit of the present invention in a voltage step-up configuration.

Switching regulator 500 includes synchronously-switched switch 15' wherein the drains of P-channel MOSFET 16 and N-channel MOSFET 17 are coupled together and to one side of inductor L1. The other side of inductor L1 is coupled to input V.sub.IN. Control circuit 70 drives driver circuit 20' including inverting P-driver 26' and inverting N-driver 27', which in turn drive P-channel MOSFET 16 and N-channel MOSFET 17, respectively.

Thus, as shown in FIG. 9, the control circuit of the present invention can be used in switching configurations wherein an input voltage V.sub.IN is stepped up to a regulated output voltage V.sub.OUT. As is the case with the step-down configurations shown in FIGS. 2-8, the control circuit of FIG. 9 can be used in other types of step-up configurations as well. For example, one-shot circuit 25 shown in FIG. 9 can include an additional input for monitoring the input voltage V.sub.IN to reduce the generation and emission of audible noise from inductor L1 at low input voltages as discussed above with respect to FIGS. 5 and 6. Also, switching regulator 500 can include circuitry to hold P-MOSFET 16 OFF during periods when the polarity of inductor current I.sub.L would otherwise reverse, as discussed above with respect to FIG. 8.

FIG. 10 shows a schematic block diagram of a switching regulator circuit incorporating the high-efficiency control circuit of the present invention in a voltage polarity-inversing configuration.

Switching regulator 600 includes switch 15" wherein the drain of P-channel MOSFET 16 is coupled to one side of inductor L1 and to V.sub.OUT through diode D601. The other side of inductor L1 is coupled to ground. The source of P-channel MOSFET 16 is coupled to the positive input voltage V.sub.IN. Control circuit 70' drives driver circuit 20" including P-driver 26 which, in turn, drives P-channel MOSFET 16.

Control circuit 70' operates substantially similar to control circuit 70 discussed above except for the following. Voltage feedback to control circuit 70' is provided by resistors R1 and R2 and amplifier 602. Amplifier 602 inverts the negative polarity voltage at V.sub.OUT to provide a positive polarity feedback voltage to control circuit 70'.

Thus, as shown in FIG. 10, the control circuit of the present invention can be used in switching configurations wherein an input voltage V.sub.IN is inverted to a regulated output voltage of opposite polarity V.sub.OUT. As is the case with the step-down configurations shown in FIGS. 2-8, the control circuit of FIG. 10 can be used in other types of polarity-inversing configurations as well. For example, one-shot circuit 25 shown in FIG. 10 can include an additional input for monitoring the input voltage V.sub.IN to reduce the generation and emission of audible noise from inductor L1 at low input voltages. Furthermore, one-shot circuit 25 can include an input for monitoring the output voltage V.sub.OUT to control the short circuit current if the output is short circuited as discussed above with respect to FIGS. 5 and 6. Also, if regulator 600 was synchronously switched and included an N-MOSFET instead of D601, the regulator could include circuitry to hold such an N-MOSFET OFF during periods when the polarity of inductor current I.sub.L would otherwise reverse, as discussed above with respect to FIG. 8.

It will be apparent to those of ordinary skill in the art that although the present invention has been discussed above with reference to a hysteretic voltage comparator for generating the sleep mode control signal to cause the switching regulator to go into and awake from the sleep-mode, other means for performing the same function are also possible. For example, if desired, the sleep mode control signal could be generated in response to a monitored output current. Furthermore, the switching regulator could be taken out of the sleep mode a predetermined time period after going into such a mode, instead after the output voltage falls below a predetermined threshold voltage, as illustrated above.

It will also be apparent that although the present invention has been discussed above with reference to FIGS. 1-10, wherein the power switches were either a pair of complementary MOSFETS (i.e., one p-channel and one n-channel) or a single p-channel MOSFET (FIG. 3), the present invention is applicable to other types of switches as well. For example, the power switch could include a pair of N-channel MOSFETS, a pair of P-channel MOSFETS, or bipolar junction transistors.

Thus, a control circuit and method for maintaining high efficiency over broad current ranges in a switching regulator circuit has been provided.

One skilled in the art will thus appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.

Claims

1. A circuit for controlling a switching voltage regulator having a switch and an output adapted to supply current at a regulated voltage to a load including an output capacitor, the switch coupled between an input voltage and an output voltage and including one or more switching transistors, the circuit comprising:

a first circuit for monitoring an output to generate a first feedback signal;

a second circuit for generating a first control signal during a first state of circuit operation, the second circuit including a one-shot circuit that generates the first control signal to switch the one or more switching transistors "on" or "off" over a first period of time to maintain the output at the regulated voltage, the one-shot circuit being triggered responsive to the first feedback signal, the first period of time being responsive to at least one of the input voltage and the output voltage.

2. The circuit of claim 1, wherein the first period of time is responsive to the input voltage.

3. The circuit of claim 2, wherein:

the switch is coupled to an inductor;

the first period of time is decreased in response to a decrease in the input voltage; and

an oscillation frequency of the ripple current through the inductor is increased from an audible frequency to one that does not generate substantial user audible noise.

4. The circuit of claim 1, wherein the first period of time is responsive to the output voltage.

5. The circuit of claim 4, wherein:

the switch is coupled to an inductor;

the first period of time is increased in response to a decrease in the output voltage; and

the total decrease in current through the inductor is increased while the first control signal is generated.

6. The circuit of claim 1, wherein the circuit includes a capacitor coupled to the one-shot circuit and a variable current source for controlling the discharging rate of the capacitor, the discharging rate being responsive to at least one of the input voltage and the output voltage to control the first period of time.

7. The circuit of claim 6, wherein the first period of time is responsive to the input voltage.

8. The circuit of claim 7, wherein:

the switch is coupled to an inductor;

the first period of time is decreased in response to a decrease in the input voltage; and

an oscillation frequency of the ripple current through the inductor is increased from an audible frequency to one that does not generate substantial user audible noise.

9. The circuit of claim 6, wherein the first period of time is responsive to the output voltage.

10. The circuit of claim 9, wherein:

the switch is coupled to an inductor;

the first period of time is increased in response to a decrease in the output voltage; and

the total decrease in current through the inductor is increased while the first control signal is generated.

11. A switching voltage regulator that generates an output at an output node from an input at an input node, the output node coupled to an output capacitor, the regulator comprising:

a switching transistor having a first terminal coupled to the input node, a second terminal, and a third terminal;

a driver circuit having a first terminal, and a second terminal coupled to the second terminal of the switching transistor;

an inductor having a first terminal coupled to the third terminal of the switching transistor, and a second terminal coupled to the output node;

a feedback circuit having a first terminal coupled to the output node, and a second terminal, the feedback circuit producing a feedback signal at the second terminal of the feedback circuit;

a feedback control circuit having a first terminal coupled to the second terminal of the feedback circuit, and a second terminal, the feedback control circuit producing a trigger signal at the second terminal of the feedback control circuit, said trigger signal being produced responsive to the feedback signal;

an off-time control circuit having a first terminal and a second terminal, the off-time control circuit producing an off-time control signal at the first terminal of the off-time control circuit, the second terminal of the off-time control circuit being coupled to one of the input node or the output node;

a one-shot generator having a first terminal coupled to the second terminal of the feedback control circuit, a second terminal coupled to the first terminal of the off-time control circuit, and a third terminal coupled to the first terminal of the driver circuit, the one-shot generator generating a switch signal on the third terminal to cause the driver to place the switching transistor in an off state starting upon receipt of the trigger signal, and continuing for a first period of time determined by the off-time control signal.

12. The regulator of claim 11, wherein the feedback circuit produces a voltage feedback signal at the second terminal of the feedback circuit.

13. The regulator of claim 11, wherein the feedback circuit produces a current feedback signal at the second terminal of the feedback circuit.

14. The regulator of claim 13, wherein the regulator further comprises a voltage feedback circuit having a first terminal coupled to the output node, and a second terminal, the voltage feedback circuit producing a voltage feedback signal at the second terminal of the voltage feedback circuit, and wherein the feedback control circuit has a third terminal coupled to the second terminal of the voltage feedback circuit, and the trigger signal is produced responsive to the current feedback signal and the voltage feedback signal.

15. The regulator of claim 11, wherein the second terminal of the off-time control circuit is coupled to the input node, and the off-time control signal is generated responsive to a voltage at the input node to vary the first period of time.

16. The regulator of claim 15, wherein the off-time control circuit produces an off-time control signal that decreases the first period of time in response to a decrease in the voltage at the input node, whereby an oscillation frequency of the ripple current through the inductor is increased from an audible frequency to a substantially inaudible frequency.

17. The regulator of claim 11, wherein the second terminal of the off-time control circuit is coupled to the output node, and the off-time control signal is generated responsive to a voltage at the output node to vary the first period of time.

18. The regulator of claim 17, wherein the off-time control circuit produces an off-time control signal that increases the first period of time in response to a decrease in the voltage at the output.

19. The regulator of claim 11, wherein the second terminal of the off-time control circuit is coupled to the input node and the off-time control circuit further comprises a third terminal coupled to the output node, and the off-time control signal is generated responsive to a voltage at the input node and a voltage at the output node to vary the first period of time.

20. The regulator of claim 11, wherein the one-shot generator includes a control capacitor coupled between the second terminal of the one-shot generator and ground, and the off time control circuit comprises a variable current source that controls the discharging rate of the control capacitor.

21. The regulator of claim 20, wherein the second terminal of the off-time control circuit is coupled to the input node, and the variable current source controls the discharging rate of the control capacitor responsive to a voltage at the input node to vary the first period of time.

22. The regulator of claim 21, wherein the variable current source controls the discharging rate of the control capacitor to decrease the first period of time in response to a decrease in the voltage at the input node, whereby an oscillation frequency of the ripple current through the inductor is increased from an audible frequency to a substantially inaudible frequency.

23. The regulator of claim 20, wherein the second terminal of the off-time control circuit is coupled to the output node, and the variable current source controls the discharging rate of the control capacitor responsive to a voltage at the output node to vary the first period of time.

24. The regulator of claim 23, wherein the variable current source controls the discharging rate of the control capacitor to increase the first period of time in response to a decrease in the voltage at the output node.

25. The regulator of claim 20, wherein the second terminal of the off-time control circuit is coupled to the input node and the off-time control circuit further comprises a third terminal coupled to the output node, and the variable current source controls the discharging rate of the control capacitor responsive to a voltage at the input node and a voltage at the output node to vary the first period of time.

26. The regulator of claim 25, wherein the off-time control circuit comprises a control circuit that produces a control current to control the variable current source responsive to a voltage at the input node and a voltage at the output node to vary the first period of time.

27. The regulator of claim 26, wherein the control circuit comprises:

a first current source, providing a first current;

a second current source, providing a second current;

a current compensation circuit; and

a current mirror output circuit that outputs the control current.

28. The regulator of claim 27, wherein the current mirror output circuit produces a current proportional to the first current, or to the sum of the first current and the second current, depending on the voltage at the input node and the voltage at the output node.

29. The regulator of claim 27, wherein the second current source causes the second current to be zero when a difference between the voltage at the input node and a voltage at the output node is greater than a predetermined value.

30. The regulator of claim 29, wherein the second current increases responsive to a decrease in the voltage at the input node when the difference between the voltage at the input node and the voltage at the output node is less than the predetermined value.

31. The regulator of claim 27, wherein the current compensation circuit adjusts the control current to compensate for changes in temperature.

32. A circuit for controlling a switching voltage regulator having a switch and an output adapted to supply current at a regulated voltage to a load including an output capacitor, the switch coupled between an input voltage and an output voltage and including one or more switching transistors, the circuit comprising:

means for generating a current feedback signal;

means for generating a voltage feedback signal;

means for generating a trigger signal responsive to the current feedback signal and the voltage feedback signal;

means for generating an off-time control signal responsive to at least one of the input voltage and the output voltage; and

one-shot means for placing the switch into an off state responsive to the trigger signal, the switch remaining-in the off state for a period of time responsive to the off-time control signal.

33. The circuit of claim 31, wherein the means for generating the off-time control signal causes the period of time to decreases in response to a decrease in the input voltage.

34. The circuit of claim 31, wherein the means for generating the off-time control signal causes the period of time to increase in response to a decrease in the output voltage.

35. A switching voltage regulator having an output node and an input node, the output node coupled to an output capacitor, the regulator comprising:

a switching transistor having a first terminal coupled to the input node, a second terminal, and a third terminal;

a driver circuit having a first terminal, and a second terminal coupled to the second terminal of the switching transistor;

an inductor having a first terminal coupled to the third terminal of the switching transistor, and a second terminal coupled to the output node;

a feedback circuit having a first terminal coupled to the output node, and a second terminal;

a feedback control circuit having a first terminal coupled to the second terminal of the feedback circuit, and a second terminal;

a one-shot generator having a first terminal coupled to the second terminal of the feedback control circuit, a second terminal, and a third terminal coupled to the first terminal of the driver circuit, the one-shot generator including a control capacitor coupled between the second terminal of the one-shot generator and ground;

an off-time control circuit having a first terminal coupled to the second terminal of the one-shot generator, and a second terminal coupled to one of the input node or the output node, the off-time control circuit including a variable current source that controls the discharging rate of the control capacitor.

36. The regulator of claim 35, wherein the feedback circuit comprises a voltage feedback circuit.

37. The regulator of claim 35, wherein the feedback circuit comprises a current feedback circuit.

38. The regulator of claim 37, wherein the regulator further comprises a voltage feedback circuit having a first terminal coupled to the output node, and a second terminal, and wherein the feedback control circuit has a third terminal coupled to the second terminal of the voltage feedback circuit.

39. The regulator of claim 35, wherein the off-time control circuit further comprises a second terminal coupled to the input node, and the off time control signal is generated responsive to a voltage at the input node to vary the first period of time.

40. The regulator of claim 35, wherein the second terminal of the off-time control circuit is coupled to the input node.

41. The regulator of claim 35, wherein the second terminal of the off-time control circuit is coupled to the output node.

42. The regulator of claim 35, wherein the second terminal of the off-time control circuit is coupled to the input node and the off-time control circuit further comprises a third terminal coupled to the output node.