Patent Application
20180248398
This application claims priority to Italian Application No. 102017000022236, filed on Feb. 28, 2017, which application is hereby incorporated herein by reference.
The description refers generally to an electronic circuit, and, in particular embodiments, to control circuits, a corresponding power supply, apparatus and method.
Switching power supplies with galvanic isolation between output voltage and input voltage are widely used.
These may, for example, be PWM power supplies with galvanic isolation between the primary side, which can be connected directly to the domestic electricity distribution network (for example 220 V AC), and the secondary side, which can be connected to the user.
Such systems may operate with voltage control (CV—control voltage mode) or current control (CC—control current mode), for example, depending on the load applied.
When operating with a regulated output voltage (CV mode), feedback can be obtained using a network on the secondary side and a photodiode (optocoupler) to transfer the information to the primary side.
Current control (CC mode) may be achieved using a circuit that, on the primary side, is able to intercept the demagnetization time of the transformer included in the power supply and produce, following processing, a primary current peak to obtain a desired current (target current).
In the application context set out above, a class of power supplies known as quick chargers and USB power delivery, used in conjunction with USB sockets, play an important role. Both types of power supply may include a converter in which the current value in CC mode may be configured as a function of the output voltage (for example, in quick chargers) or simply modified to determine a power target to transfer to the load (for example, in USB power delivery circuits).
As mentioned previously, in the field of switching power supplies with galvanic isolation between output voltage and input voltage, the voltage control feedback may be achieved using an optocoupler that, in addition to closing the control loop, also enables galvanic isolation to be implemented. Current control may be implemented using a circuit on the primary side including a demagnetization detection unit (demag detector) able to generate a digital signal that follows the demagnetization phase of the transformer, which can be obtained, for example, by monitoring a division of the voltage on an auxiliary winding of the (secondary) of the transformer.
U.S. Pat. No. 5,729,443 A provides an example of extensive research and innovation activity undertaken in the sector.
Despite such extensive activity, there remains a need for improved solutions.
This may be the case, for example, for applications (for example quick charger—QC and/or USB Power Delivery—USB PD) in which the point set for continuous current regulation may change depending on the desired voltage, for which, as illustrated below, some parameters may vary according to the operating point (for example input voltage VIN and output voltage VOUT), situations in which the output current is greater than desired being possible.
One or more embodiments address this requirement.
One or more embodiments may be applied to the control of switching power supplies that can for example be used in battery chargers for mobile communication devices.
One or more embodiments may concern a corresponding power supply, a corresponding apparatus (for example a battery charger for mobile communication devices including such a power supply) and a corresponding method.
One or more embodiments may address different drawbacks and limitations in the known solutions, including in relation to the function, found for example in battery chargers, referred to as current foldback, i.e., a short-circuit protection that makes it possible to reduce the mean output current, for example to approximately one tenth of the maximum current, when the output voltage is below a given voltage level.
One or more embodiments may extend the functional scope of CC mode control, for example enable the achievement of a wide range of possible variations in current gain (GI).
One or more embodiments are described below by way of non-limiting example with reference to the attached figures, in which:
The description below illustrates the various specific details to provide an in-depth understanding of several example embodiments according to the description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials and the like. In other cases, known structures, materials or operations are not shown or described in detail so as not to obscure the different aspects of the embodiments. References to “an embodiment” in this description indicate that a particular configuration, structure or feature described in relation to the embodiment is included in at least one embodiment. Consequently, phrases such as “in one embodiment” that may appear at different points of the present description do not necessarily refer exactly to the same embodiment. Furthermore, specific formations, structures or features may be combined in any appropriate manner in one or more embodiments.
The references used here are provided merely for convenience and as such do not define the scope of protection or the scope of the embodiments.
By way of introduction to the detailed description of examples of one or more embodiments, it would be useful to summarize some of the observations made in relation to prior references.
As described, for example, in U.S. Pat. No. 5,729,443 A, when a switching power supply system such as the ones discussed herein reach a steady-state condition, the mean output current is a function of the transformation ratio between the primary side and secondary side of the transformer, of various parameters inside the device and of an amperometric design parameter Rsens, which enables the output current to be set to the desired value.
As previously mentioned, the foldback function may be particularly important in certain potential applications. One method for implementing the current foldback function, or more generally a function for varying the output current as a function of the output voltage (for example in a quick charger) or simply a function for varying the output current to modify the output power (for example in USB power delivery devices—USB PD) may be a method including different values of one of the aforementioned parameters (for example the current gain parameter GI) that can be set according to the desired output current Iout, or defining different values GIi for the parameter, each being able to produce a corresponding desired output current value IOUTi.
It has been observed that, when operating such solutions a voltage VIREF may develop on a reference node IREF (identifying a desired output current value), which may be dependent on: the demagnetization time TDEMAG (it is noted that the value TDEMAG identifies the demagnetization time of the transformer of the power supply and is the same as the time during which current is flowing on the secondary side), and the switching frequency fs=1/TS, where TS is the switching period.
It can be seen that, in CC mode, the values of TDEMAG and of TS depend on the working point of the system, i.e. on the output voltage VOUT and the input voltage VIN, and the voltage VIREF also depends on the working point. In particular, it can be seen that VIREF is a function of the output current lout (settable by design) and of the ratio TS/TDEMAG (function of the working point).
When the system is working in CC mode, the value TDEMAG is linked to the magnetisation inductance of the transformer Lm and to the direct voltage drop Vf of the recirculation diode of the winding of the transformer.
Where TON is the time during which the transformer is magnetised (for example, by a power MOS transistor made conductive for example by a gate driver drive circuit), the value TS (total switching period) is given by the sum of TDEMAG, TON and a dead time TDEAD during which the system is neither magnetising nor demagnetising the transformer.
In zero voltage switching (ZVS) solutions, the power MOS transistor can be powered up when the drain-source voltage of same reaches a minimum value, and the time Tv taken between the end of the magnetisation and power up of the power MOS transistor (which would ideally occur exactly when VDS is at its lowest point) depends on Lp=Lm+Lleak (where Lleak is the leakage inductance of the transformer, while Lm is the magnetization inductance) and by the drain capacitance Cd of the power MOS transistor. At the moment the power transistor is powered down and current begins to flow on the secondary of the transformer, there is again a certain time TDEAD1 that, when added to the value Tv, identifies the value TDEAD.
The considerations set out above (and the ratios derived from same) ensure that for a given application and for a given output current value Iout, the values of VIREF and, therefore, also the time TON, are dependent on the working point (output voltage VOUT and input voltage VIN).
This situation may be unsatisfactory in some applications such as, for example, where there is a need to take account of possible variations in VIN in a field that may range, for example, from 80 V to 380 V.
When making AC/DC converters such as those discussed, switched-mode power supply (SMPS) controllers may be used, using a mask on the reset signal of the power MOS transistor (known as leading edge blanking, or LEB).
When the power MOS transistor is powered up and for a set period of time TLEB, the reset of the PWM is inhibited, such that the voltage spike that occurs on the source just after power-up of the power MOS transistor caused by the discharge current of the capacitor Cd is not able to generate a reset pulse for the power MOS transistor.
It is possible to define a delay-to-output value (TD) when the power MOS transistor is powered down that is equal to the sum of the intrinsic delay of the comparator of the generator of the PWM signal and the power-down delay of the power MOS transistor. Both TLEB and TD link the power-up time (“ON time”) of the power MOS transistor to a minimum value that is equal to TONMIN=TLEB+TD (typically a value of around 400-500 nanoseconds). This means that the system cannot set TON below the aforementioned TONMIN, which may, in some cases, represent an intrinsic limit of the system when regulating current.
When making a system in which the current value IOUT can be configured with values that can differ by a factor of 10 (in the case of implementation of the foldback function), current regulation may hit the aforementioned limit TONMIN.
With reference (by way of example) to quantitative values, assuming a desired system in which the output current IOUT can be set to two values IOUT1=1.48 A and IOUT2=2.22 A, it can be seen that, in order to achieve such current values, the parameter GI mentioned above needs to be configurable according to the values GI1=0.166 and GI2=0.25.
It can be seen that, where GI is set to 0.25, the time TON is always higher than TONMIN, with the system able (for all values of VOUT) to correctly regulate the current IOUT=2.22 A set.
Where GI is set to the value 0.166, conversely, the time TON is higher than TONMIN for values of VOUT greater than 0.8 V, while the time TON is less than TONMIN for values of VOUT below 0.8 V.
This means that for voltages of VOUT greater than 0.8 V, the system can correctly regulate the set current value to 1.48 A, while for voltages of VOUT lower than 0.8 V, the system is forced to work with TON=TONMIN with the output current higher than the desired target value.
For example, calculating the output current where TON=TONMIN, it can be seen that for values of VOUT<0.8 V, the current IOUT increases as the value of voltage VOUT drops, while for VOUT>0.8 V the current remains constant at the target value. Where VIN is higher, for example 380 V, the voltage VOUT at which the system begins working at TONMIN is close to 2 V.
Consequently, systems in which the output current is configured by setting the parameter GI display working conditions in which the output current is higher than the desired current.
This constitutes a limitation for the application itself. For example, where the foldback function is to be implemented and GI is set at one tenth of the nominal value, the aforementioned problem may occur for all of the application conditions VIN and VOUT. In this case, it can be seen that the TON required for the current IOUT to be the target current is less than 100 ns.
The diagram in
It may, for example, be a power supply for a battery charger for mobile communication devices.
Notwithstanding the further details given below, in particular in relation to the unit indicated using reference sign 200, the structure and the operating criteria of a power supply of this type are understood to be known in the most general terms, and as such there is no need to provide a detailed description here.
For the purposes of the present document, the power supply in
The transformer T can also be associated with an auxiliary winding Waux, on which a signal AUX can be detected and that can use another diode D′ to establish a voltage VDD on another capacitor Cvdd referred to ground.
The primary winding W1 of the transformer T (at the ends of which a circuit SC may be arranged to act as a “snubber”) may be acted upon by an electronic switch PS, such as a power transistor (for example a MOSFET transistor, such as a PMOS), the control terminal of which (gate, in the case of a field-effect transistor such as a MOSFET) is driven by a drive output GD of the circuit 10 discussed below.
An amperometric sensing resistor RS interposed between the transistor PS and ground is able to supply a (voltage) signal indicative of the intensity of the current flowing on the current path (source-drain in the case of a field-effect transistor such as a MOSFET) of the power transistor PS, and therefore at least approximately on the primary winding W1 of the transformer T, to a sensing input CS of the circuit 10.
The reference sign VD indicates a voltage divider (for example resistive) to which the signal AUX of the auxiliary winding Vaux can be applied, there being a signal ZCD (virtual zero-crossing) at the division point of same that can be applied to a counterpart input of the circuit 10 such as to perform (according to known criteria) a demagnetization detection function (demag detector) of the transformer T, such as to generate a digital signal X that follows the demagnetization phase of the transformer.
It can be seen that the different components discussed above and shown in
In one or more embodiments, the circuit 10 may include a PWM generator unit 100 (i.e. a rectangular-wave switched signal generator) that is designed to generate a signal QG (with a duty cycle that is selectively variable according to the criteria regulating generation of a PWM signal) with a period TS that can be used to drive, for example via a driver 102, the output GD and, therefore, the control terminal of the power switch (power MOS) PS.
In one or more embodiments, the modulator PWM can operate as a function of different signals.
These include a first signal that can be represented by the output of a logic AND gate 104 that receives the signal LEB on one of the inputs of same (for example outputted from the PWM generator unit 100).
As discussed previously, the signal LEB can implement a mask on the reset signal of the power transistor PS, with the reset signal applied to the other input of the logic AND gate 104 from an OR gate 106 that in turn receives as input the output from a first comparator 108a and the output of a second comparator 108b, for example resetting the PWM when the reset signal is high, this reset resulting from an OR of the two output signals of the comparators 108a and 108b.
The first comparator 108a is able to compare the signal on the input CS (amperometric signal of the resistor RS) with the output VCCREF of a CC mode block 110a that “senses” the signal on the input ZCD.
The second comparator 108b is able to compare the signal on the input CS (amperometric signal of the resistor RS) with the output VCVREF of a CV mode block 110b that also “senses” the signal on the input ZCD.
The same signal ZCD is also taken to a unit 112 that transforms same into the digital signal X, i.e. the signal, discussed previously in relation to the demag detector function, that follows the demagnetization phase of the transformer T and that is powered towards two logic AND gates 114a, 114b acting on the PWM generator unit 100.
The two logic gates n4a, 114b each receive on one input (via a logic inverter 116) a signal COUNTED discussed below, with the logic gate n4a receiving the signal X on the other input of same from the unit 112, while the logic gate 114b receives a restart signal on the other input of same from a starter unit 118.
Reference sign 120 indicates another logic AND gate that receives the signal COUNTED on one input and a signal START_PULSE on the other input.
In one or more embodiments, the signals COUNTED and START_PULSE can be generated by a unit 200 for regulating or adjusting the switching period TS in CC mode operation.
In one or more embodiments, the block 200 can receive the aforementioned signals X, LEB, QG, VCCREF, VCVREF as input.
In one or more embodiments, the unit 200 can be organized as shown by way of example in
Unit 201: detection time TONMIN as a function of the signals LEB and QG under the control of a CC-mode enabling signal CC_MODE_ENABLED, with generation of a signal TONMIN_ACTIVE.
Unit 202: detection upper value of time TONMIN as a function of the signals LEB and QG under the control of the CC-mode enabling signal CC_MODE_ENABLED, with generation of a signal TONMIN_HIGH.
Unit 203: up/down counter also enabled by the signal CC_MODE_ENABLED, which receives the signals TONMIN_ACTIVE (unit 201) and TONMIN_HIGH (unit 202) and outputs the signal COUNTED and a signal number_shift.
Unit 204: another counter that receives the signal X as input, receiving a start-count signal START_COUNT from the counter 203 and sending an end-count signal END_COUNT to the counter 203.
Unit 205: also enabled by the signal CC_MODE_ENABLED, receives as input the signal X as well as the signal number_shift from the block 203 generating the signal START_PULSE, under the control of the signal CC_MODE_ENABLED.
In one or more embodiments, the (macro) unit 200 can perform the function of appropriately adapting the switching period TS acting on the time TDEAD, during operation in CC mode identified by the enabling signal CC_MODE_ENABLED that can be obtained at the output of a comparator 210 receiving the signals VCCREF and VCVREF as input.
In one or more embodiments, the comparator 210 may perform the function of identifying the current-control (CC) operating mode of the system (i.e. of the power supply).
For example, when the system is working in CC mode, the voltage level VCCREF is lower than the level VCVREF. In the opposite case, the system operates in voltage-control (CV) mode. Consequently, the signal CC_MODE_ENABLED (brought for example to a “high” logical level) can indicate CC mode operation, this signal enabling the different units described above.
In one or more embodiments, the unit 201 can perform the function of identifying the working condition in which TON of the transistor PS is precisely TONMIN. The inputs of the unit 201 are the signals QG and LEB, both coming from the PWM generator unit 100, where QG is the signal that drives the driver 102 and is therefore indicative of the on state of the transistor PS.
As seen previously, LEB is a masking time that is used to ensure masking of the reset of the transistor PS by part of the PWM generator unit 100 following the voltage spike occurring on the pin CS as a result of the discharge of Cd (drain capacitance) of the transistor PS occurring after power-up of the transistor PS.
In one or more embodiments, the signal TONMIN_ACTIVE (for example at a high logic level) outputted from the unit 201 can precisely indicate the condition in which the TON is precisely TONMIN.
In one or more embodiments, the unit 202 can perform the function of identifying the working condition in which TON of the transistor PS is higher than a given predetermined level TON HIGH greater than TONMIN. QG and LEB are inputs to the unit 202. The output signal TONMIN_HIGH (for example at a high logic level) can precisely indicate the condition in which the TON is higher than a predetermined value TON_HIGH>TONMIN.
In one or more embodiments, the unit 203 may perform the function of incrementing and decrementing a counter on the basis of the input signals TONMIN_ACTIVE, TONMIN_HIGH and END_COUNT, outputting a number signal number_shift that corresponds to a number to be processed by the unit 205.
A signal called COUNTED, which is for example at a high logic level when the signal number_shift is not zero, may also be outputted. This signal inhibits both the signal X (ZCD unit) entering the PWM generator unit 100 (which forces the transistor PS to be powered up, for example implementing the ZVS function) and the restart signal coming from the unit 118, forcing the unit 205 to power up again via the signal START_PULSE.
In one or more embodiments, the unit 205 may perform the function of generating a pulse that forces the transistor PS to power up (signal START_PULSE) after a given time (equal for example to number_shifter*Tfix) from the falling edge of the signal X, with the objective of increasing the switching period TS of the system, necessarily increasing the time TDEAD.
Possible operating modes of one or more embodiments are described below by way of example.
For example, when the system switches from CV mode to CC mode, the voltage level of the signal VCCREF goes lower than the voltage level of VCVREF, the comparator 210 switches and the signal CC_MODE_ENABLE goes for example to a high logic level, enabling the entire unit 200.
This makes it easier for the regulation mechanism for TS to occur (only) when the system is operating in CC mode.
Assuming, in a possible example, that the working point of the system is such that TON is greater than TONMIN. Under such conditions the signal TONMIN_ACTIVE is at the low logic level and no action is carried out by the system, which can then continue to operate normally, for example with TS equal to the typical value defined by the application. For example:
T
S
=T
ON
+T
DEMAG
+T
DEADmin
where TDEADmin is the minimum value of the time TDEAD defined previously.
It is now assumed that the working point moves towards lower VOUT values, enabling TON to reach the value TONMIN for VOUTvalues of less than 2 V, for example.
As discussed previously, in the absence of any mechanism for adjusting the period TS, the system would supply an output current that is higher than the target current.
In one or more embodiments, the condition for TON reaching TONMIN may be identified by the unit 201 that configures the signal TONMIN_ACTIVE, for example to the high logic level.
With TONMIN_ACTIVE high, the unit 203 can in turn switch the signal START_COUNT to the high logic level and, consequently, the unit 204 can start counting events for the signal X and, after a given number of events have been counted for the signal X (number indicated as “NeventX” for the sake of brevity), send a pulse to the unit 203 using the signal END_COUNT.
If, when counting the events for X, TON again becomes greater than TONMIN, the signal TONMIN_ACTIVE again returns to the low logic level and consequently the signal START_COUNT also goes to the low logic level and the unit 204 stops counting and resets the counter, the counter restarting from zero when START_COUNT returns to the high logic level.
Such a counting mechanism for the signal X before TS is modified facilitates adjustment of TS (only) after the transient on TON has passed. This transient can be attributed to the variation of the working point (for example variation of VOUT) or to the change made to TDEAD by the mechanism for adjusting TS.
Assuming now that, while TONMIN_ACTIVE is for example high, the unit 204 finishes counting a number of events for X equal to “NeventX,” a pulse, via the signal END_COUNT, can be sent to the unit 203, which increments the number counter number_shift by one from 0 to 1 and, simultaneously, since number_shift is not 0, the signal COUNTED can be moved to the high logic level.
This prevents the signal X or the signal restart from powering up the transistor PS and enables the transistor PS to be powered up again (only) by the signal START_PULSE. The pulse START_PULSE is generated by the unit 205, which generates the pulse (precisely) after a time delay equal to number_shift*Tfix (where Tfix has a predetermined value for example if Tfix=1 microsecond and number_shift=1 number_shift*Tfix=1 microsecond) from the falling edge of the signal X.
Consequently, the period TS is higher than the quantity number_shift*Tfix and, as a result of the variation of TS caused by the lengthening of TDEAD, the current IOUT drops.
If the new current level is lower than the target value, the CC mode can act (in practice increasing the “virtual” reference VIREF discussed in the introduction) and consequently TON will also be greater than TONMIN adjusting the current IOUT to the target value.
By bringing TON to a value greater than TONMIN, the signal TONMIN_ACTIVE can go, for example, to a low level and the system can freeze that condition with TDEAD at 1 microsecond. If the current IOUT, after TS has been increased, is still higher than the target current, TON is still equal to TONMIN, the signal TONMIN_ACTIVE remains, for example, high and the signal START_COUNT also remains high, the unit 204 begins a new count of the X events and, having counted “NeventX,” sends another END_COUNT pulse to the unit 203, which increments the number counter number_shift by one from 1 to 2.
In this case, the pulse START_PULSE generated by the unit 205 is sent after a time delay equal to 2*Tfix=2 microseconds from the falling edge of the signal X. This causes a further drop in the current level IOUT. The process freezes in this state if TON, following the increase in TS, becomes higher than TONMIN, and TDEAD continues to increase if TON remains equal to TONMIN.
Again by way of non-limiting example, it can be assumed that the working point changes, assuming that the output voltage VOUT moves from 0.15 V to 4.25 V. Assuming that from the aforementioned condition in which TDEAD is reset to the value 4*nTfix, i.e. 4 microseconds.
Following the change in the working point, to facilitate achievement of the target value by the current IOUT supplied, the system can increase the voltage of the reference VIREF and consequently also TON. Without a reduction mechanism for TDEAD, the reference VIREF would quickly reach maximum value, with the current IOUTsupplied under such conditions being lower than the target value.
In one or more embodiments, in order to obviate this drawback, the unit 202 can identify the condition in which TON is greater than a predetermined value indicated using TONHIGH (which is set to a value greater than TONMIN and less than an upper limit TON@Vlow that is possible if VIREF=Vlow, for example where TONHIGH is set to approximately 615 nanoseconds).
If TON is greater than TONHIGH, the signal TONMIN_HIGH is set, for example, to a high logic level, and the unit 204 begins a new count of X events, and once X reaches “NeventX,” sends an END_COUNT pulse to the unit 203, which in this specific case in which TONMIN_HIGH is high, decrements the number counter number_shift by one from 4 to 3.
The process can continue until TON is greater than TONHIGH stopping either when TON is less than TONHIGH or when number_shifter reaches 0.
In this latter case, TDEAD is again equal to TDEADmin, the signal COUNTED again returns to the low logic level and powering up of the transistor PS is again determined by the signal X (via the unit 112), without any additional delay, everything in principle occurring before the mechanism is activated by achievement of the condition TON=TONMIN.
Experiments carried out with two changes in the output voltage Vout, the first from 1.5 V to 0.15 V (with the system adapting by reducing the frequency of the system) and the second from 0.15 V to 4.2 V (with the system increasing the frequency returning to the starting condition) have confirmed the possibility of achieving entirely satisfactory results using one or more embodiments.
One or more embodiments may result in a system that, having identified the condition TONMIN, can increase the switching period TS for example increasing TDEAD (using a discrete quantity such as 1 microsecond, 2 microseconds, etc.) until the system finds another working point in which TON is greater than TONMIN.
When the working point changes, for example when the output voltage increases, TON increases. In one or more embodiments, if a given value is exceeded (for example TONHIGH), the system starts to reduce TDEAD, this process being liable to stop either when TON is less than TONHIGH or when TDEAD reaches the minimum value restoring the starting condition.
The graphs in
The graph in
When working in such conditions, in one or more embodiments TDEAD may be increased until TON is greater than TONMIN. Under these new conditions, the current IOUT is correctly regulated.
In the example shown in
Having positioned TONHIGH (horizontal line in
One or more embodiments may work such that, within the voltage range VOUT containing the limit of TONMIN, there being no option of reducing TON, the switching frequency is reduced (increasing TS by acting on TDEAD) thereby forcing the system to work with TONMIN<TON <TONHIGH.
In short, one or more embodiments can detect the condition of TONMIN and correspondingly increase the switching period TS by increasing TDEAD appropriately (the time elapsed between the end of the demagnetization interval and actual powering up of the power switch PS), for example using discrete values of 1 microsecond, 2 microseconds and so on, until the system reaches a new working point in which TON is greater than TONMIN.
Following a change in the operating conditions, for example following an increase of the output voltage, TON also increases and, if same exceeds a predetermined value TONHIGH, the system reduces TDEAD, and the process ends as a result of the fact that (i) TON is less than TONHIGH or (ii) TDEAD reaches the lowest value, restoring the initial condition.
It can also be seen that the use of one or more embodiment can be compared by detecting, during operation in CC mode, quantities that can be measured from the outside, such as frequency 1/TS, on time TON and dead time TDEAD.
One or more embodiments may therefore concern a circuit (for example 10) including: a driving terminal (for example GD) couplable to a control terminal of a power transistor (for example PS), an amperometric input (for example CS) for detecting an amperometric signal, the amperometric signal being indicative of the intensity of the current flowing through the power transistor, a switched signal generator (for example 100) coupled (for example via the driver 102) to the driving terminal, the switched signal having a period, Ts, being the sum of an active time (activation of the transistor PS), TON, and a dead time, TDEAD, a control network (see for example the elements 104 to 118) coupled to the amperometric input and to the switched signal generator, the control network being configured to control the active time, TON, of the switched signal as a function of the signal at the amperometric input, with the active time, TON, able to reach a lower limit, TONMIN, and a regulating network (for example 200, 120) of the switched signal generator, the regulating network comprising: a detection unit (for example 201) of the active time, TON, reaching the lower limit, TONMIN, and a variation unit (for example the counter 203) for the dead time TDEAD being activatable (for example via TONMIN_ACTIVE) to increment the dead time, TDEAD, as a result of the active time, TON reaching the lower limit, TONMIN.
The fact of referring to the period TS as including the sum of an active time (activation of the transistor PS), TON, and a dead time, TDEAD, disregarding the presence of the demagnetization time TDEMAG, shows that, following detection (for example in 201) on TON (in order to check that TONMIN has been reached), and following regulation on the dead time TDEAD (in order to increase the period TS and reduce the frequency 1/Ts), one or more embodiments can be “transparent” with regard to the demagnetization time TDEMAG, which in one or more embodiments may even be undetected.
One or more embodiments may include: an additional amperometric input (for example ZCD) for detecting a demagnetization signal, the demagnetization signal being indicative (for example X) of the demagnetization time, TDEMAG, of a transformer (for example T) driven by the power transistor (PS), the switched signal generator coupled (for example 112, 114a) to the additional amperometric input, with the period of the switched signal, Ts, being the sum of the active time, TON, the demagnetization time, TDEMAG, and the dead time, TDEAD.
In one or more embodiments, the variation unit for the dead time, TDEAD, is activatable in discrete steps (for example 1 microsecond, 2 microseconds) varying the dead time, TDEAD.
In one or more embodiments, the switched signal generator may be disabled (for example LEB, 104) from resetting during a masking interval after the application of a turn-on pulse for the power transistor at the driving terminal (GD), the lower limit, TONMIN, being a function of the masking interval.
In one or more embodiments, the regulating network may include: a detection unit (for example 202) of the active time, TON, reaching an upper limit, TONHIGH, and the variation unit of the dead time, TDEAD, activatable (TONMIN_HIGH) to decrement the dead time, TDEAD, as a result of the active time, TON reaching the upper limit, TONHIGH.
In one or more embodiments, the regulating network may include a variation unit (for example the counter 203) of the dead time, TDEAD, activatable (for example via TONMIN_ACTIVE, TONMIN_HIGH) alternatively to increment and to decrement the dead time, TDEAD, as a result of the active time, TON, reaching the lower limit, TONMIN, or the upper limit, TONHIGH, respectively.
In one or more embodiments, the regulating network may be configured (for example via the signal TONMIN_ACTIVE) to maintain or change the dead time, TDEAD, to a respective lower limit, TDEADmin, in the presence of an active time, TON, greater than the lower limit, TONMIN.
In one or more embodiments, the regulating network may include an enabling module (210) sensitive (for example VCCREF, VCVREF) to a current control state of the power transistor, with the regulating network being enabled (only) during the current control state.
In one or more embodiments, a power supply may include: a transformer with a primary winding (for example W1) and a secondary winding (for example W2) couplable to a powered load, a power transistor (for example PS) driving the primary winding of the transformer, the power transistor (PS) having a control terminal (for example gate), an amperometric sensor (for example RS) sensitive to the current flowing in the power transistor (for example on the current path, for example source-drain in the case of a FET), and a circuit according to one or more embodiments having the driving terminal coupled to the control terminal of the power transistor, and the amperometric control input being coupled to the amperometric sensor.
In one or more embodiments: the transformer may include an auxiliary winding (for example Waux) to provide (for example via a divider VD) a demagnetization signal (ZCD) indicative of the demagnetization time, TDEMAG, of the transformer driven by the power transistor, the circuit may include an additional amperometric input (ZCD) that receives the demagnetization signal, the switched signal generator may be coupled to the additional amperometric input (ZCD), with the period of the switched signal, Ts , being the sum of the active time, TON, the demagnetization time, TDEMAG, and the dead time, TDEAD.
An apparatus according to one or more embodiments, optionally a battery charger, may include a power supply according to one or more embodiments.
A method for using a circuit according to one or more embodiments may include: coupling a control terminal of a power transistor to the driving terminal, detecting an amperometric signal at the amperometric input that is indicative of the intensity of the current flowing through the power transistor, applying the switched signal (100) to the driving terminal with a period, Ts, that is the sum of an active time, TON, and a dead time, TDEAD, controlling, via the control network, the active time, TON, of the switched signal as a function of the signal at the amperometric input, with the active time, TON, able to reach a lower limit, TONMIN, and detecting the active time, TON, reaching the lower limit, TONMIN, and incrementing the dead time, TDEAD, as a result of the active time, TON reaching the lower limit, TONMIN.
As discussed above,
As shown in
In CC MODE, when TONMIN_ACTIVE goes high, the system goes to INCREASE COUNTER state to increment by one the number_shifter, which increases the period TS of the system by an amount number_shifter*Tfix, where Tfix is a fixed time. At the same time, a counter starts to count a fixed number of TS periods (1st ENABLE COUNTER X state), while a transient time due to the variation done on TS is elapsed.
At the end of the count, END_COUNT signal goes high, and, if TONMIN ACTIVE is still high (TONMIN ACTIVE and END COUNT is high), the system goes again to the INCREASE COUNTER state, and the number_shifter is incremented by another unit. The system, then, goes again to the 1st ENABLE COUNTER X state, repeating the sequence.
When TONMIN_ACTIVE goes low, the system goes to the FREEZE state. In the FREEZE state, the number_shifter is held to the last one value and the TS period of the system is frozen to the value (TS+number_shifter*Tfix). This is maintained until the signals TONMIN_ACTIVE or TONMIN_HIGH go high. If the TONMIN_ACTIVE goes high, the system goes to the INCREASE COUNTER, repeating the sequence.
If the TONMIN_HIGH goes high, the system goes to the DECREASE COUNTER state, in which the number_shifter is decremented by one from its last value (in this way the TS period is decreased by an amount of Tfix). At the same time, a counter starts to count a fixed number of TS periods (2nd ENABLE COUNTER X state), while a transient time due to the variation done on TS is elapsed. At the end of the count, END_COUNT signal goes high, and if TONMIN_ACTIVE is still high (TONMIN_ACTIVE and END COUNT is high) the system goes again to the DECREASE COUNTER state and the number_shifter is decremented by another unit. The system, then, goes again to the 2nd ENABLE COUNTER X state, repeating the sequence. When TONMIN_ACTIVE goes low, the system goes to the FREEZE state, repeating the sequence.
As shown in
Notwithstanding the basic principles, the implementation details and embodiments may vary, even significantly, from those given here purely by way of non-limiting example, without thereby moving outside the scope of protection.
This scope of protection is defined by the attached claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102017000022236 | Feb 2017 | IT | national |
