Claims
- 1. A digital control within a feedback control loop of a sampling data detection channel for controlling a predetermined operating parameter of the channel in which an analog to digital converter provides digital samples of information in the channel at a predetermined channel clock rate, the digital control comprising:
- a parameter error extraction circuit clocked at the predetermined channel rate and connected to receive digital samples from the analog to digital converter, for extracting parameter error values from the digital samples,
- an averaging circuit for averaging the extracted parameter error values over an integral submultiple of the predetermined channel rate, and
- a parameter error processing circuit connected to the parameter error extraction circuit and clocked at the integral submultiple of the predetermined channel rate for generating and putting out digital control values within the feedback control loop for controlling the predetermined operating parameter, the parameter error processing circuit includes at least one multiplier for multiplying the averaged extracted parameter values by a loop constant, to produce a product, and an integrator for integrating the product.
- 2. The digital control within a feedback control loop set forth in claim 1 wherein the feedback control loop is an nth order control loop, wherein n comprises an interger greater than zero, and wherein the parameter error processing circuit includes at least n multipliers for multiplying the averaged extracted parameter values by n loop constants, to produce n normalized products, and combining means for combining the n normalized products.
- 3. The digital control within a feedback control loop set forth in claim 1 wherein the feedback control loop controls clock frequency and phase of the analog to digital converter.
- 4. The digital control within a feedback control loop set forth in claim 1 wherein the sampling data detection channel includes a variable gain amplifier and wherein the feedback control loop controls gain of the variable gain amplifier.
- 5. The digital control within a feedback control loop set forth in claim 1 wherein the sampling data detection channel includes a DC offset summing junction and wherein the feedback control loop controls the DC offset summing junction.
- 6. The digital control within a feedback control loop set forth in claim 1 wherein the digital control comprises one of a plurality of digital controls within timing, gain and DC offset feedback control loops of the sampling data detection channel included in a magnetic recording device.
- 7. A method for reducing power consumption within a feedback control loop of a sampling data detection channel including generating a digital control for controlling a predetermined operating parameter of the channel in which an analog to digital converter provides digital samples of information in the channel at a predetermined channel clock rate, the method comprising the steps of:
- extracting parameter error values at the predetermined channel rate from the digital samples within a parameter error extraction circuit connected to receive digital samples from the analog to digital converter,
- averaging the extracted parameter error values within an averaging circuit over an integral submultiple of the predetermined channel rate,
- generating and putting out digital control values at the integral submultiple of the predetermined channel rate from a parameter error processing circuit for controlling the predetermined operating parameter within the feedback control loop and
- multiplying the averaged extracted parameter values by a loop constant to produce a product, and integrating the product.
- 8. The control method set forth in claim 7 wherein the feedback control loop is an nth order control loop, wherein n comprises an integer greater than zero, and the step of generating and putting out digital control values at the integral submultiple of the predetermined channel rate comprises the steps of multiplying the averaged extracted parameter values by n loop constants within at least n multipliers for producing n normalized products, and combining the n normalized products within combining means to generate the digital control values.
- 9. The control method set forth in claim 7 for generating a timing control (VCO.sub.k) for controlling sampling frequency and phase of the analog to digital converter.
- 10. The control method set forth in claim 9 wherein the timing control (VCO.sub.k) is generated in accordance with:
- VCO.sub.k+1 =T.sub.k +.alpha./2.DELTA..sub..rho.k,T.sub.k+1 =T.sub.k +.beta./2.DELTA..sub..rho.k,
- where n represents a current digital sample, where x.sub.n represents a current sample estimate, where k=2n, where .DELTA..rho.n=((x.sub.n-2 -x.sub.n)xn-1+x.sub.n-1 (x.sub.n -x.sub.n-2)) (wherein .alpha. and .beta. represent timing control loop scaling functions), and where .DELTA..rho..sub.n represents an average timing phase error.
- 11. The control method set forth in claim 9, wherein the timing control (VCO.sub.k) is generated in accordance with:
- VCO.sub.k+1 =T.sub.k +.alpha./2.DELTA..sub..rho.k,T.sub.k+1 =T.sub.k +.beta./2.DELTA..sub..rho.k,
- where n represents a current digital sample, where x.sub.n represents a current sample estimate, where k=2n, where .DELTA..rho.n=e.sub.n-1 (x.sub.n -x.sub.n-2)+e.sub.n-2 (x.sub.n-1 -x.sub.n-3)(wherein .alpha. and .beta. represent timing control loop scaling functions), and where .DELTA..rho..sub.n represents an average timing phase error.
- 12. The control method set forth in claim 7 wherein the sampling data detection channel includes a variable gain amplifier and wherein the control method generates a gain control (V.sub.g .DELTA..sub.k) for controlling gain of a variable gain amplifier within the channel.
- 13. The control method set forth in claim 12 wherein the gain control (Vgak) is generated during at least a gain acquisition mode in accordance with:
- Vga.sub.k+1 =Vga.sub.k +.gamma./2.DELTA..sub.gk,
- where .DELTA.g.sub.n =e.sub.n sgn(x.sub.n)+e.sub.n-1 sgn(x.sub.n-1)=average gain error, where n denotes a current digital sample, where x.sub.n represents a current sample estimate, where k=2n, en=xn-x.sub.n, and where ##EQU3##
- 14. The control method set forth in claim 7 wherein the sampling data detection channel includes a DC offset summing junction and wherein the control method generates a DC offset control (Offset.sub.k) for controlling the DC offset summing junction.
- 15. The control method set forth in claim 14 wherein the DC offset control (Offset.sub.k) is generated in accordance with: Offset.sub.k+1 =Offset.sub.k +.mu./2.DELTA.O.sub.k, where n denotes a current digital sample, where .mu. represents a DC offset control loop scaling factor, where .DELTA.O.sub.n =(x.sub.n +x.sub.n-2 +x.sub.n-1 +x.sub.n-3)=a current averaged DC offset error, and where k=2n.
- 16. The control method set forth in claim 14 wherein the DC offset control (Offsetk) is generated in accordance with:
- Offset.sub.k+1 =Offset.sub.k +.mu./2.DELTA.O.sub.n, where n denotes a current digital sample, where .mu. represents a DC offset control loop scaling factor, where .DELTA.O.sub.n =e.sub.n +e.sub.n-1 =x.sub.n -x.sub.n +x.sub.n-1 -x.sub.n-1 =a current averaged DC offset error, and where x.sub.n denotes a current sample estimate.
- 17. The control method set forth in claim 7 wherein the method is for controlling one of a plurality of digital controls within timing, gain and DC offset feedback control loops of the sampling data detection channel included in a magnetic recording device.
REFERENCE TO RELATED APPLICATION
This application is a divisional application of co-pending U.S. patent application Ser. No. 08/920,696, filed Aug. 29, 1997.
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Divisions (1)
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Number |
Date |
Country |
Parent |
920696 |
Aug 1997 |
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