Patent Application
20220416112
Substrates, usually GaAs, are the most expensive component in III-V solar cells. Spalling is a method by which device layers deposited onto substrates can be removed from the substrates, with the substrate preserved, enabling its recycle and reuse for future device growth. Spalling of the more common (100) substrate crystal orientation results in an undesirable “saw-toothed” surface with triangular facets; facets bound by the (110) or (211) planes, which have some of the weakest bond energies of any GaAs plane. Thus, there remains a need for improved spalling methods capable of producing substrate surfaces better suited for depositing semiconductor materials and for reliable recovery and reuse of the substrates.
An aspect of the present disclosure is a composition that includes a III-V planar substrate having a surface aligned with and parallel to a reference plane, where the surface includes a plurality of terraces, each terrace includes a first surface positioned between a first boundary and a second boundary, each boundary is substantially parallel to the other boundaries and positioned substantially parallel to the reference plane, and each terrace is separated from an adjacent terrace by a second surface positioned between the second boundary of the terrace and the first boundary of the adjacent terrace. Further, for each terrace, the first boundary is positioned approximately at a distance, H, relative to its second boundary in a first direction that is orthogonal to the reference plane and the first boundary is positioned approximately at a distance, W, relative to the second boundary in a second direction parallel to the reference plane and orthogonal to the first direction. Finally, each terrace is positioned in a plane that is positioned at an angle, a, relative to the reference plane, each terrace has a surface roughness of less than 1 nm, as measured by atomic force microscopy, 0 μm≤H≤3 μm, and 1 μm<W≤1 mm.
In some embodiments of the present disclosure, H may vary between ±20% relative to the average value of H. In some embodiments of the present disclosure, W may vary between ±15% relative to the average value of W. In some embodiments of the present disclosure, the III-V planar substrate may have a zinc blende crystal structure. In some embodiments of the present disclosure, the III-V planar substrate may be constructed of at least one of GaAs, GaP, InAs, AlAs, AlP, and/or InP. In some embodiments of the present disclosure, the III-V planar substrate may be constructed of a pseudo-binary combinations of at least one of GaAs, GaP, InAs, AlAs, AlP, and/or InP. In some embodiments of the present disclosure, α may be between less than 5°. In some embodiments of the present disclosure, α may be between less than 3°. In some embodiments of the present disclosure, each terrace may be positioned substantially in at least one of the (110) plane, the (111) plane, the (211) plane, and/or the (311) plane. In some embodiments of the present disclosure, 30 μm<W≤100 μm.
An aspect of the present disclosure is a method that includes depositing a device layer onto a planar substrate, depositing a stressor layer onto the device layer, and applying a directional force orthogonal to the reference plane and moving in a direction that is parallel to the reference plane. Further, the planar substrate is oriented to a plane is that is positioned at an angle, α, relative to a reference plane, and the applying results in the separating of the device layer from at least a portion of the planar substrate. In some embodiments of the present disclosure, the planar substrate may be substantially oriented in at least one of the (110) plane, the (111) plane, the (211) plane, and/or the (311) plane.
In some embodiments of the present disclosure, the planar substrate may be composed of a III-V alloy having a zinc blende crystal structure. In some embodiments of the present disclosure, the angle α may be less than 5°. In some embodiments of the present disclosure, the angle α may be less than 3°. In some embodiments of the present disclosure, the planar substrate may be substantially oriented in the (110) plane and the moving of the directional force may be substantially in the [1-10] direction. In some embodiments of the present disclosure, the separating of the device layer may occur at thickness, t, of less than 10 μm into the planar substrate relative to an interface created by the planar substrate and the device layer. In some embodiments of the present disclosure, the thickness into the planar substrate may be 3 μm≤t<10 μm. In some embodiments of the present disclosure, the applying may be achieved using a roller configured with an adhesive. In some embodiments of the present disclosure, the method may further include recovering and recycling the separated planar substrate for at least one additional depositing of a device layer.
Some embodiments are illustrated in referenced figures of the drawings. It is intended that the embodiments and figures disclosed herein are to be considered illustrative rather than limiting.
The embodiments described herein should not necessarily be construed as limited to addressing any of the particular problems or deficiencies discussed herein. References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, “some embodiments”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
As used herein the term “substantially” is used to indicate that exact values are not necessarily attainable. By way of example, one of ordinary skill in the art will understand that in some chemical reactions 100% conversion of a reactant is possible, yet unlikely. Most of a reactant may be converted to a product and conversion of the reactant may asymptotically approach 100% conversion. So, although from a practical perspective 100% of the reactant is converted, from a technical perspective, a small and sometimes difficult to define amount remains. For this example of a chemical reactant, that amount may be relatively easily defined by the detection limits of the instrument used to test for it. However, in many cases, this amount may not be easily defined, hence the use of the term “substantially”. In some embodiments of the present invention, the term “substantially” is defined as approaching a specific numeric value or target to within 20%, 15%, 10%, 5%, or within 1% of the value or target. In further embodiments of the present invention, the term “substantially” is defined as approaching a specific numeric value or target to within 1%, 0.9%, 0.8%, 0.7%, 0.6%, 0.5%, 0.4%, 0.3%, 0.2%, or 0.1% of the value or target.
As used herein, the term “about” is used to indicate that exact values are not necessarily attainable. Therefore, the term “about” is used to indicate this uncertainty limit. In some embodiments of the present invention, the term “about” is used to indicate an uncertainty limit of less than or equal to ±20%, ±15%, ±10%, ±5%, or ±1% of a specific numeric value or target. In some embodiments of the present invention, the term “about” is used to indicate an uncertainty limit of less than or equal to ±1%, ±0.9%, ±0.8%, ±0.7%, ±0.6%, ±0.5%, ±0.4%, ±0.3%, ±0.2%, or ±0.1% of a specific numeric value or target.
Among other things, the present disclosure relates to methods that provide a consistent and reliable separation of a device layer (or layers) that was deposited onto a substrate, resulting in a separate device layer and a separate substrate layer. The device layer may then be subsequently processed and at least a portion of the original substrate may then be recycled and reused to produce additional device layers. As shown herein, manufacturing costs for III-V devices may be reduced by depositing (e.g., by hydride vapor phase epitaxy (HVPE)) III-V device layers onto a (110)-oriented GaAs substrate layer, after which the device layers may be removed by controlled spalling on the (110) plane of the device in a specific direction (e.g. [1-10]), resulting in the separation of the device layers from the (110)-oriented GaAs substrate. Although, the focus of the present disclosure is the depositing of III-V device layers onto III-V substrate layers, device layers constructed of other crystalline semiconducting materials may also fall within the scope of the present disclosure. Similarly, although GaAs is described herein in detail, substrate layers constructed of other III-V alloys may also fall within the scope of the present disclosure.
As described herein, spalling is a method by which III-V device layers can be exfoliated (i.e., separated, removed) from the parent substrate, enabling reuse of the substrate with potentially minimal surface re-preparation. This provides improved economics over state-of-the-art substrate recovery techniques such as epitaxial liftoff (ELO). Spalling of the most common GaAs substrate orientation, (100), results in the formation of surface facets, defined as large regular features with a low index crystallographic orientation, i.e. (110) or (211), having peak-to-valley characteristic length/height dimensions between 10 μm and 15 μm, which require polishing or epitaxial smoothing before devices can be re-grown on the substrate, thereby limiting the viability of this technology. On the other hand, as shown herein, spalling (i.e., separating) of device layers from preferentially oriented substrates (e.g., 110-oriented substrates) can successfully recover the substrates having surfaces suitable for the regrown of additional device layers and requiring no or minimal surface preparation before the depositing of the new device layers. Therefore, the methods described herein relate to the spalling (i.e., removing) of III-V device layers from substrates having an (110)-orientation, followed by the growth and regrowth of new device layers onto the recovered and recycled (110)-oriented substrates. In some embodiments of the present disclosure, device layers may be deposited by dynamic hydride vapor phase epitaxy (D-HVPE), a growth technology with the potential for, among other things, manufacturing cost savings.
In some embodiments of the present disclosure, the methods and resultant compositions and devices may apply to any III-V alloy having a zinc blende crystal structure. Examples of III-V alloys having a zinc blende crystal structure include GaAs, GaP, InAs, AlAs, AlP, InP, and pseudo-binary combinations of these binary alloys.
As described herein, a device 100 may be constructed of a III-V alloy. In some embodiments of the present disclosure, a device 100 may be constructed of a III-V alloy having a zinc blende crystal structure. Examples of III-V alloys having a zinc blende crystal structure include GaAs, GaP, InAs, AlAs, AlP, InP, and pseudo-binary combinations of these binary alloys. In some embodiments of the present disclosure, the first surface 134 of a terrace 130 of a device 100 may be positioned at an offcut angle, α, relative to the horizontal reference plane, of less than 5°, less than 4°, less than 3°, less than 2°, or less than 1°. In some embodiments of the present disclosure, the first surface 134 of a terrace 130 may be positioned in the (110) plane or other low index planes such as the (111), (211), and/or (311) planes. In some embodiments of the present disclosure, the distance between a pair of boundaries (120 and 122) in the A-axis directed, W, may be between 1 μm and 1 mm. In some embodiments of the present disclosure, the distance between a first boundary 120 and the second boundary 122 in the B-axis direction, H, may be between greater than 0 μm and 3 μm.
As shown herein, GaAs solar cells were grown by dynamic-HYPE (D-HPVE) on (110)-oriented GaAs substrates, which demonstrated equivalent performance and material quality relative to D-HVPE grown GaAs solar cells grown on (100)-oriented GaAs substrates. Complementing this success, was the successful development and use of a method capable of providing the repeatable wafer-scale spalling of GaAs device layers from their underlying (110)-oriented GaAs substrate layer. The spalled surfaces of the recovered GaAs substrate layers were free of the facets typically found after spalling in recovered (100)-oriented substrates surfaces and free of surface features having greater than 3 μm in peak-to-valley height, which can otherwise degrade the efficiency of subsequent III-V device layers grown on the recovered substrate layer. A sub-μm step-terrace morphology, as described above and illustrated in
Further, an understanding was developed of the factors that determine the resulting step-terrace morphology, enabling ample opportunity for optimization of morphologies suitable for device growth, as well as minimizing the amount of GaAs wasted in post-spalling treatment steps to smooth the spalled surfaces. In addition, as described herein, a solar cell device was successfully grown on a previously spalled (110)-oriented GaAs substrate surface. The resultant devices exhibited a relative efficiency difference of only about 8% relative to a control solar cell grown on a new unspalled (110)-oriented GaAs substrate surface. These results highlight the promise of (110)-oriented devices coupled with substrate reuse by spalling as a pathway for low-cost III-V photovoltaics.
Device efficiency is the most direct way to evaluate whether the quality of material grown on HYPE-ready and as-spalled surfaces can sustain high quality devices. As shown herein, a 15% efficiency baseline was demonstrated in a device structure including a (110)-oriented GaAs substrate layer and a doped GaInP device layer, as well as their integration into a complete device with suitable quality. Demonstration of efficiencies within 15% (relative) in at least one device utilizing a spalled (110)-oriented GaAs substrate shows that major hurdles to regrowth on spalled surfaces do not exist. Overall, this validates the potential for both high-efficiency (110) devices as well as a viable low-cost pathway for substrate reuse on this platform.
So, in more detail, to evaluate the effect of growing device layers on a (110)-oriented GaAs substrate on device performance (e.g., a solar cell), a complete device stack having the architecture shown in Panel (a) of
An example of controlled spalling (i.e., separating, exfoliation) is illustrated in
In order for spalling to provide an economical substrate re-use solution, wafer-scale spalls should be demonstrated without significant edge effects that increase roughness and limit the number of achievable spalls per wafer. Therefore, (110)-oriented GaAs substrate wafers with 50-mm diameters were prepared for spalling by electroplating a stressed Ni layer on the surface of the GaAs substrate layers, defined by an edge-adhesion demoter of a photoresist (PR) mask coated on the outer 4 mm of the wafer radius. An area of 14 cm2 was spalled from wafers using an automated spalling apparatus. Development of edge-to-edge plating methods may eliminate the need for the demoter in the future.
A selective etching procedure was developed to measure the spalled depth of GaAs substrates. A gridded PR mask was applied to the substrate using photolithography and the exposed GaAs was etched. Spalled wafer surfaces were evaluated using laser profilometry, confocal microscopy, and atomic force microscopy (AFM) for surface roughness and topographical features. Crystallographic terraces, features distinct from surface facets and other fracture morphologies were observed on spalled (110)-GaAs samples with a terrace height, H, of between 0.1 μm and 1 μm, with slightly larger heights, H, observed on samples with high wafer offcut angle (1.5°±0.5°, 3°±0.5°). Relatively smooth terraces were observed, positioned in {110} planes with sub-nm roughness. The size of the terraces was determined to be dependent on the offcut angle of the substrate and the spall direction. Substrates with high offcut angle (1.5°±0.5°, 3°±0.5°) produced small terraces from a few microns to 10 s of micrometers in width, W. Substrates cut on-axis within ±0.5° and ±0.05° tolerance produced large terraces tens to hundreds of micrometers in width, W. Spall direction impacted terrace width on substrates with high offcut angles, producing wide parallel terraces when spalling in the [1-10] direction and small irregular terraces when spalling in the [00-1] direction (see
The foregoing discussion and examples have been presented for purposes of illustration and description. The foregoing is not intended to limit the aspects, embodiments, or configurations to the form or forms disclosed herein. In the foregoing Detailed Description for example, various features of the aspects, embodiments, or configurations are grouped together in one or more embodiments, configurations, or aspects for the purpose of streamlining the disclosure. The features of the aspects, embodiments, or configurations, may be combined in alternate aspects, embodiments, or configurations other than those discussed above. This method of disclosure is not to be interpreted as reflecting an intention that the aspects, embodiments, or configurations require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment, configuration, or aspect. While certain aspects of conventional technology have been discussed to facilitate disclosure of some embodiments of the present invention, the Applicants in no way disclaim these technical aspects, and it is contemplated that the claimed invention may encompass one or more of the conventional technical aspects discussed herein. Thus, the following claims are hereby incorporated into this Detailed Description, with each claim standing on its own as a separate aspect, embodiment, or configuration.
This application claims priority from U.S. Provisional Patent Application No. 63/216,391 filed on Jun. 29, 2021, the contents of which are incorporated herein by reference in their entirety.
This invention was made with government support under Contract No. DE-AC36-08GO28308 awarded by the Department of Energy. The government has certain rights in the invention.
| Number | Date | Country | |
|---|---|---|---|
| 63216391 | Jun 2021 | US |
