The present invention is directed, in general, to power electronics and, more specifically, to a power converter employing a control system configured to make multiple operational use of a circuit node therein and method of operating the same.
A switched-mode power converter (also referred to as a “power converter” or “regulator”) is a power supply or power processing circuit that converts an input voltage waveform into a specified output voltage waveform. Dc-dc power converters convert a direct current (“dc”) input voltage into a dc output voltage. Controllers associated with the power converters manage an operation thereof by controlling conduction periods of power switches employed therein. Some power converters include a controller coupled between an input and output of the power converter in a feedback loop configuration (also referred to as a “control loop” or “closed control loop”) to regulate an output signal or characteristic of the power converter. Typically, the controller measures the output characteristic (e.g., an output voltage, an output current, or a combination of an output voltage and an output current) of the power converter, and based thereon modifies a duty cycle which can be an ON time or a switching frequency of a power switch of the power converter to regulate the output characteristic. Other power converters operate in an open-loop manner wherein an output voltage is produced substantially proportional to an input voltage.
The number of physical input pins on integrated circuits (“ICs”) such as mixed-signal integrated circuits that embody a controller for a power converter typically sense a single analog voltage level entering the integrated circuit, and are limited to adjustment of only one internal signal level by that analog voltage level through external components. Occasionally, there is also a logic function associated with these input pins as well, but only a single voltage level sense. Thus, additional pins are conventionally added to an integrated circuit to provide additional voltage inputs for an internal signal that is utilized by the controller. However, the additional integrated circuit pins are expensive, especially when exceeding a typical package limit (e.g., changing from 16 to 17 or more pins). It is highly advantageous from a manufacturing cost perspective to maintain a standardized pin arrangement.
Accordingly, what is needed in the art is a design approach and related method for a control system for a power converter that enables multiple functional use of an integrated circuit input pin without compromising product performance, and that can be advantageously adapted to high-volume manufacturing techniques without adding significant cost. A further need in the art is elimination of an opto-isolator by sharing an opto-isolator (e.g., a feedback opto-isolator) with another opto-isolator (e.g., a fault opto-isolator) in the power converter.
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by advantageous embodiments of the present invention, including a power converter employing a control system configured to make multiple functional use of a circuit node therein and method of operating the same. In one embodiment, the power converter includes a power train including at least one power switch. The power converter also includes a control system including an opto-isolator circuit, including a resistor, configured to receive an output signal from the power converter and provide a feedback signal to a feedback node for the control system to provide a switch control signal for the at least one power switch. The control system also includes a current source configured to produce multiple voltage levels at the feedback node in accordance with the resistor, thereby enabling multiple functional uses of the feedback node.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated, and may not be redescribed in the interest of brevity after the first instance. The FIGUREs are drawn to illustrate the relevant aspects of exemplary embodiments.
The making and using of the present exemplary embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
The present invention will be described with respect to exemplary embodiments in a specific context, namely, a power converter employing a control system configured to provide multiple functional use of a circuit node (e.g., a pin such as a pin of an integrated circuit), or to eliminate a need for an added opto-isolator for fault reporting or other purposes. While the principles of the present invention will be described in the environment of a power converter, any application that may benefit from a control system as described herein including, without limitation, a bias supply, a power amplifier, or a motor controller is well within the broad scope of the present invention.
A resonant full-bridge or half-bridge power converter or other resonant power converter topology with a substantially symmetric input current waveform may be employed in low and medium power applications such as in a power adapter for a printer because of its low cost and high power conversion efficiency at power levels of interest for these applications. Power converters are typically designed to operate continuously at their full rated output power level.
Turning now to
The power converter includes first and second power switches Q1, Q2 in series with a dc bus (at an input of the power converter) produced by a dc input voltage source 110, represented in
The transformer T1, coupled to the first and second power switches Q1, Q2, has a primary winding P1, and first and second secondary windings S1, S2 with a turns ratio n:1:1 that is selected to provide an output signal or characteristic (e.g., an output voltage VOUT) with consideration of the range of the input voltage Vbus and stress on the power train of the power converter. A resonant full-bridge dc-dc power converter may be formed with two power switches substituted for the first and second divider capacitors C4, C5. Each of the added power switches in a full-bridge configuration would be switched substantially synchronously with a diagonally oriented power switch.
The first and second power switches Q1, Q2 (e.g., n-channel field-effect transistors) are controlled by a controller (or control system) 140 that produces switch control signals (e.g., gate-drive signals HDRV, LDRV) to control the first and second power switches Q1, Q2 to conduct for controlled intervals of time (i.e., for controlled “ON” times). The term “signal” is used herein to represent, without limitation, a physical voltage or current. The first and second power switches Q1, Q2 alternately conduct in response to the gate-drive signals HDRV, LDRV (e.g., gate-drive voltages) produced by the controller 140 with a switching frequency (designated “fs”) and a corresponding switching period Ts=1/fs. The ac voltage appearing or present on the first and second secondary windings S1, S2 of the transformer T1 is rectified by first and second diodes D1, D2, and the dc component of the resulting waveform is coupled to the output through the low pass output filter formed with output filter capacitor Cout to produce the output voltage VOUT. The controller 140 senses the output voltage VOUT to regulate the ON time of the first and second power switches Q1, Q2. The OFF time of the first and second power switches Q1, Q2 may also be adjusted as a function of a current or a power level of the power converter to reduce power converter losses as described by Jungreis, et al., cited previously hereinabove.
The power converter is operated as a resonant half-bridge topology. The term “resonant” is employed herein to refer to a switch-mode topology employing a resonant tank circuit or resonant circuit formed principally by a resonant capacitor C1 and a resonant inductor Lres to produce a current waveform that is a portion of, but may not be a full, sinusoidal waveform. The resonant circuit is series-coupled to the transformer T1. The circuit node between first and second divider capacitors C4, C5 substantially remains at a voltage approximately equal to half of the input voltage Vbus with respect to a primary ground, which is identified with the symbol “p.” The secondary ground is identified with the symbol “s.” The source of second power switch Q2 is coupled to the primary ground p.
The resonant capacitor C1 and the first and second divider capacitors C4, C5 are coupled together at common circuit node N0. The first and second divider capacitors C4, C5 are roughly equal in capacitance and the combination is generally larger in capacitance than that of the resonant capacitor C1. Such a structure provides symmetry from an EMI perspective for high frequency currents fed back to the dc input voltage source 110, and also provides a relatively unvarying voltage at the common circuit node N0. In an alternative embodiment, one or both of the resonant capacitor C1 and the first divider capacitor C4 can be omitted from the power converter. If both the resonant capacitor C1 and the first divider capacitor C4 are omitted from the power converter, the second divider capacitor C5 would be selected with a capacitance similar to that of resonant capacitor C1.
The resonant inductor Lres includes the leakage inductance of the transformer T1 referenced to its primary winding P1. The effective resonant capacitance is Ceff, given by the equation:
Ceff=C1·(C4+C5)/(C1+C4+C5).
The half period Thalf of the resonant circuit, which is the period during which a power switch is turned ON, can be represented approximately by the equation:
Thalf=π·√{square root over (Lres·Ceff)}.
If a power switch ON times are approximately equal to the half-period Thalf shown above, the power converter operates as a “dc transformer” that produces an output voltage VOUT substantially proportional to the input voltage Vbus. The output-to-input voltage ratio is substantially fixed by the transformer T1 turns ratio when it is operated as a dc transformer, and thus the power converter per se does not provide output voltage regulation if the power switch ON times are approximately equal to the half period Thalf shown above. Regulation of the output voltage VOUT in such an arrangement can be provided by a pre-converter stage (not shown) that regulates the input voltage Vbus to the power converter illustrated in
Control (e.g., modification, alteration, variation, etc.) of the switching frequency by varying the ON time of the first and second power switches Q1, Q2 can be employed to regulate the output voltage VOUT of the power converter. In an embodiment, the ON time (or conduction periods or a duty cycle) between fixed OFF times of the first and second power switches Q1, Q2 may be varied to control the switching frequency to regulate the output voltage VOUT. The dead times between power switch conduction periods and/or the ON times of the first and second power switches Q1, Q2 may be substantially equal, but are not required to be so.
At a high input voltage level, the power train may be operated at a switching frequency that is higher than the resonant frequency fres of the resonant circuit. At a high input voltage level, the ON time (often referred to or designated as “Ton”) of each of the first and second power switches Q1, Q2 corresponds to an ON time that is equivalent to a frequency that is a higher than the resonant frequency of the resonant circuit. In other words, the ON time for each of the first and second power switches Q1, Q2 is a little shorter than the half period Thalf of the resonant circuit, and together the first and second power switches Q1, Q2 are ON for a period of time that is a little shorter or less than twice the half period Thalf. The ON times of the first and second power switches Q1, Q2 are preferably, but not necessarily, equal. Thus, the first and second power switches Q1, Q2 are turned OFF before the time that the current in the resonant circuit reaches zero, and the switching period is kept short enough and the dead-time between alternate switch conduction times long enough to assure that, throughout the tolerance band of variations of power converter inductances and capacitances, the current through a controlled switch on a primary side of the power converter will shift to an anti-parallel diode (or body diode) of the power switch that is about to be turned ON (or prior to turning ON the same) or that the resonant current has decayed to approximately zero. The body diodes of the first and second power switches Q1, Q2 are designated DBD1, DBD2, respectively. Thus, a variable ON time is employable in a power converter such as a resonant bridge power converter to regulate the output voltage VOUT.
In U.S. patent application Ser. No. 12/486,520, entitled “Power Converter Employing a Variable Switching Frequency and a Magnetic Device with a Non-Uniform Gap,” to A. Brinlee, et al., filed Jun. 17, 2009, which is incorporated herein by reference, a switching frequency of a power switch of a power converter is controlled as a function of a condition of the power converter representing an output power. Also, a duty cycle of the power switch(es) is controlled to regulate an output characteristic of the power converter such as the output voltage. The ON time of the power switches may be controlled (e.g., slightly modulated) to reduce or cancel a ripple voltage (e.g., a 120 hertz ripple voltage) of an input voltage source such as an upstream power converter (e.g., a power factor correction converter) to the power converter employing the power switches.
Turning now to
Thus, the OFF times of the power switches (such as the first and second power switches Q1, Q2 illustrated with respect to
The input pins on mixed signal integrated circuits such as an integrated circuit embodying a controller for an LLC power stage typically sense a single analog voltage level entering the integrated circuit, and are limited to an adjustment of one internal level by that analog voltage level through external components. An integrated circuit embodying a controller is generally formed as an application specific integrated circuit (“ASIC”), and will be generally referred to herein as an integrated circuit. Occasionally, there is also a logic function associated with these pins as well, but only a single voltage level sense. Thus, additional pins, which are generally expensive, are conventionally added to an integrated circuit to provide additional voltage inputs for an internal signal.
Turning now to
The power train 301 is formed with transformer T2 with primary windings P1, P2, P3 and secondary windings S1, S2. A bias startup circuit 302 is coupled to hot and neutral lines H, N, of ac mains to a capacitor C8 through the high resistance of a resistor R8 to provide a startup voltage for a bias voltage source VCC. When the voltage of the bias voltage source VCC is greater than a threshold voltage, such as 16 volts, a comparator U24 produces a signal (an under-voltage lockout “UVLO”) that enables power switch control signals DRV_A, DRV_B to be generated by the controller. The power switch control signals DRV_A, DRV_B are coupled to high-side and low-side driver 307 to initiate switching operation of the power train 301. High-side and low-side driver 307 produces gate-drive signals HDRV, LDRV for the power switches Q1, Q2. The switching action of the power train 301 provides an ongoing energy source for the bias voltage source VCC from the primary windings P2, P3. An internal five volt linear regulator 314 coupled to the bias voltage source VCC produces an internal regulated bias voltage source VREF. A capacitor C5 filters high-frequency components from the regulated bias voltage source VREF, and provides stability for the linear regulator 314.
The power converter illustrated in
A current produced by a current source I1 (or, in an alternative embodiment, a current sink) is applied within the controller 304 to the feedback node FB to enable multiple functional uses thereof. The amount of current produced by the current source I1 is designed to be low compared with the current that would otherwise flow through any impedances that would typically be connected to that node FB. The current source I1 is switched ON and OFF with a timing signal TOFF inside the controller 304. A timing signal TON produced by a timing clock U12 coupled to the timing circuit 306 is inverted by an inverter U16 to produce the timing signal TOFF. By placing a large-resistance resistor R23 in series with the feedback node FB, two levels of voltage can be selectively obtained at the node FB. These two levels of voltage are a function of both the voltage level that would be present without the current source I1 as well as with the (large) resistance value of the resistor R23 (e.g., 100 kilo-ohms “kΩ”) placed in series with the feedback node FB and the current source I1. Two separate resistors (e.g., resistors R5 and R23) external to the controller 304 can accordingly be used to adjust two separate parameters therein using only a single integrated feedback node FB. As an example, the value of the current source I1 is ten microamperes (“μA”) when the timing signal TOFF is high and zero amperes when the timing signal TOFF is low. Thus, the voltage appearing on the feedback node FB is equal to the voltage across the resistor R5 when the timing signal TOFF is low and is equal to the voltage across the resistor R5 plus one volt when the timing signal TOFF is high. The voltage differential of one volt can be changed external to the controller by changing the value of the resistor R23.
The feedback node FB thus allows external adjustment of a number of parameters. A circuit (a non-latching shutdown circuit) 312 illustrated in
The feedback node FB generates a current through a voltage controlled current source G1 that is proportional thereto minus an offset of approximately 1.2 volts produced by an emitter follower Q5 and the base-emitter drop inside the current mirror that is used to create the voltage controlled current source G1. This current, which is a function of the feedback voltage at the feedback node FB, modulates the current into a timing capacitor C1 coupled to a circuit node or pin CT during the ON time of the gate drives (that is, when the timing signal TON is high and the timing signal TOFF is low). The 1.2 voltage offset allows for an external setting of the opto-isolator bias current through the choice of the resistor R5.
Turning now to
Returning to
The current source I1 that may be formed with a current mirror and a resistor in a conventional manner and controlled by the timing signal TOFF injects a square wave of current into the feedback node FB. An exemplary injected current amplitude would be approximately ten microamperes, which produces a square-wave offset voltage of about the same. Since the resistance of the resistor R5 (e.g., one kilo-ohm “kΩ”) is typically much lower than the resistance of resistor R23 (e.g., 100 kilo-ohms) the effect of the ten microampere injected current on the voltage across the resistor R5 is negligible. The current source I1 that produces the current is turned off by a switch S2 during the ON time of the gate drives. What results is a superimposed square wave voltage at the feedback node FB of the controller 304. The superimposed square wave voltage has an amplitude equal to the product of the current amplitude of the switching current source and the external resistor R23 in series with the feedback node FB. In this case, the amplitude of the superimposed square wave voltage would be approximately one volt [(10 μA)×·(100 kΩ)=1 volt].
Logic coupled to the comparator U4 for the controller 304 transitions the same into a low power mode when the feedback voltage at the opto-isolator emitter rises above 2.1 volts, but gates the controller 304 out of the low power mode after the feedback voltage at the opto-isolator emitter falls below about 1.1 volts. The one volt hysteresis band is settable by changing the resistance value of the external resistor R23.
The process to make multifunctional use of the feedback node FB advantageously includes turning a low value current source (or sink) ON and OFF in synchronization with a clock oscillator and injecting the current produced by the current source I1 into a circuit node such as the feedback node FB that is used to sense a voltage. The gating of a condition within the controller 304 is also timed to coincide with the gating of the current source I1 so that a band of hysteresis is created that can be externally set with a single resistance value (e.g., the resistance of resistor R23). The process thus allows for an increase in the number of externally settable parameters for the controller 304 without increasing a pin count. The process can also be used to increase the number of sensed parameters to three rather than two by using both a current source and a current sink that are turned ON and OFF in synchronization with the controller 304.
A signal LLC_RUN that is an enabling signal for the overall operation of the power converter is produced by logic U13. This signal LLC_RUN is generally produced by logic U3 that is tailored for a particular power converter design, and will not be further described herein in the interest of brevity. In addition, internal reference voltages such as “4V7,” “3V7,” etc., representing voltage sources with respective voltages of 4.7 volts, 3.7 volts, etc., are conventionally produced by small internal dissipative regulators and/or voltage dividers coupled to the bias voltage sources VCC, VREF, and will also not be further described herein in the interest of brevity.
Turning now to
Returning again to
Thus, a controller 304 has been introduced that may be formed as an integrated circuit for a power converter. The power converter may be constructed as an LLC power stage. The controller 304 is constructed with a feedback node FB configured to alter a gate drive signal [HDRV or LDRV] for a power switch [Q2 or Q1] in the power converter. A current source I1 in the controller 304 is coupled to the feedback node FB. The current source I1 may be selectively turned ON in synchronization by a timing signal (a clock signal) TOFF in the controller 304 (to produce a square-wave voltage at the feedback node FB). A resistor R23 is coupled between the feedback node FB and a feedback control signal [such as the feedback current control signal produced by opto-isolator U6]. Also, a comparator U4 is coupled to the feedback node FB. The comparator U4 is configured to produce a signal to control a function of the power converter in response to a voltage produced at the feedback node FB by the selectively enabled current source I1. The selectively enabled current source I1 may alter the feedback control signal to accommodate a low power mode of the power converter. The selectively enabled current source I1 creates a hysteresis band to prevent oscillating between the low power mode and a standard power mode of the power converter.
The controller 304 may further include a comparator [U11 or U14] as part of one of the circuits 311, 312 configured to transition the controller 304 to another operational mode of the power converter, such as a latching or non-latching shutdown mode, in response to the voltage produced at the feedback node FB by the current source I1. The comparator may be employed in addition to or in lieu of the selectively enabled current source I1. A Zener diode (e.g., ZD400) may be coupled to the feedback control signal to provide a limit for an operational characteristic of the controller 304 such as a switching frequency.
The controller may further include another current source that is selectively turned ON in synchronization with the timing signal TOFF and another comparator configured to control another function of the power converter in response to a voltage produced at the feedback node FB by the another selectively enabled current source. The another selectively enabled current source may be selectively turned ON in synchronization with a sub-multiple of the timing signal TOFF such as a sub-multiple clock signal produced by a T (toggle) flip-flop coupled to the timing signal TOFF.
Additional pins are also conventionally added to a controller formed as an integrated circuit to enable additional parameters to be set related to timing conduction of power switches. Typically, an oscillator function of the controller is formed with a charge/discharge source connected to an external resistor and capacitor. A sense node or pin is coupled to the external capacitor that senses the voltage on the external capacitor, and another pin is employed to provide another coupling to the external resistor. This allows a single controller parameter to be set through external components. As introduced herein, two changes are made to a conventional circuit to enable several parameters to be externally set for the controller using the same two pins. The first change involves enabling a charge/discharge pin also go to a tri-state value during certain modes of operation of the controller. The term tri-state refers to a circuit condition wherein a signal line is open circuited, and pulled neither high nor low. The second change involves gating the information from the feedback control node or pin FB, a third pin, to draw current through the external timing capacitor C1 during a charge or discharge cycle, but preferably not both.
As previously described hereinabove,
When a voltage on the pin RT is high, the timing capacitor C1 charges through series-coupled resistors (charge/discharge resistors) R1, R22. Due to the presence of the diode D1, when the voltage on the pin RT is low, the timing capacitor C1 discharges through the resistor R1. The resistor R22 has negligible effect. When the circuit coupled to the pin RT is tri-state (e.g., when the switches Q4, Q11 are both disabled to conduct), the timing capacitor C1 slowly discharges through resistor R13. While the resistor R13 is always in the circuit regardless of the state of the circuit coupled to the pin RT, in practice, the resistor R13 has negligible effect when the circuit coupled to the pin RT is not tri-state since the resistances of resistors R1, R22 are significantly smaller than the resistance of resistor R13. Furthermore, the voltage of the feedback node FB is translated to a current inside the controller 304 by voltage controlled current source G1. This current increases the charging rate of the timing capacitor C1 to change the ON time of the switch control signals (or gate drive signals). The switch S3 shuts off the current source G1 (which is increasing the charging rate) during the discharge of the timing capacitor C1 (corresponding to the OFF time (or dead-time) of the gate drive signals). The voltage on the feedback node FB, therefore, only affects the ON time of the power switches Q1, Q2, not the OFF time.
When the voltage of the feedback node FB exceeds a predetermined threshold (about 2.1 volts for the power converter illustrated in
Accordingly, the normal operation ON time, normal operation OFF time, and low power OFF time can be set with external resistors using two integrated circuit nodes or pins RT, CT. Furthermore, since the feedback voltage threshold for transitioning to a low power mode is fixed internal to the controller 304 and corresponds to a fixed level of timing current being supplied to the external timing capacitor C1, the gate drive ON time at which the controller 304 enters low power mode can be changed by adjusting the value of the timing capacitor C1. The ability to externally set the OFF time is important since it allows tuning a resonant tank to have substantially zero-voltage switching regardless of a transformer leakage inductance.
It is also noted that pulling the CT pin up to a voltage between 2.5 and five volts and holding it at a voltage level puts the timing into the OFF time and effectively disables the gate drive signals, thus allowing a separate control mechanism for disabling the output of the power converter. Pulling the CT pin to local circuit ground will also disable the power converter as well as reset the soft-start circuit; however, when pulling the CT pin to local circuit ground, one of the gate drive signals will be kept high. Thus, a process and method are introduced to design an integrated circuit for a controller 304 so that multiple (e.g., four) parameters can be adjusted with two timing pins on the integrated circuit such as the ON time, OFF time, low power OFF time, and low power threshold voltage. One of the timing pins can also be used for an output gate drive disable function.
Thus, a controller 304 has been introduced that may be formed as an integrated circuit for a power converter (e.g., a power converter constructed with an LLC power stage). The controller 304 is constructed with two nodes or pins, a first node CT and a second node RT. A capacitor C1 is coupled to the first node CT. A comparator U12 is also coupled to the first node CT, and the comparator U12 is configured to control a power switch of the power converter. The second node RT is coupled to the first node CT through a resistor-diode network (a timing circuit 306). A first switch Q11 is coupled to the second timing node RT. The first switch Q11 is configured to couple the second node RT to a bias voltage source, and the second node RT is configured to charge the timing capacitor C1 through a resistor R22 in the timing circuit 306 when the second node RT is coupled to the bias voltage source by the first switch Q11. A second switch Q4 is also coupled to the second node RT. The second switch Q4 is configured to couple the second node RT to a second voltage level, local circuit ground. The second node RT is configured to discharge the capacitor C1 through a resistance R1 in the timing circuit 306 when the second node RT is coupled to the second voltage level by the second switch Q4.
If the bias voltage source is brought out of the controller 304 (i.e., if the bias voltage source is duplicated external thereto through a linear regulator) one can flip the resistor-capacitor-diode network shown in the timing circuit 306 as well as flip the logic. In the power converter illustrated in
If the logic is flipped, then the second node RT would be dropped to zero volts to discharge the timing capacitor C1, corresponding to when the timing signal TON is enabled. The second node RT being raised to five volts would charge the timing capacitor C1, corresponding to when the timing signal TOFF is enabled. A disadvantage with this direction of the charge/discharge of the timing capacitor C1 is that a tri-state does not allow a slow discharge of the timing capacitor C1 unless the resistor R13 is connected to five volts rather than to local circuit ground. The resistor R13 cannot be connected to five volts unless either the bias voltage source is externally available on the integrated circuit, or another five voltage supply is created such as by using a five voltage Zener diode or a linear regulator after the bias voltage source.
The controller 304 is further constructed to operate the first and second switches Q11, Q4 coupled to the first node CT in a tri-state mode in response to an internal signal, wherein the first switch Q11 and the second switch Q4 are both disabled to conduct, enabling the timing capacitor C1 to be discharged through a third resistance R13. The internal signal is generated by a comparator [U11 or U14] sensing a voltage produced by a feedback control signal coupled to a feedback node or pin FB exceeding a threshold voltage level to signal the controller 304 to operate in a low power mode. A Zener diode ZD400 may be coupled to the feedback control signal to provide a limit for an operational characteristic of the controller 304, such as a switching frequency. Ac-dc power supplies typical require the secondary side of the circuit to transmit fault information (e.g., overvoltage protection “OVP” and overcurrent protection “OCP” signals) to a controller to latch off the operation of the power converter or to initiate an auto-restart mode. Transmitting fault information across the primary-secondary isolation boundary usually entails adding a second opto-isolator in addition to a first opto-isolator used for the feedback signal. Adding a second opto-isolator to the design of a controller takes up additional space and cost.
The integrated circuit for the controller 304 is generally formed with comparators coupled to a feedback node or pin FB. When a voltage of the feedback node FB exceeds a level expected in a normal feedback range, it trips fault logic in the integrated circuit. There are two levels for comparison beyond that of the normal feedback range. The lower level initiates a non-latching fault, wherein the operation of the power converter is restarted when the voltage of the feedback node FB falls below the lower level, and a “wait” time has expired. The higher level initiates a latching fault that generally requires removal of input power to the power converter for a sufficient period of time to reset.
As mentioned above,
The feedback node FB is responsive to a second type of fault shutdown. If the voltage of the feedback node FB exceeds 4.7 volts, a thyristor formed by the pair of switches Q19, Q20 draw down the voltage of the bias voltage source VCC and continue to hold the voltage of the bias voltage source VCC down while there is any current flowing thereto, which can be sourced by the bias startup circuit 302. The non-latching fault input already described disables the gate drive signals HDRV, LDRV while the fault on the feedback node FB exceeds 3.7 volts. Thus, when the voltage at the feedback node FB exceeds 4.7 volts, the gate drive signals HDRV, LDRV are disabled and the thyristor formed by the pair of switches Q19, Q20 will turn ON, holding down the voltage of the bias voltage source VCC.
In the case of the non-latching fault, the switch Q11 draws down the voltage of the bias voltage source VCC until the UVLO signal goes low. In contrast, during a latching fault, the thyristor draws down the voltage of the bias voltage source VCC as long as there is any holding current in the thyristor. The bias startup circuit 302 that is designed to provide startup power to the controller 304 provides the holding current for the thyristor. If the bias voltage source VCC is connected to a rectified input line via a high-voltage current source or by a resistor, the controller 304 will remain latched off until the power converter is disconnected from the ac mains for a sufficient period of time (e.g., to discharge the capacitor C8), and is then reconnected.
In order to use the latching or non-latching fault capability of the controller 304, the secondary-side fault output is connected to a switch (switch Q21 in
The opto-isolator circuit 305 that is already used to provide a feedback signal to the feedback node FB to regulate an output signal or characteristic of the power converter such as the output voltage VOUT can therefore also be used to provide latching or non-latching fault capability for the power converter. Whether the fault is latching or non-latching can be set externally by the presence or absence of a Zener diode on the feedback node FB.
Thus, a controller 304 has been introduced that may be formed as an integrated circuit for a power converter. The controller 304 is constructed with a feedback node FB configured to receive a feedback control signal from an opto-isolator circuit 305 to produce a control signal for a power switch in the power converter. The power converter may be constructed, without limitation, as an LLC power stage or a pulse-width modulated (“PWM”) power converter. A comparator U11 is coupled to the feedback node FB, and the comparator U11 is configured to enable a first mode of operation for the power converter (e.g., a non-latching shutdown mode) when a voltage to the comparator U11 produced at the feedback node FB exceeds a first threshold voltage. A selectively switched current source, resistor R45, switch Q21, may be coupled to the opto-isolator circuit 305, and the selectively switched current source may be employed to selectively produce a level of current in the opto-isolator circuit 305 sufficient to trip the comparator U11. The controller 304 further includes a comparator U14 coupled to the feedback node FB, and the comparator U14 is configured to enable a second mode of operation for the power converter (e.g., a latching shutdown mode), when a voltage to the comparator U14 produced at the feedback node FB exceeds a second threshold voltage.
A Zener diode ZD400 may be coupled to the feedback control signal to prevent the voltage to the comparator U14 produced at the feedback node FB from exceeding the second threshold voltage. A Zener diode ZD401 may be placed directly across the feedback node FB to prevent the voltage to the comparator U14 produced at the feedback node FB from exceeding the second threshold voltage. Inclusion of the Zener diode prevents the comparator from enabling the second mode of operation.
Those skilled in the art should understand that the previously described embodiments of a power converter including circuits to make multiple functional use of a circuit node or pin and related methods of operating the same are submitted for illustrative purposes only. While a power converter including circuits to make multiple functional use of a circuit node or pin has been described in the environment of a power converter, these processes may also be applied to other systems such as, without limitation, a bias supply, a power amplifier, or a motor controller. Additionally, it should be understood that separations in circuit functions are provided only for the purposes of description, and selected circuits may be combined into an integrated controller and still fall within the broad scope of the present invention. For the purposes of the discussion herein, a control system may include, without limitation, a controller, opto-isolator circuit, timing circuit, bias startup circuit, output voltage sensing circuit and a driver. In short, any circuit that assists in the management or control of a power train of a power converter may be incorporated into a controller or control system.
For a better understanding of power converters, see “Modern DC-to-DC Power Switch-mode Power Converter Circuits,” by Rudolph P. Severns and Gordon Bloom, Van Nostrand Reinhold Company, New York, N.Y. (1985) and “Principles of Power Electronics,” by J. G. Kassakian, M. F. Schlecht and G. C. Verghese, Addison-Wesley (1991).
Also, although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
This application claims the benefit of U.S. Provisional Application No. 61/314,900, entitled “Controller for a Power Converter and Method of Operating the Same,” filed on Mar. 17, 2010, which application is incorporated herein by reference.
Number | Name | Date | Kind |
---|---|---|---|
1376978 | Stoekle | May 1921 | A |
2473662 | Pohm | Jun 1949 | A |
3007060 | Guenther | Oct 1961 | A |
3346798 | Dinger | Oct 1967 | A |
3358210 | Grossoehme | Dec 1967 | A |
3433998 | Woelber | Mar 1969 | A |
3484562 | Kronfeld | Dec 1969 | A |
3553620 | Cielo et al. | Jan 1971 | A |
3622868 | Todt | Nov 1971 | A |
3681679 | Chung | Aug 1972 | A |
3708742 | Gunn | Jan 1973 | A |
3708744 | Stephens et al. | Jan 1973 | A |
4011498 | Hamstra | Mar 1977 | A |
4019122 | Ryan | Apr 1977 | A |
4075547 | Wroblewski | Feb 1978 | A |
4202031 | Hesler et al. | May 1980 | A |
4257087 | Cuk | Mar 1981 | A |
4274071 | Pfarre | Jun 1981 | A |
4327348 | Hirayama | Apr 1982 | A |
4471423 | Hase | Sep 1984 | A |
4499481 | Greene | Feb 1985 | A |
4570174 | Huang et al. | Feb 1986 | A |
4577268 | Easter et al. | Mar 1986 | A |
4581691 | Hock | Apr 1986 | A |
4613841 | Roberts | Sep 1986 | A |
4636823 | Margalit et al. | Jan 1987 | A |
4660136 | Montorefano | Apr 1987 | A |
4672245 | Majumdar et al. | Jun 1987 | A |
4770667 | Evans | Sep 1988 | A |
4770668 | Skoultchi et al. | Sep 1988 | A |
4780653 | Bezos et al. | Oct 1988 | A |
4785387 | Lee et al. | Nov 1988 | A |
4799138 | Chahabadi et al. | Jan 1989 | A |
4803609 | Gillett et al. | Feb 1989 | A |
4823249 | Garcia, II | Apr 1989 | A |
4837496 | Erdi | Jun 1989 | A |
4866367 | Silva et al. | Sep 1989 | A |
4876638 | Silva et al. | Oct 1989 | A |
4887061 | Matsumura | Dec 1989 | A |
4899271 | Seiersen | Feb 1990 | A |
4903089 | Hollis et al. | Feb 1990 | A |
4922400 | Cook | May 1990 | A |
4962354 | Visser et al. | Oct 1990 | A |
4964028 | Spataro | Oct 1990 | A |
4999759 | Cavagnolo et al. | Mar 1991 | A |
5003277 | Sokai et al. | Mar 1991 | A |
5014178 | Balaakrishnan | May 1991 | A |
5027264 | DeDoncker et al. | Jun 1991 | A |
5055991 | Carroll et al. | Oct 1991 | A |
5068756 | Morris et al. | Nov 1991 | A |
5106778 | Hollis et al. | Apr 1992 | A |
5126714 | Johnson | Jun 1992 | A |
5132888 | Lo et al. | Jul 1992 | A |
5134771 | Lee et al. | Aug 1992 | A |
5177460 | Dhyanchand et al. | Jan 1993 | A |
5182535 | Dhyanchand | Jan 1993 | A |
5204809 | Andresen | Apr 1993 | A |
5206621 | Yerman | Apr 1993 | A |
5208739 | Sturgeon | May 1993 | A |
5223449 | Morris et al. | Jun 1993 | A |
5225971 | Spreen | Jul 1993 | A |
5231037 | Yuan et al. | Jul 1993 | A |
5244829 | Kim | Sep 1993 | A |
5262930 | Hua et al. | Nov 1993 | A |
5291382 | Cohen | Mar 1994 | A |
5303138 | Rozman | Apr 1994 | A |
5305191 | Loftus, Jr. | Apr 1994 | A |
5335163 | Seiersen | Aug 1994 | A |
5336985 | McKenzie | Aug 1994 | A |
5342795 | Yuan et al. | Aug 1994 | A |
5343140 | Gegner | Aug 1994 | A |
5353001 | Meinel et al. | Oct 1994 | A |
5369042 | Morris et al. | Nov 1994 | A |
5374887 | Drobnik | Dec 1994 | A |
5399968 | Sheppard et al. | Mar 1995 | A |
5407842 | Morris et al. | Apr 1995 | A |
5453923 | Scalais et al. | Sep 1995 | A |
5459652 | Faulk | Oct 1995 | A |
5468661 | Yuan et al. | Nov 1995 | A |
5477175 | Tisinger et al. | Dec 1995 | A |
5508903 | Alexndrov | Apr 1996 | A |
5523673 | Ratliff et al. | Jun 1996 | A |
5539630 | Pietkiewicz et al. | Jul 1996 | A |
5554561 | Plumton | Sep 1996 | A |
5555494 | Morris | Sep 1996 | A |
5581224 | Yamaguchi | Dec 1996 | A |
5610085 | Yuan et al. | Mar 1997 | A |
5624860 | Plumton et al. | Apr 1997 | A |
5661642 | Shimashita | Aug 1997 | A |
5663876 | Newton et al. | Sep 1997 | A |
5671131 | Brown | Sep 1997 | A |
5700703 | Huang et al. | Dec 1997 | A |
5712189 | Plumton et al. | Jan 1998 | A |
5719544 | Vinciarelli et al. | Feb 1998 | A |
5734564 | Brkovic | Mar 1998 | A |
5736842 | Jovanovic | Apr 1998 | A |
5742491 | Bowman et al. | Apr 1998 | A |
5747842 | Plumton | May 1998 | A |
5756375 | Celii et al. | May 1998 | A |
5760671 | Lahr et al. | Jun 1998 | A |
5783984 | Keuneke | Jul 1998 | A |
5784266 | Chen | Jul 1998 | A |
5804943 | Kollman et al. | Sep 1998 | A |
5815386 | Gordon | Sep 1998 | A |
5864110 | Moriguchi et al. | Jan 1999 | A |
5870299 | Rozman | Feb 1999 | A |
5886508 | Jutras | Mar 1999 | A |
5889298 | Plumton et al. | Mar 1999 | A |
5889660 | Taranowski et al. | Mar 1999 | A |
5900822 | Sand et al. | May 1999 | A |
5909110 | Yuan et al. | Jun 1999 | A |
5910665 | Plumton et al. | Jun 1999 | A |
5920475 | Boylan et al. | Jul 1999 | A |
5925088 | Nasu | Jul 1999 | A |
5929665 | Ichikawa et al. | Jul 1999 | A |
5933338 | Wallace | Aug 1999 | A |
5940287 | Brkovic | Aug 1999 | A |
5946207 | Schoofs | Aug 1999 | A |
5956245 | Rozman | Sep 1999 | A |
5956578 | Weitzel et al. | Sep 1999 | A |
5959850 | Lim | Sep 1999 | A |
5977853 | Ooi et al. | Nov 1999 | A |
5982640 | Naveed et al. | Nov 1999 | A |
5999066 | Saito et al. | Dec 1999 | A |
5999429 | Brown | Dec 1999 | A |
6003139 | McKenzie | Dec 1999 | A |
6008519 | Yuan et al. | Dec 1999 | A |
6011703 | Boylan et al. | Jan 2000 | A |
6038154 | Boylan et al. | Mar 2000 | A |
6046664 | Weller et al. | Apr 2000 | A |
6060943 | Jansen | May 2000 | A |
6067237 | Nguyen | May 2000 | A |
6069798 | Liu | May 2000 | A |
6069799 | Bowman et al. | May 2000 | A |
6078510 | Spampinato et al. | Jun 2000 | A |
6084792 | Chen et al. | Jul 2000 | A |
6094038 | Lethellier | Jul 2000 | A |
6097046 | Plumton | Aug 2000 | A |
6125046 | Jang et al. | Sep 2000 | A |
6144187 | Bryson | Nov 2000 | A |
6147886 | Wittenbreder | Nov 2000 | A |
6156611 | Lan et al. | Dec 2000 | A |
6160721 | Kossives et al. | Dec 2000 | A |
6163466 | Davila, Jr. et al. | Dec 2000 | A |
6181231 | Bartilson | Jan 2001 | B1 |
6188586 | Farrington et al. | Feb 2001 | B1 |
6191964 | Boylan et al. | Feb 2001 | B1 |
6208535 | Parks | Mar 2001 | B1 |
6212084 | Turner | Apr 2001 | B1 |
6215290 | Yang et al. | Apr 2001 | B1 |
6218891 | Lotfi et al. | Apr 2001 | B1 |
6229197 | Plumton et al. | May 2001 | B1 |
6262564 | Kanamori | Jul 2001 | B1 |
6288501 | Nakamura et al. | Sep 2001 | B1 |
6288920 | Jacobs et al. | Sep 2001 | B1 |
6295217 | Yang et al. | Sep 2001 | B1 |
6304460 | Cuk | Oct 2001 | B1 |
6309918 | Huang et al. | Oct 2001 | B1 |
6317021 | Jansen | Nov 2001 | B1 |
6317337 | Yasumuar | Nov 2001 | B1 |
6320490 | Clayton | Nov 2001 | B1 |
6323090 | Zommer | Nov 2001 | B1 |
6325035 | Codina et al. | Dec 2001 | B1 |
6344986 | Jain et al. | Feb 2002 | B1 |
6348848 | Herbert | Feb 2002 | B1 |
6351396 | Jacobs | Feb 2002 | B1 |
6356462 | Jang et al. | Mar 2002 | B1 |
6362986 | Schultz et al. | Mar 2002 | B1 |
6373727 | Hedenskog et al. | Apr 2002 | B1 |
6373734 | Martinelli | Apr 2002 | B1 |
6380836 | Matsumoto et al. | Apr 2002 | B2 |
6388898 | Fan et al. | May 2002 | B1 |
6392902 | Jang et al. | May 2002 | B1 |
6396718 | Ng et al. | May 2002 | B1 |
6400579 | Cuk | Jun 2002 | B2 |
6414578 | Jitaru | Jul 2002 | B1 |
6418039 | Lentini et al. | Jul 2002 | B2 |
6438009 | Assow | Aug 2002 | B2 |
6445598 | Yamada | Sep 2002 | B1 |
6462965 | Uesono | Oct 2002 | B1 |
6466461 | Mao et al. | Oct 2002 | B2 |
6469564 | Jansen | Oct 2002 | B1 |
6477065 | Parks | Nov 2002 | B2 |
6483724 | Blair et al. | Nov 2002 | B1 |
6489754 | Blom | Dec 2002 | B2 |
6498367 | Chang et al. | Dec 2002 | B1 |
6501193 | Krugly | Dec 2002 | B1 |
6504321 | Giannopoulos et al. | Jan 2003 | B2 |
6512352 | Qian | Jan 2003 | B2 |
6525603 | Morgan | Feb 2003 | B1 |
6539299 | Chatfield et al. | Mar 2003 | B2 |
6545453 | Glinkowski et al. | Apr 2003 | B2 |
6548992 | Alcantar et al. | Apr 2003 | B1 |
6549436 | Sun | Apr 2003 | B1 |
6552917 | Bourdillon | Apr 2003 | B1 |
6559689 | Clark | May 2003 | B1 |
6563725 | Carsten | May 2003 | B2 |
6570268 | Perry et al. | May 2003 | B1 |
6580627 | Toshino | Jun 2003 | B2 |
6608768 | Sula | Aug 2003 | B2 |
6611132 | Nakagawa et al. | Aug 2003 | B2 |
6614206 | Wong et al. | Sep 2003 | B1 |
6654259 | Koshita et al. | Nov 2003 | B2 |
6661276 | Chang | Dec 2003 | B1 |
6668296 | Dougherty et al. | Dec 2003 | B1 |
6674658 | Mao et al. | Jan 2004 | B2 |
6683797 | Zaitsu et al. | Jan 2004 | B2 |
6687137 | Yasumuar | Feb 2004 | B1 |
6696910 | Nuytkens et al. | Feb 2004 | B2 |
6731486 | Holt et al. | May 2004 | B2 |
6741099 | Krugly | May 2004 | B1 |
6751106 | Zhang et al. | Jun 2004 | B2 |
6753723 | Zhang | Jun 2004 | B2 |
6765810 | Perry | Jul 2004 | B2 |
6775159 | Webb et al. | Aug 2004 | B2 |
6784644 | Xu et al. | Aug 2004 | B2 |
6804125 | Brkovic | Oct 2004 | B2 |
6813170 | Yang | Nov 2004 | B2 |
6831847 | Perry | Dec 2004 | B2 |
6839247 | Yang et al. | Jan 2005 | B1 |
6856149 | Yang | Feb 2005 | B2 |
6862194 | Yang et al. | Mar 2005 | B2 |
6867678 | Yang | Mar 2005 | B2 |
6867986 | Amei | Mar 2005 | B2 |
6873237 | Chandrasekaran et al. | Mar 2005 | B2 |
6882548 | Jacobs et al. | Apr 2005 | B1 |
6906934 | Yang et al. | Jun 2005 | B2 |
6943553 | Zimmerman | Sep 2005 | B2 |
6944033 | Xu et al. | Sep 2005 | B1 |
6977824 | Yang et al. | Dec 2005 | B1 |
6980077 | Chandrasekaran et al. | Dec 2005 | B1 |
6982887 | Batarseh et al. | Jan 2006 | B2 |
7009486 | Goeke et al. | Mar 2006 | B1 |
7012414 | Mehrotra et al. | Mar 2006 | B1 |
7016204 | Yang et al. | Mar 2006 | B2 |
7026807 | Anderson et al. | Apr 2006 | B2 |
7034586 | Mehas et al. | Apr 2006 | B2 |
7034647 | Yan et al. | Apr 2006 | B2 |
7046523 | Sun et al. | May 2006 | B2 |
7061358 | Yang | Jun 2006 | B1 |
7072189 | Kim | Jul 2006 | B2 |
7075799 | Qu | Jul 2006 | B2 |
7076360 | Ma | Jul 2006 | B1 |
7095638 | Uusitalo | Aug 2006 | B2 |
7099163 | Ying | Aug 2006 | B1 |
7136293 | Petkov et al. | Nov 2006 | B2 |
7148669 | Maksimovic et al. | Dec 2006 | B2 |
7170268 | Kim | Jan 2007 | B2 |
7176662 | Chandrasekaran | Feb 2007 | B2 |
7200016 | Ogawa | Apr 2007 | B2 |
7209024 | Nakahori | Apr 2007 | B2 |
7269038 | Shekhawat et al. | Sep 2007 | B2 |
7280026 | Chandrasekaran et al. | Oct 2007 | B2 |
7285807 | Brar et al. | Oct 2007 | B2 |
7298118 | Chandrasekaran | Nov 2007 | B2 |
7301785 | Yasumura | Nov 2007 | B2 |
7312686 | Bruno | Dec 2007 | B2 |
7321283 | Mehrotra et al. | Jan 2008 | B2 |
7332992 | Iwai | Feb 2008 | B2 |
7339208 | Brar et al. | Mar 2008 | B2 |
7339801 | Yasumura | Mar 2008 | B2 |
7348612 | Sriram et al. | Mar 2008 | B2 |
7362592 | Yang et al. | Apr 2008 | B2 |
7362593 | Yang et al. | Apr 2008 | B2 |
7375607 | Lee et al. | May 2008 | B2 |
7385375 | Rozman | Jun 2008 | B2 |
7386404 | Cargonja et al. | Jun 2008 | B2 |
7393247 | Yu et al. | Jul 2008 | B1 |
7417875 | Chandrasekaran et al. | Aug 2008 | B2 |
7427910 | Mehrotra et al. | Sep 2008 | B2 |
7431862 | Mehrotra et al. | Oct 2008 | B2 |
7439556 | Brar et al. | Oct 2008 | B2 |
7439557 | Brar et al. | Oct 2008 | B2 |
7446512 | Nishihara et al. | Nov 2008 | B2 |
7447049 | Garner et al. | Nov 2008 | B2 |
7453709 | Park et al. | Nov 2008 | B2 |
7462891 | Brar et al. | Dec 2008 | B2 |
7468649 | Chandrasekaran | Dec 2008 | B2 |
7489225 | Dadafshar | Feb 2009 | B2 |
7554430 | Mehrotra et al. | Jun 2009 | B2 |
7558037 | Gong et al. | Jul 2009 | B1 |
7567445 | Coulson et al. | Jul 2009 | B2 |
7626370 | Mei et al. | Dec 2009 | B1 |
7630219 | Lee | Dec 2009 | B2 |
7633369 | Chandrasekaran et al. | Dec 2009 | B2 |
7663183 | Brar et al. | Feb 2010 | B2 |
7667986 | Artusi et al. | Feb 2010 | B2 |
7675758 | Artusi et al. | Mar 2010 | B2 |
7675759 | Artusi et al. | Mar 2010 | B2 |
7675764 | Chandrasekaran et al. | Mar 2010 | B2 |
7715217 | Manabe et al. | May 2010 | B2 |
7733679 | Luger et al. | Jun 2010 | B2 |
7746041 | Xu et al. | Jun 2010 | B2 |
7778050 | Yamashita | Aug 2010 | B2 |
7778051 | Yang | Aug 2010 | B2 |
7787264 | Yang | Aug 2010 | B2 |
7791903 | Zhang | Sep 2010 | B2 |
7795849 | Sohma | Sep 2010 | B2 |
7813101 | Morikawa | Oct 2010 | B2 |
7847535 | Meynard et al. | Dec 2010 | B2 |
7876191 | Chandrasekaran et al. | Jan 2011 | B2 |
7889517 | Artusi et al. | Feb 2011 | B2 |
7889521 | Hsu | Feb 2011 | B2 |
7906941 | Jayaraman et al. | Mar 2011 | B2 |
7940035 | Yang | May 2011 | B2 |
7965528 | Yang et al. | Jun 2011 | B2 |
7983063 | Lu et al. | Jul 2011 | B2 |
8004112 | Koga et al. | Aug 2011 | B2 |
8125205 | Chandrasekaran et al. | Feb 2012 | B2 |
8134443 | Chandrasekaran et al. | Mar 2012 | B2 |
8179699 | Tumminaro et al. | May 2012 | B2 |
8278889 | Tataeishi | Oct 2012 | B2 |
8638578 | Zhang | Jan 2014 | B2 |
8643222 | Brinlee et al. | Feb 2014 | B2 |
20010020886 | Matsumoto et al. | Sep 2001 | A1 |
20010024373 | Cuk | Sep 2001 | A1 |
20010055216 | Shirato | Dec 2001 | A1 |
20020044463 | Bontempo et al. | Apr 2002 | A1 |
20020057080 | Telefus et al. | May 2002 | A1 |
20020071295 | Nishikawa | Jun 2002 | A1 |
20020101741 | Brkovic | Aug 2002 | A1 |
20020110005 | Mao et al. | Aug 2002 | A1 |
20020114172 | Webb et al. | Aug 2002 | A1 |
20020145888 | Yoshinaga et al. | Oct 2002 | A1 |
20020167385 | Ackermann | Nov 2002 | A1 |
20020176262 | Tripathi et al. | Nov 2002 | A1 |
20030026115 | Miyazaki | Feb 2003 | A1 |
20030030422 | Sula | Feb 2003 | A1 |
20030063483 | Carsten | Apr 2003 | A1 |
20030063484 | Carsten | Apr 2003 | A1 |
20030076079 | Alcantar et al. | Apr 2003 | A1 |
20030086279 | Bourdillon | May 2003 | A1 |
20030197585 | Chandrasekaran et al. | Oct 2003 | A1 |
20030198067 | Sun et al. | Oct 2003 | A1 |
20040017689 | Zhang et al. | Jan 2004 | A1 |
20040032754 | Yang | Feb 2004 | A1 |
20040034555 | Dismukes et al. | Feb 2004 | A1 |
20040064621 | Dougherty | Apr 2004 | A1 |
20040148047 | Dismukes et al. | Jul 2004 | A1 |
20040156220 | Kim et al. | Aug 2004 | A1 |
20040196672 | Amei | Oct 2004 | A1 |
20040200631 | Chen | Oct 2004 | A1 |
20040217794 | Strysko | Nov 2004 | A1 |
20040257095 | Yang | Dec 2004 | A1 |
20050024179 | Chandrasekaran et al. | Feb 2005 | A1 |
20050046404 | Uusitalo | Mar 2005 | A1 |
20050052224 | Yang et al. | Mar 2005 | A1 |
20050052886 | Yang | Mar 2005 | A1 |
20050207189 | Chen | Sep 2005 | A1 |
20050245658 | Mehrotra et al. | Nov 2005 | A1 |
20050254266 | Jitaru | Nov 2005 | A1 |
20050254268 | Reinhard | Nov 2005 | A1 |
20050281058 | Batarseh et al. | Dec 2005 | A1 |
20050286270 | Petkov et al. | Dec 2005 | A1 |
20060006975 | Jitaru et al. | Jan 2006 | A1 |
20060006976 | Bruno | Jan 2006 | A1 |
20060007713 | Brown | Jan 2006 | A1 |
20060018136 | Takahashi | Jan 2006 | A1 |
20060038549 | Mehrotra et al. | Feb 2006 | A1 |
20060038649 | Mehrotra et al. | Feb 2006 | A1 |
20060038650 | Mehrotra et al. | Feb 2006 | A1 |
20060044845 | Fahlenkamp et al. | Mar 2006 | A1 |
20060091430 | Sriram et al. | May 2006 | A1 |
20060109698 | Qu | May 2006 | A1 |
20060187684 | Chandrasekaran et al. | Aug 2006 | A1 |
20060197510 | Chandrasekaran | Sep 2006 | A1 |
20060198173 | Rozman | Sep 2006 | A1 |
20060226477 | Brar et al. | Oct 2006 | A1 |
20060226478 | Brar et al. | Oct 2006 | A1 |
20060227576 | Yasumura | Oct 2006 | A1 |
20060237968 | Chandrasekaran | Oct 2006 | A1 |
20060255360 | Brar et al. | Nov 2006 | A1 |
20060271315 | Cargonja et al. | Nov 2006 | A1 |
20070007945 | King et al. | Jan 2007 | A1 |
20070010298 | Chang | Jan 2007 | A1 |
20070019356 | Morikawa | Jan 2007 | A1 |
20070025124 | Hansson | Feb 2007 | A1 |
20070030717 | Luger et al. | Feb 2007 | A1 |
20070041224 | Moyse et al. | Feb 2007 | A1 |
20070045765 | Brar et al. | Mar 2007 | A1 |
20070058402 | Shekhawat et al. | Mar 2007 | A1 |
20070069286 | Brar et al. | Mar 2007 | A1 |
20070114979 | Chandrasekaran | May 2007 | A1 |
20070120953 | Koga et al. | May 2007 | A1 |
20070121351 | Zhang et al. | May 2007 | A1 |
20070159857 | Lee | Jul 2007 | A1 |
20070206523 | Huynh et al. | Sep 2007 | A1 |
20070222463 | Qahouq et al. | Sep 2007 | A1 |
20070241721 | Weinstein et al. | Oct 2007 | A1 |
20070274106 | Coulson et al. | Nov 2007 | A1 |
20070274107 | Garner et al. | Nov 2007 | A1 |
20070296028 | Brar et al. | Dec 2007 | A1 |
20070296383 | Xu | Dec 2007 | A1 |
20070298559 | Brar et al. | Dec 2007 | A1 |
20070298564 | Brar et al. | Dec 2007 | A1 |
20080012423 | Mimran | Jan 2008 | A1 |
20080024094 | Nishihara et al. | Jan 2008 | A1 |
20080024259 | Chandrasekaran et al. | Jan 2008 | A1 |
20080031021 | Ros et al. | Feb 2008 | A1 |
20080037294 | Indika de Silva et al. | Feb 2008 | A1 |
20080043503 | Yang | Feb 2008 | A1 |
20080054874 | Chandrasekaran et al. | Mar 2008 | A1 |
20080080219 | Sohma | Apr 2008 | A1 |
20080111657 | Mehrotra et al. | May 2008 | A1 |
20080130321 | Artusi et al. | Jun 2008 | A1 |
20080130322 | Artusi et al. | Jun 2008 | A1 |
20080137381 | Beasley | Jun 2008 | A1 |
20080150666 | Chandrasekaran et al. | Jun 2008 | A1 |
20080175026 | Yang | Jul 2008 | A1 |
20080205104 | Lev et al. | Aug 2008 | A1 |
20080224812 | Chandrasekaran | Sep 2008 | A1 |
20080232141 | Artusi et al. | Sep 2008 | A1 |
20080298106 | Tateishi | Dec 2008 | A1 |
20080310190 | Chandrasekaran et al. | Dec 2008 | A1 |
20080315852 | Jayaraman et al. | Dec 2008 | A1 |
20080316779 | Jayaraman et al. | Dec 2008 | A1 |
20090002054 | Tsunoda et al. | Jan 2009 | A1 |
20090027926 | Yang et al. | Jan 2009 | A1 |
20090046486 | Lu et al. | Feb 2009 | A1 |
20090097290 | Chandrasekaran | Apr 2009 | A1 |
20090109711 | Hsu | Apr 2009 | A1 |
20090257250 | Liu | Oct 2009 | A1 |
20090273957 | Feldtkeller | Nov 2009 | A1 |
20090284994 | Lin et al. | Nov 2009 | A1 |
20090289557 | Itoh et al. | Nov 2009 | A1 |
20090310388 | Yang | Dec 2009 | A1 |
20090315530 | Baranwal | Dec 2009 | A1 |
20100091522 | Chandrasekaran et al. | Apr 2010 | A1 |
20100123486 | Berghegger | May 2010 | A1 |
20100149838 | Artusi et al. | Jun 2010 | A1 |
20100164443 | Tumminaro et al. | Jul 2010 | A1 |
20100182806 | Garrity et al. | Jul 2010 | A1 |
20100188876 | Garrity et al. | Jul 2010 | A1 |
20100202165 | Zheng et al. | Aug 2010 | A1 |
20100213989 | Nakatake | Aug 2010 | A1 |
20100254168 | Chandrasekaran | Oct 2010 | A1 |
20100321958 | Brinlee et al. | Dec 2010 | A1 |
20100321964 | Brinlee et al. | Dec 2010 | A1 |
20110038179 | Zhang | Feb 2011 | A1 |
20110089917 | Chen et al. | Apr 2011 | A1 |
20110134664 | Berghegger | Jun 2011 | A1 |
20110149607 | Jungreis et al. | Jun 2011 | A1 |
20110182089 | Berghegger | Jul 2011 | A1 |
20110239008 | Lam et al. | Sep 2011 | A1 |
20110241738 | Tamaoka | Oct 2011 | A1 |
20110305047 | Jungreis et al. | Dec 2011 | A1 |
20120243271 | Berghegger | Sep 2012 | A1 |
20120294048 | Brinlee | Nov 2012 | A1 |
Number | Date | Country |
---|---|---|
101141099 | Mar 2008 | CN |
101202509 | Jun 2008 | CN |
201252294 | Jun 2009 | CN |
10310361 | Sep 2004 | DE |
0 665 634 | Jan 1994 | EP |
57097361 | Jun 1982 | JP |
3-215911 | Sep 1991 | JP |
2000-68132 | Mar 2000 | JP |
8700991 | Feb 1987 | WO |
WO 2010083511 | Jul 2010 | WO |
WO 2010083514 | Jul 2010 | WO |
WO 2010114914 | Oct 2010 | WO |
2011116225 | Sep 2011 | WO |
Entry |
---|
Ajram, S., et al., “Ultrahigh Frequency DC-to-DC Converters Using GaAs Power Switches,” IEEE Transactions on Power Electronics, Sep. 2001, pp. 594-602, vol. 16, No. 5, IEEE, Los Alamitos, CA. |
“AN100: Application Note using Lx100 Family of High Performance N-Ch JFET Transistors,” AN100.Rev 1.01, Sep. 2003, 5 pp., Lovoltech, Inc., Santa Clara, CA. |
“AN101A: Gate Drive Network for a Power JFET,” AN101A.Rev 1.2, Nov. 2003, 2 pp., Lovoltech, Inc., Santa Clara, CA. |
“AN108: Applications Note: How to Use Power JFETs® and MOSFETs Interchangeably in Low-Side Applications,” Rev. 1.0.1, Feb. 14, 2005, 4 pp., Lovoltech, Inc., Santa Clara, CA. |
Balogh, L., et al., “Power-Factor Correction with Interleaved Boost Converters in Continuous-Inductor-Current Mode,” IEEE Proceedings of APEC, pp. 168-174, 1993, IEEE, Los Alamitos, CA. |
Biernacki, J., et al., “Radio Frequency DC-DC Flyback Converter,” Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, Aug. 8-11, 2000, pp. 94-97, vol. 1, IEEE, Los Alamitos, CA. |
Chen, W., et al., “Design of High Efficiency, Low Profile, Low Voltage Converter with Integrated Magnetics,” Proceedings of 1997 IEEE Applied Power Electronics Conference (APEC '97), 1997, pp. 911-917, IEEE, Los Alamitos, CA. |
Chen, W. et al., “Integrated Planar Inductor Scheme for Multi-module Interleaved Quasi-Square-Wave (QSW) DC/DC Converter,” 30th Annual IEEE Power Electronics Specialists Conference (PESC '99), 1999, pp. 759-762, vol. 2, IEEE, Los Alamitos, CA. |
Chhawchharia, P., et al., “On the Reduction of Component Count in Switched Capacitor DC/DC Convertors,” Hong Kong Polytechnic University, IEEE, 1997, Hung Hom, Kowloon, Hong King, pp. 1395-1401. |
Curtis, K., “Advances in Microcontroller Peripherals Facilitate Current-Mode for Digital Power Supplies,” Digital Power Forum '06, 4 pp., Sep. 2006, Darnell Group, Richardson, TX. |
Eisenbeiser, K., et al., “Manufacturable GaAs VFET for Power Switching Applications,” IEEE Electron Device Letters, Apr. 2000, pp. 144-145, vol. 21, No. 4, IEEE. |
Gaye, M., et al., “A 50-100MHz 5V to -5V, 1W Cuk Converter Using Gallium Arsenide Power Switches,” ISCAS 2000—IEEE International Symposium on Circuits and Systems, May 28-31, 2000, pp. I-264-I-267, vol. 1, IEEE, Geneva, Switzerland. |
Goldberg, A.F., et al., “Issues Related to 1-10-MHz Transformer Design,” IEEE Transactions on Power Electronics, Jan. 1989, pp. 113-123, vol. 4, No. 1, IEEE, Los Alamitos, CA. |
Goldberg, A.F., et al., “Finite-Element Analysis of Copper Loss in 1-10-MHz Transformers,” IEEE Transactions on Power Electronics, Apr. 1989, pp. 157-167, vol. 4, No. 2, IEEE, Los Alamitos, CA. |
Jitaru, I.D., et al., “Quasi-Integrated Magnetic an Avenue for Higher Power Density and Efficiency in Power Converters,” 12th Annual Applied Power Electronics Conference and Exposition, Feb. 23-27, 1997, pp. 395-402, vol. 1, IEEE, Los Alamitos, CA. |
Kollman, R., et al., “10 MHz PWM Converters with GaAs VFETs,” IEEE 11th Annual Applied Power Electronics Conference and Exposition, Mar. 1996, pp. 264-269, vol. 1, IEEE. |
Kuwabara, K., et al., “Switched-Capacitor DC-DC Converters,” Fujitsu Limited, IEEE, 1988, Kawasaki, Japan, pp. 213-218. |
Lee, P.-W., et al., “Steady-State Analysis of an Interleaved Boost Converter with Coupled Inductors,” IEEE Transactions on Industrial Electronics, Aug. 2000, pp. 787-795, vol. 47, No. 4, IEEE, Los Alamitos, CA. |
Lenk, R., “Introduction to the Tapped Buck Converter,” PCIM 2000, HFPC 2000 Proceedings, Oct. 2000, pp. 155-166. |
Liu, W., “Fundamentals of III-V Devices: HBTs, MESFETs, and HFETs/HEMTs,” §5-5: Modulation Doping, 1999, pp. 323-330, John Wiley & Sons, New York, NY. |
Maksimović, D., et al., “Switching Converters with Wide DC Conversion Range,” IEEE Transactions on Power Electronics, Jan. 1991, pp. 151-157, vol. 6, No. 1, IEEE, Los Alamitos, CA. |
Maxim, Application Note 725, www.maxim-ic.com/an725, Maxim Integrated Products, Nov. 29, 2001, 8 pages. |
Middlebrook, R.D., “Transformerless DC-to-DC Converters with Large Conversion Ratios,” IEEE Transactions on Power Electronics, Oct. 1988, pp. 484-488, vol. 3, No. 4, IEEE, Los Alamitos, CA. |
Miwa, B.A., et al., “High Efficiency Power Factor Correction Using Interleaving Techniques,” IEEE Proceedings of APEC, 1992, pp. 557-568, IEEE, Los Alamitos, CA. |
National Semiconductor Corporation, “LMC7660 Switched Capacitor Voltage Converter,” www.national.com, Apr. 1997, 12 pages. |
National Semiconductor Corporation, “LM2665 Switched Capacitor Voltage Converter,” www.national.com, Sep. 2005, 9 pages. |
Nguyen, L.D., et al., “Ultra-High-Speed Modulation-Doped Field-Effect Transistors: A Tutorial Review,” Proceedings of the IEEE, Apr. 1992, pp. 494-518, vol. 80, No. 4, IEEE. |
Niemela, V.A., et al., “Comparison of GaAs and Silicon Synchronous Rectifiers in a 3.3V Out, 50W DC-DC Converter,” 27th Annual IEEE Power Electronics Specialists Conference, Jun. 1996, pp. 861-867, vol. 1, IEEE. |
Ninomiya, T., et al., “Static and Dynamic Analysis of Zero-Voltage-Switched Half-Bridge Converter with PWM Control,” Proceedings of 1991 IEEE Power Electronics Specialists Conference (PESC '91), 1991, pp. 230-237, IEEE, Los Alamitos, CA. |
O'Meara, K., “A New Output Rectifier Configuration Optimized for High Frequency Operation,” Proceedings of 1991 High Frequency Power Conversion (HFPC '91) Conference, Jun. 1991, pp. 219-225, Toronto, CA. |
Peng, C., et al., “A New Efficient High Frequency Rectifier Circuit,” Proceedings of 1991 High Frequency Power Conversion (HFPC '91) Conference, Jun. 1991, pp. 236-243, Toronto, CA. |
Pietkiewicz, A., et al. “Coupled-Inductor Current-Doubler Topology in Phase-Shifted Full-Bridge DC-DC Converter,” 20th International Telecommunications Energy Conference (INTELEC), Oct. 1998, pp. 41-48, IEEE, Los Alamitos, CA. |
Plumton, D.L., et al., “A Low On-Resistance High-Current GaAs Power VFET,” IEEE Electron Device Letters, Apr. 1995, pp. 142-144, vol. 16, No. 4, IEEE. |
Rajeev, M., “An Input Current Shaper with Boost and Flyback Converter Using Integrated Magnetics,” Power Electronics and Drive Systems, 5th International Conference on Power Electronics and Drive Systems 2003, Nov. 17-20, 2003, pp. 327-331, vol. 1, IEEE, Los Alamitos, CA. |
Rico, M., et al., “Static and Dynamic Modeling of Tapped-Inductor DC-to-DC Converters,” 1987, pp. 281-288, IEEE, Los Alamitos, CA. |
Severns, R., “Circuit Reinvention in Power Electronics and Identification of Prior Work,” Proceedings of 1997 IEEE Applied Power Electronics Conference (APEC '97), 1997, pp. 3-9, IEEE, Los Alamitos, CA. |
Severns, R., “Circuit Reinvention in Power Electronics and Identification of Prior Work,” IEEE Transactions on Power Electronics, Jan. 2001, pp. 1-7, vol. 16, No. 1, IEEE, Los Alamitos, CA. |
Sun, J., et al., “Unified Analysis of Half-Bridge Converters with Current-Doubler Rectifier,” Proceedings of 2001 IEEE Applied Power Electronics Conference, 2001, pp. 514-520, IEEE, Los Alamitos, CA. |
Sun, J., et al., “An Improved Current-Doubler Rectifier with Integrated Magnetics,” 17th Annual Applied Power Electronics Conference and Exposition (APEC), 2002, pp. 831-837, vol. 2, IEEE, Dallas, TX. |
Texas Instruments Incorporated, “LT1054, LT1054Y Switched-Capacitor Voltage Converters With Regulators,” SLVS033C, Feb. 1990—Revised Jul. 1998, 25 pages. |
Thaker, M., et al., “Adaptive/Intelligent Control and Power Management Reduce Power Dissipation and Consumption,” Digital Power Forum '06, 11 pp., Sep. 2006, Darnell Group, Richardson, TX. |
Vallamkonda, S., “Limitations of Switching Voltage Regulators,” A Thesis in Electrical Engineering, Texas Tech University, May 2004, 89 pages. |
Wei, J., et al., “Comparison of Three Topology Candidates for 12V VRM,” IEEE APEC, 2001, pp. 245-251, IEEE, Los Alamitos, CA. |
Weitzel, C.E., “RF Power Devices for Wireless Communications,” 2002 IEEE MTT-S CDROM, 2002, pp. 285-288, paper TU4B-1, IEEE, Los Alamitos, CA. |
Williams, R., “Modern GaAs Processing Methods,” 1990, pp. 66-67, Artech House, Inc., Norwood, MA. |
Wong, P.-L., et al., “Investigating Coupling Inductors in the Interleaving QSW VRM,” 15th Annual Applied Power Electronics Conference and Exposition (APEC 2000), Feb. 2000, pp. 973-978, vol. 2, IEEE, Los Alamitos, CA. |
Xu, M., et al., “Voltage Divider and its Application in the Two-stage Power Architecture,” Center for Power Electronics Systems, Virginia Polytechnic Institute and State University, IEEE, 2006, Blacksburg, Virginia, pp. 499-505. |
Xu, P., et al., “Design and Performance Evaluation of Multi-Channel Interleaved Quasi-Square-Wave Buck Voltage Regulator Module,” HFPC 2000 Proceedings, Oct. 2000, pp. 82-88. |
Xu, P., et al., “Design of 48 V Voltage Regulator Modules with a Novel Integrated Magnetics,” IEEE Transactions on Power Electronics, Nov. 2002, pp. 990-998, vol. 17, No. 6, IEEE, Los Alamitos, CA. |
Xu, P., et al., “A Family of Novel Interleaved DC/DC Converters for Low-Voltage High-Current Voltage Regulator Module Applications,” IEEE Power Electronics Specialists Conference, Jun. 2001, pp. 1507-1511, IEEE, Los Alamitos, CA. |
Xu, P., et al., “A Novel Integrated Current Doubler Rectifier,” IEEE 2000 Applied Power Electronics Conference, Mar. 2000, pp. 735-740, IEEE, Los Alamitos, CA. |
Yan, L, et al., “Integrated Magnetic Full Wave Converter with Flexible Output Inductor,” 17th Annual Applied Power Electronics Conference and Exposition (APEC), 2002, pp. 824-830, vol. 2, IEEE, Dallas, TX. |
Yan, L, et al., “Integrated Magnetic Full Wave Converter with Flexible Output Inductor,” IEEE Transactions on Power Electronics, Mar. 2003, pp. 670-678, vol. 18, No. 2, IEEE, Los Alamitos, CA. |
Zhou, X., et al., “A High Power Density, High Efficiency and Fast Transient Voltage Regulator Module with a Novel Current Sensing and Current Sharing Technique,” IEEE Applied Power Electronics Conference, Mar. 1999, pp. 289-294, IEEE, Los Alamitos, CA. |
Zhou, X., et al., “Investigation of Candidate VRM Topologies for Future Microprocessors,” IEEE Applied Power Electronics Conference, Mar. 1998, pp. 145-150, IEEE, Los Alamitos, CA. |
Freescale Semiconductor, “Design of a Digital AC/DC SMPS using the 56F8323 Device, Designer Reference Manual, 56800E 16-bit Digital Signal Controllers”, DRM074, Rev. 0, Aug. 2005 (108 pages). |
Freescale Semiconductor, “56F8323 Evaluation Module User Manual, 56F8300 16-bit Digital Signal Controllers”, MC56F8323EVMUM, Rev. 2, Jul. 2005 (72 pages). |
Freescale Semiconductor, “Implementing a Digital AC/DC Switched-Mode Power Supply using a 56F8300 Digital Signal Controller,” Application Note AN3115, Aug. 2005, 24 pp., Chandler, AZ. |
Freescale Semiconductor, “56F8323/56F8123 Data Sheet Preliminary Technical Data, 56F8300 16-bit Digital Signal Controllers,” MC56F8323 Rev. 17, Apr. 2007 (140 pages). |
Power Integrations, Inc., “TOP200-4/14 TOPSwitch® Family Three-terminal Off-line PWM Switch,” Internet Citation, http://www.datasheet4u.com/.download.php?id=311769, Jul. 1996, XP002524650, pp. 1-16. |
Bill Andreycak, Active Clamp and Reset Technique Enhances Forward Converter Performance, Oct. 1994, Texas Instruments, 19 pages. |
Ridley, R., Designing with the TL431, Switching Power Magazine, Designer Series XV, pp. 1-5, 2005. |
Number | Date | Country | |
---|---|---|---|
20110305047 A1 | Dec 2011 | US |
Number | Date | Country | |
---|---|---|---|
61314900 | Mar 2010 | US |