Hereinafter, Embodiment 1 of the invention will be described with reference to
Embodiment 1 of the invention relates to a method for restraining and controlling a tertiary harmonic current generated in a TCR-based static var compensator (SVC) in which the magnitude of a reactor current is phase-controlled by a thyristor converter, thereby adjusting the magnitude of reactive power. It also describes an exemplary control method for a static var compensator that can minimizes a tertiary harmonic current flowing out from the SVC toward a power system because of three-phase unbalanced voltage components existing in the power system when the SVC is connected to the power system. It also describes a control method for a static var compensator that can operate stably by restraining a tertiary harmonic current flowing out from the SVC toward a power system is restrained, and by detecting a tertiary harmonic current component that flows through each phase of the SVC, correcting the phase-control angle of a thyristor converter for each phase of the SVC to reduce the unbalance in the detected tertiary harmonic current between the respective phases and thus restraining the outflow of the tertiary harmonic current toward the system, and by introducing a control circuit that corrects a nonlinear relation between the quantity of generated tertiary harmonic and the phase-control angle of the SVC.
The detailed description will follow.
In
A PT 10 that measures a bus voltage is connected to the bus 2.
A voltage signal of the bus 2 measured by the PT is inputted to a voltage sensor (VS) 100 of an SVC control unit, converted to a three-phase voltage r.m.s. value, and taken in the SVC control unit as a voltage signal VM.
In a subtraction circuit 101, the voltage signal VM is subtracted from a voltage reference value (Vref) preset by a control circuit, and the difference ΔV (=Vref−VM) is inputted to an AVR circuit 102 on the next stage.
This AVR circuit 102 is formed by a composite circuit of proportional control and integral control and serves to perform feedback control of the quantity of reactive power flowing through the SVC so that the voltage difference ΔV is constantly close to 0.
An output QA of this AVR circuit 102 is inputted to a phase-control angle calculating circuit (Gα) 103 on the next stage, which calculates a thyristor phase-control angle α of the SVC for getting a required quantity of reactive power.
In this calculation, a thyristor phase-control angle α that is necessary for outputting a desired quantity of reactive power is calculated, for example, in accordance with the equation (13.8) of R. Mohan Mathur and Rajiv K. Varma. This value α is the same and common among the three phases.
Meanwhile, currents IU, IV, IW flowing through the respective phases of the delta-connected SVC 3 are detected by CT11, 12, 13, and the magnitudes of tertiary harmonic currents of the respective phases are calculated by a current sensor (CS-U) 104a, a current sensor (CS-V) 104b and a current sensor (CS-W) 104c.
As these current sensors, for example, a circuit shown in
In the example shown in this embodiment, the SVC 3 includes a first series circuit formed by reactors 4a, 4b and the thyristor converter 7, a second series circuit formed by reactors 5a, 5b and the thyristor converter 8, and a third series circuit formed by reactors 6a, 6b and the thyristor converter 9. The first series circuit, the second series circuit and the third series circuit are delta-connected.
These tertiary current detection values IU3, IV3, IW3 are inputted to an average value circuit (CS-AV) 105, which calculates an average value of the three phases, that is, an average value IAV3.
Current difference calculating circuits (combining circuits) 106a, 106b, 106c calculate the difference between the tertiary harmonic current values IU3, IV3, IW3 of the respective phases and the average harmonic current value IAV3 in accordance with the following equations.
ΔAU3=IU3−IAV3
ΔAV3=IV3−IAV3
ΔAW3=IW3−IAV3
The relation between the tertiary harmonic current generated by the SVC 3 and the thyristor phase-control angle α is as shown in
During a period when α<α0 holds, the tertiary harmonic current increases as α increases.
During a period when α>α0 holds, the tertiary harmonic current decreases as α increases.
From
As is clear from
To this end, the tertiary harmonic difference signals ΔIU3, ΔIV3, ΔIW3 are inputted to multiplying circuits 107a, 107b, 107c to calculate the following equations.
ΔIUA=F(α)*ΔIU3
ΔIVA=F(α)*ΔIV3
ΔIWA=F(α)*ΔIW3
F(α) is a linearization function to linearize the sensitivity coefficient K3 shown in
The current difference signals ΔIUA, ΔIVA, ΔIWA are inputted to correction angle calculating circuits (PHC-U, PHC-V, PHC-W) 108a, 108b, 108c, which output phase-control angle correction signals ΔαU, ΔαV, ΔαW. These correction angle calculating circuits include a combination of a proportional control function and an integral control function, and serve to correct the thyristor phase-control angle of each phase by feedback control so that ΔIUA, ΔIVA, ΔIWA become closer to 0.
The phase-control angle correction signals ΔαU, ΔαV, ΔαW are inputted to combining circuits 110a, 110b, 110c to correct the phase-control angles of the respective phases by using the following equations. Thus, thyristor phase-control angles αU, αV, αW for the respective phases are acquired.
αU=αA+ΔαU
αV=αA+ΔαV
αW=αA+ΔαW
In these equations, αA is the thyristor phase-control angle that is common among the respective phases, acquired by the equation (3.8) of R. Mohan Mathur and Rajiv K. Varma.
The thyristor phase-control angles αU, αV, αW acquired by the above equations are inputted to gate pulse generating circuits (GPG-U, GPG-V, GPG-W) 111a, 111b, 111c on the next stage, which provide gate pulses corresponding to the thyristor phase-control angles αU, αV, αW to the thyristor converters 7, 8, 9, thus controlling the thyristor converters for each phase.
In such a configuration, when an unbalanced voltage exists on the bus 2, the SVC performs control to equalize the magnitudes of the tertiary harmonic currents of the three phases generated at the time of thyristor control. These tertiary harmonic currents are offset within the delta connection of the SVC and the tertiary harmonic current flowing out toward the system are restrained. Also, as the linearization function F(α) is introduced into the control, the instability of control can be eliminated and stable control can be made.
In this manner, according to Embodiment 1 of the invention, even when the voltage on the bus 2 has an unbalanced component, the tertiary harmonic current flowing out of the SVC 3 toward the system can be minimized. The voltage distortion of the power system can be reduced and the tertiary harmonic filter is no longer necessary.
While the presently preferred embodiments of the present invention have been shown and described, it is to be understood that these disclosures are for the purpose of illustration and that various changes and modifications may be made without departing from the scope of the invention as set forth in the appended claims.
Number | Date | Country | Kind |
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2006-178153 | Jun 2006 | JP | national |