Patent Application
20160091960
The present disclosure relates generally to control systems. More specifically, the present embodiments relate to control systems for reducing the current transients occurring between a processor and a power supply.
Modern computing devices have become more advanced over time while also becoming more compact. The limited space within various computing devices has led to a demand for power supplies that are small enough to be easily transported through the daily routine of a typical consumer, while being large enough to manage the sometimes unpredictable power demands of a computing device. In computing devices such as laptops, the laptop can often be designed to be as portable as a cellular phone while having the processing power of a desktop computer. Additionally, the laptop can include a battery for providing the energy needed for performing various tasks while also enabling the laptop to be operable almost anywhere. However, as the processing power of laptops and other portable devices increases, typically the size of the power supply also increases in order to accommodate increasing current demands. Unfortunately, bulkier power supplies can be expensive and inconvenient to carry around, thereby ruining the purpose of designing a computing device for portability.
This paper describes various embodiments that relate to control systems for reducing demand currents from a power supply. Specifically, the embodiments relate to throttling a processor using a control system to reduce the current demanded by the processor from a power supply.
In some embodiments, a controller is set forth. The controller can be used to reduce a frequency and/or a peak current value of a transient current induced in an input current supplied, by a power supply, to a computing system having at least one processor. The controller can include an input current filter operable at a first frequency and arranged to sample the input current. The controller can further include a control effort (CE) generator coupled to the input current filter that is operable at a second frequency that is less than the first frequency and uses a sampled input current to provide a CE signal to the at least one processor that reduces the frequency and/or the peak current value of the transient current by throttling at least one processor by reducing a performance (p) state of at least one processor.
In other embodiments, a system is set forth for temporarily reducing a current demand of at least one processor. The system can include a sample generator configured to sample an input current according to a first time domain, and output a current sample from a sample buffer of the sample generator according to a second time domain. The system can further include a process limiter operatively coupled to the sample generator and configured to provide a CE signal according to a signal delay to limit an activity of the at least one processor and delay an increase in the activity of the at least one processor.
In yet other embodiments, a method is set forth for temporarily limiting a power consumption of a processor in response to an increased current demand of the processor from a power supply. The method can include receiving a sampled input current from a sample storage. The sample storage can include an input and output contemporaneously operable at different frequencies, and sample an input current being transmitted between the processor and power supply. The sample storage can further output the sampled input current for comparison to a reference value associated with the power supply. The method can also include a step of limiting the power consumption of the processor when the sampled input current reaches at least the reference value.
Other aspects and advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings which illustrate, by way of example, the principles of the described embodiments.
The described embodiments may be better understood by reference to the following description and the accompanying drawings. Additionally, advantages of the described embodiments may be better understood by reference to the following description and accompanying drawings.
Representative applications of methods and apparatus according to the present application are described in this section. These examples are being provided solely to add context and aid in the understanding of the described embodiments. It will thus be apparent to one skilled in the art that the described embodiments may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order to avoid unnecessarily obscuring the described embodiments. Other applications are possible, such that the following examples should not be taken as limiting.
In the following detailed description, references are made to the accompanying drawings, which form a part of the description and in which are shown, by way of illustration, specific embodiments in accordance with the described embodiments. Although these embodiments are described in sufficient detail to enable one skilled in the art to practice the described embodiments, it is understood that these examples are not limiting; such that other embodiments may be used, and changes may be made without departing from the spirit and scope of the described embodiments.
The embodiments discussed herein relate to control systems configured to reduce current transients occurring between a system and a power supply. Current transients can be the result of an increase in workload of the system and can cause the power supply to operate out of a specification of which the power supply was designed. Over time, this can eventually cause the power supply to malfunction. The current transients can have a frequency defining how often the current transients spike above or exceed a peak current threshold associated with the specification of the power supply. In order to mitigate potential harm to the power supply, the control system is configured to reduce the frequency and amplitude of these current transients. In this way, although the power supply may occasionally operate out of specification, the amount of time the power supply will be operating out of specification will be reduced. The control system accomplishes this by removing or limiting a workload and/or performance state of the system, thus causing the system to demand less current from the power supply.
The control system can be configured to sample an input current from the power supply. In order to perform the sampling, a sampling filter can be provided in the control system and to be operable in a hybrid domain. In this way, the sampling can occur at a frequency that is higher than a frequency that the samples are output from a buffer of the sampling filter. For example, the sampling can be performed at 10 kilohertz and the outputting of samples from the buffer can be performed at 1 kilohertz. Once in the buffer, the current samples can be filtered according to the operational parameters of the sampling filter. For example, the sampling filter can be configured to not filter the current samples in the buffer as long as the current samples are increasing with respect to time. Alternatively, when the current samples in the buffer are decreasing with respect to time, a single pole filter can be applied to the current samples in order to differentiate between current spikes increasing in peak amplitude, and current spikes decreasing in peak amplitude. In this way, the control system will filter spikes in current that are not indicative of a potentially detrimental transient current. Thereafter, buffered current samples can be output from the buffer according to an output frequency of the sampling filter.
Current samples outputted from the buffer can be provided to an arithmetic operator of the control system. The arithmetic operator can include a comparator configured to compare the current samples to a reference current value associated with the power supply. The reference current value can define a current threshold of the control system. Additionally, the current threshold can correspond to a maximum current specification for the power supply. When a current sample received by the comparator is greater than the reference current value (if a difference between the current sample and the reference current value is a positive number (i.e. an error value)), a control effort signal can be generated by a compensator of the control system, which may be used to throttle the system and reduce a current performance state of the system. The compensator can perform a proportional, integral, and/or derivative operation on an error signal, which is a difference between the reference current value and the current sample, and may come from an output of the arithmetic operator. In this way, the generation of the control effort signal can be based on the result of the operations performed on the error signal. The control effort signal can also be based on a limiter, which can limit a magnitude of the control effort signal, thereby limiting the magnitude of the resulting throttling signal. In this way, because the removal and release of performance states can be based on the magnitude of the throttling signal, the limiter acts limit the range or number of performance states that the system can transition in and out of The limiter can communicate with a memory configured to store a limit or range defining the number of performance states that can be released to or removed from the system. For example, the limiter can receive an output from the compensator and limit the output to a value or range of values in order to ensure that certain performance states are not removed from the system. In some embodiments, the magnitude of the control effort signal can be associated with one or more performance state values of a lookup table stored in the memory. Therefore, the limiter can limit the number of performance state values that the control effort signal can correspond to in the lookup table. The control effort signal can also be provided to the system according to a release filter. The release filter can be configured to slow the decay of the output of the control effort signal in order to prevent frequent throttling of the system. However, in some embodiments, the release filter and limiter can be optional components of the control system.
These and other embodiments are discussed below with reference to
After the filtered sample 322 is output from the input filter 318, an arithmetic operator 316 can be configured to receive the filtered sample 322. The arithmetic operator 316 can comprise a comparator configured to compare the filtered sample 322 to a reference current value 310. The reference current value 310 can be a value stored in a memory 312 of the PMU 208 or of the computing device 202 that the PMU 208 is operable within. In some embodiments, the reference current value 310 is generated as a result of the power supply 206 initially being plugged into the computing device 202. In response, the PMU 208 or other system of the computing device 202 can determine the type of power supply 206 that is plugged in and generate the reference current value 310 according to the type of power supply 206. In other embodiments, the power supply 206 can provide a reference signal to the PMU 208 or computing device 202 that identifies the power supply 206 and/or indicates the appropriate reference current value 310 to be provided for comparing to the buffered current samples. The reference current value 310 can be updatable by the PMU 208, computing device 202, and/or the external power supply 206. For example, the reference current value 310 can correspond to a peak current threshold for a particular external power supply 206. The PMU 208 can store one or more reference current values 310 that correspond to one or more external power supplies 206 that can be coupled to the computing device 202. The PMU 208 can supply one or more reference current values 310 to the arithmetic operator 316, which can be configured to generate an error signal 308 based on a difference or comparison between the reference current value 310 and a buffered current sample. Additionally, the reference current value 310 can be updated through a software and/or a firmware update of the computing device 202 or PMU 208. In this way, as new power adapters are designed, the PMU 208 can be configured to operate with the new power adapters. Additionally, in some embodiments, when a power adapter is attached to the computing device 202, the reference current value 310 can be provided by the power adapter to the PMU 208. Such an embodiment allows the PMU 208 to receive different reference current values 310 from different power adapters.
The arithmetic operator 316 can be configured to perform a logical operation according to a comparator included in the arithmetic operator 316. The logical operation can involve determining whether the reference current value 310 is greater than, equal to, or less than the filtered sample 322. The result of the logical operation can be included in the output error signal 308. The arithmetic operator 316 can also be configured to perform a mathematical operation on the filtered sample 322 and the reference current value 310. For example, in some embodiments, the filtered sample 322 can be subtracted from the reference current value 310 and the difference can be included in the error signal 308. Additionally, the filtered sample 322 and the reference current value 310 can be added, multiplied, divided, or otherwise combined through an arithmetic operation in order to gauge how close to or above a peak current threshold the external power supply 206 is operating. In some embodiments, the error signal 308 is only output when the filtered sample 322 is equal to or greater than the reference current value 310. In other embodiments, the error signal 308 is also output when the filtered sample 322 is less than the reference current value 310, however, in such an instance the error signal 308 may not cause a throttling of the CPU 210 and/or GPU 212.
The PMU 208 can include a control effort (CE) generator 324 having a compensator 302, and optionally a limiter 304 and delayed release filter 306. The control effort generator 324 may receive one or more input signals (e.g., the error signal 308 from the arithmetic operator 316), and may output a control effort signal, which may be used to throttle the system. The compensator 302 for conditioning one or more input signals being input into the compensator 302. For example, in some embodiments, the compensator 302 is an integral compensator that can integrate one or more input signals (e.g., error signals 308) provided to the compensator 302. Furthermore, the compensator 302 can be a proportional, integral, and/or derivative compensator 302, or any combination thereof. For example, the compensator 302 can be configured to multiply one or more error signals 308 by a gain value and integrate the resulting multiplied one or more error signals when the compensator 302 is configured as a proportional integral controller. Thereafter, the CE generator 324 can output the CE signal 314 based on the output of the compensator 302, which may be used to throttle the system (e.g., CPU 210 and/or GPU 212) based on a result of the computations performed by the compensator 302.
A limiter 304 can optionally be provided in the CE generator 324 for limiting the performance states that can be removed from and/or released to the CPU 210 and/or GPU 212. The operation of the limiter 304 can be based on an output of the compensator 302 and data provided in the memory 312. For example, the limiter 304 can be configured to access certain parameters in memory 312 and generate a limited CE signal 330. The limited CE signal 330 corresponds to a CE signal 314 with a magnitude that has been limited by the limiter 304. In this way, the limiter can limit which performance states can and/or cannot be removed from the CPU 210 and/or GPU 212, as further discussed herein. For example, the limiter 304 can prevent the CE signal 314 from causing all the performance states from being removed from the CPU 210 and/or GPU 212. Additionally, in some embodiments the limiter 304 can be associated with parameters including a lower limit and/or an upper limit of performance states that can or cannot be removed. Furthermore, in other embodiments, a range of performance states can be associated with the limiter 304 in order to prevent the CE signal 314 from causing performance states outside or inside of the range from being removed. The limiter 304 can also be configured to access a lookup table in memory 312 and identify a first performance state that the CE signal 314 is associated with. Thereafter, the limiter 304 can modify the CE signal 314 to be associated with a second performance state if the limiter 304 determines that the first performance state was outside of a range of performance states that can be removed from the CPU 210 and/or GPU 212.
The CE generator 324 can also optionally include a delayed release filter 306. The delayed release filter 306 can be configured to slow or otherwise limit a rate of decrease of the CE signal 314 generated by the CE generator 324, which in turn may delay the removal and/or release of performance states at the CPU 210 and/or GPU 212. During the operation of the PMU 208, a performance state may be removed and returned to the CPU 210 and/or GPU 212 multiple times. However, because frequent throttling between performance states can interfere with the performance of the CPU 210 and/or GPU 212, it can be beneficial to delay the release of performance states back to the CPU 210 and/or GPU 212 in order for the current demanded from the external power supply 206 by the CPU 210 and/or GPU 212 to remain low for a period of time. The period of delay can depend on a stored time delay constant of the delayed release filter 306. The time delay constant can be set during manufacturing of the PMU 208 or anytime thereafter by any suitable software modification such as a software update provided by the manufacturer. The delayed release filter 306 can be configured to act as a single pole filter that does not filter the CE signal 314 when the CE signal is increasing but filters the CE signal 314 when the CE signal 314 is decreasing. When the CE signal 314 is decreasing, the delayed release filter 306 can regulate the decay or decrease of the CE signal 314 in order to slow down the decay of the CE signal 314. In this way, the CE signal 314 will release one or more performance states at a later point than a decreasing CE signal 314 that is unfiltered.
The CE generator 324 can communicate with a control decision 336. The control decision 336 can be configured to receive an input that includes a resulting CE signal 332. The resulting CE signal 332 can correspond to the CE signal 314, a limited signal in instances where the CE generator 324 includes the limiter 304, and/or a delayed-release signal in instances where the CE generator 324 includes the delayed release filter 306. The control decision 336 can also be configured to output a throttling signal 326. The throttling signal 326 can in turn set a maximum performance state for one or more components of the electronic device (e.g., one or more processors such as CPU 210 and/or GPU 212. Lowering the maximum performance state (i.e., removing a performance state) of a processor may reduce or otherwise constrain the power consumed due to operation of the processor, while raising the maximum performance state (i.e., releasing a performance state) may allow the processor to operate in a manner that may consume more power. The performance states to be released or removed are based on a performance limit corresponding to an input to the control decision 336. For example, as the value of the CE signal 314 increases, the resulting throttle signal may remove additional performance states. In some instances, the number of performance states that can be removed from a component may be limited (e.g., to provide for a minimum operating level for that component). Conversely, as the value of the CE signal 314 decreases, performance states may be released back to the components such as CPU 210 and/or GPU 212. The number of performances states that may be released to a component may be limited. In some embodiments, the performance limit corresponding to a certain input value can be different depending on whether the CE signal 314 is increasing or decreasing. For example, when the CE signal 314 is increasing, a performance limit can be associated with a first CE value, and when the CE signal 314 is decreasing, the same performance limit can be associated with a second CE value that is less than the first CE value. In this way, the performance states removed when the input was above the first CE value will not be released until the input falls below both the first CE value and the second CE value. The control decision 336 can include one or more tables (e.g., a hysteresis table or lookup table) in order to perform the functions associated with the control decision 336 discussed herein.
In some embodiments, the control decision 336 is configured to order the throttling of certain processors 404 in a certain way. For example, in some embodiments control decision 336 is configured to cause the CPU 210 to be throttled before the GPU 212 is throttled. Furthermore, in some embodiments, the GPU 212 can be throttled before the CPU 210, or both the GPU 212 and the CPU 210 can be throttled contemporaneously. The throttling can be based on performance states specifically associated with either the CPU 210 or the GPU 212, or both. Therefore, one or more hysteresis tables 402 can be associated with performance states exclusively operable by the CPU 210 or the GPU 212. The control decision 336 can further be configured to provide an order for the release of performance states after one or more performance states have been removed or reduced. Moreover, the control decision 336 can be updateable by the system or manufacturer in order to adapt to new power supplies that can be designed to supply power to the various processors 404 communicatively coupled to the CE generator 324.
The method 700 of
The computing device 800 can also include user input device 804 that allows a user of the computing device 800 to interact with the computing device 800. For example, user input device 804 can take a variety of forms, such as a button, keypad, dial, touch screen, audio input interface, visual/image capture input interface, input in the form of sensor data, etc. Still further, the computing device 800 can include a display 808 (screen display) that can be controlled by processor 802 to display information to a user. Controller 810 can be used to interface with and control different equipment through equipment control bus 812. The computing device 800 can also include a network/bus interface 814 that couples to data link 816. Data link 816 can allow the computing device 800 to couple to a host computer or to accessory devices. The data link 816 can be provided over a wired connection or a wireless connection. In the case of a wireless connection, network/bus interface 814 can include a wireless transceiver.
The computing device 800 can also include a storage device 818, which can have a single disk or a plurality of disks (e.g., hard drives) and a storage management module that manages one or more partitions (also referred to herein as “logical volumes”) within the storage device 818. In some embodiments, the storage device 818 can include flash memory, semiconductor (solid state) memory or the like. Still further, the computing device 800 can include Read-Only Memory (ROM) 820 and Random Access Memory (RAM) 822. The ROM 820 can store programs, code, instructions, utilities or processes to be executed in a non-volatile manner. The RAM 822 can provide volatile data storage, and store instructions related to components of the storage management module that are configured to carry out the various techniques described herein. The computing device 800 can further include data bus 824. Data bus 824 can facilitate data and signal transfer between at least processor 802, controller 810, network interface 814, storage device 818, ROM 820, and RAM 822.
The various aspects, embodiments, implementations or features of the described embodiments can be used separately or in any combination. Various aspects of the described embodiments can be implemented by software, hardware or a combination of hardware and software. The described embodiments can also be embodied as computer readable code on a computer readable storage medium. The computer readable storage medium can be any data storage device that can store data which can thereafter be read by a computer system. Examples of the computer readable storage medium include read-only memory, random-access memory, CD-ROMs, HDDs, DVDs, magnetic tape, and optical data storage devices. The computer readable storage medium can also be distributed over network-coupled computer systems so that the computer readable code is stored and executed in a distributed fashion. In some embodiments, the computer readable storage medium can be non-transitory.
The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the described embodiments. However, it will be apparent to one skilled in the art that the specific details are not required in order to practice the described embodiments. Thus, the foregoing descriptions of specific embodiments are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the described embodiments to the precise forms disclosed. It will be apparent to one of ordinary skill in the art that many modifications and variations are possible in view of the above teachings.
