The present invention relates to an inverter with at least two switching means for feeding an oscillator circuit from a source, wherein a control device of the inverter controls the switching means.
In modern inverter technology, resonant switching processes are increasingly used as switching relief of the power semiconductors. This results in lower switching losses and therefore improved overall efficiency also. If the inverters are loaded with a resonant load network, the oscillator circuit is active in the output circuit and not in the intermediate circuit of the inverter.
Various methods exist for feeding resonant loads by means of an inverter. A first method provides that the power semiconductors of the inverter are controlled at a fixed clock frequency. The clock frequency is selected in such a way that only the smallest possible switching losses occur. The operating point is preferably to be selected as slightly inductive. Provided that a series oscillator circuit is fed, the power semiconductors are activated only if their voltage is equal to zero, and are de-activated (ZVS) only if their current is more or less zero (ZCS). The disadvantage of this method is that only unfavourable facilities for control via the timing of the power semiconductors exist, since a pulse width modulation causes high switching losses. A further control facility exists in the variation of the intermediate circuit voltage Uic of the feed-in inverter. The intermediate circuit voltage can be set e.g. by means of a DC/DC converter, as shown in
In a second possible method, the output variable can be controlled via the clock frequency of the inverter. This method exploits the frequency dependence of the output-side oscillator circuit. The control device times the power semiconductors at a higher frequency than the resonant frequency so that inductive operation is always guaranteed. The disadvantage of this method is that, although activation takes place at ZVS, the power semiconductors must always de-activate a certain current, as a result of which switching losses occur.
A third possible method offers the advantage of an adaptation to changes in the transmission medium, such as e.g. a change in the inductances due to mechanical influence, ageing of the capacitors, heating, etc. Measurements must be performed which enable the time specifications of the timing. If a series oscillator circuit is used, it suffices to measure the output current and forward the latter as an inverted control signal to the power semiconductors. The 180° phase shift enables the oscillation build-up of the system.
In the previously described method, control is possible via the intermediate circuit voltage also, as a result of which, however, a further power stage in the form of a DC/DC converter must be connected upstream of the inverter, whereby the overall efficiency disadvantageously deteriorates.
A method is known from DE 101 15 326 for controlling de-activatable semiconductor switches in bridge arms of an inverter which serve to supply a parallel oscillator circuit connected to the input of the inverter, wherein the inverter is operated with an injected current and at least one diode is connected in series with the semiconductor switches. The method known from DE 101 15 326 uses a controller which sets an optimum phase angle so that voltage peaks occur on neither the semiconductor switches nor the series diodes.
The object of the present invention is to provide an inverter with a control device for the switching means of the inverter which are designed in particular as power semiconductors which, with the use of a constant source feeding the inverter, enables a control of the output variable in line with a nominal variable.
This object is achieved according to the invention in that the control device controls the switching means in such a way that, in a first mode A, the inverter feeds the oscillator circuit via the switching means from the source and, in a second mode B, the oscillator circuit is decoupled from the source, wherein the control device switches back and forth between the two modes A and B to adjust a desired current (Ip
The desired current if a series oscillator circuit is used or the desired voltage when a parallel oscillator circuit is used is set over the temporal duration of the two modes A and B, in particular over their pulse duty factor. The control device controls the switching means softly so that the temporal duration while one mode is active is equal to or longer than the period duration of the resonant frequency of the oscillator circuit. The switching frequency of the control signals controlling the switching means, in particular the gate signals, is dependent in mode A on the resonant frequency of the oscillator circuit, normally minimally greater than the resonant frequency. The control device or controller can be advantageously designed in such a way that the switching frequency at which the switching means are switched in mode A is determined by the frequency of the oscillator circuit.
The inverter can be implemented by means of a bridge circuit. This can be designed as a full-bridge or half-bridge or push-pull circuit. The switching means are disposed in its bridge arms, wherein the transverse arm is formed by the oscillator circuit. If a semi-controlled inverter is used, capacitors are to be provided in the uncontrolled bridge arms, as shown in
If a series oscillator circuit is connected at the output of the inverter, the inverter is advantageously fed by a DC voltage source, in particular a voltage source with a constant output voltage. In this case, the current Ip flowing through the series oscillator circuit is controlled. A two-step controller, a PWM controller or a push-pull controller can be used as the controller. In mode A, the inverter operates normally, wherein the clock frequency of the switching means is predefined by the resonant frequency of the series oscillator circuit. If a two-step controller is used, the control device switches over to mode B as soon as the current Ip in the series oscillator circuit has exceeded a maximum value. In mode B, the series oscillator circuit is short-circuited over two bridge arms of the inverter and is thus decoupled from the voltage source feeding the inverter. The current in the series oscillator circuit thus freewheels in mode B over the two upper or two lower bridge arms of the full-bridge circuit of the inverter. If a primary oscillator circuit of an energy transmission system is fed by means of the inverter according to the invention, the resonant frequency of the series oscillator circuit changes with the width of the air gap and the secondary-side load. Depending on the secondary-side quality or load, the current decreases more or less quickly in the series oscillator circuit. As soon as the current in the series oscillator circuit has reached or fallen below a lower threshold value, the control device switches over once more to mode A. The changeover from one mode to the other advantageously involves soft switching, so that only low switching losses and interfering electromagnetic radiation arise.
If a parallel oscillator circuit is connected at the output of the inverter, the inverter is advantageously fed by a DC current source, in particular a constant current source. In this case, the voltage Up decreasing on the parallel oscillator circuit is controlled. In mode A, the switching frequency of the switching means of the inverter similarly follows the frequency of the parallel oscillator circuit. After an upper voltage value has been exceeded, switchover to mode B takes place here also, so that the parallel oscillator circuit is no longer fed via the current source. For this purpose, the switching means must be switched for the duration of mode B in such a way that the current of the current source flows only through the bridge arm and the voltage freewheels in the parallel oscillator circuit.
The switching means are switched with the lowest possible loss. If a series oscillator circuit is used, the control device can advantageously be developed in such a way that the switching means are activated only if the voltage decreasing on them is equal to zero. The de-activation process is initiated or released only if the current through the respective switching means has fallen below a specific, in particular predefinable, threshold value. The threshold value is set either as a one-off by means of a calibration process in which the inverter is optimised in terms of e.g. optimum overall efficiency and/or low electromagnetic interferences. Due to the optimised threshold value, the phase angle between the current and voltage is set in such a way that the de-activation process is neither too inductive, and therefore no excessively high current needs to be switched, nor too capacitive, so that switching is not carried out too close to the current zero transition.
If a parallel oscillator circuit is used, all switching means are active, i.e. conducting, in the overlap time. While a diagonal pair of the switching elements in the form of controllable semiconductors is closed, the others are closed only if a negative voltage threshold value Uthresh on them is exceeded. The switching elements are advantageously de-activated only if the current flowing in them is zero. This time arises when a positive voltage is measured on the switching elements. The preferred phase position is slightly capacitive. This produces an operating frequency fA which is slightly greater than the resonant frequency f0of the parallel oscillator circuit.
Due to the quality of the oscillator circuit, the abrupt change in the injected power during the changeover from one mode to the other is advantageously smoothed so that the load undergoes only a small subsynchronous ripple.
If a series oscillator circuit is used, at least the voltage decreasing on a switching means and the actual current Ip-act flowing through the oscillator circuit are measured. The measured variables form feedback variables for the control circuit while the desired current Ip-ref to be set forms the input variable of the controller.
If a parallel oscillator circuit is used, at least the voltage decreasing on a switching means and the actual voltage Up-act decreasing on the oscillator circuit are measured. The measured variables form feedback variables for the control circuit while the desired voltage Up-ref to be set forms the input variable of the controller.
One possible embodiment of the control device for a fully controlled full-bridge inverter with an output-side series oscillator circuit is explained below.
For each switching means of the inverter, the control device generates a control signal G1 to G4, e.g. by means of flip-flops. To do this, the voltage potentials on both end points P1 and P2 of the transverse arm or of the series oscillator circuit of the full bridge are determined and compared by means of comparators with a voltage threshold value UPthresh The output signals of the comparators serve to generate activation release signals. Depending on the activation release signal, the switching means concerned can be activated on the next voltage zero transition.
The de-activation release signals are generated in that the current Ip-act flowing in the series oscillator circuit is compared in comparators with the current threshold values IPosThresh and UNegThresh. An additional device also generates a blocking signal which ensures that a de-activation release signal can be generated only during the positive half-wave of the current and simultaneously negative increase in the current Ip, or a de-activation release signal can be generated only during the negative half-wave of the current Ip and simultaneously positive increase in the current Ip for the respectively conducting switching means. It is thus ensured by means of the blocking voltage that the generation of the de-activation release signal is generated only in the second half of a half-wave of the current Ip. The blocking signal can be implemented, for example, by means of a dead-time element or a device consisting of a series circuit comprising an integrator which integrates the current Ip and a downstream zero transition detection device.
Through the calibration to define an optimum current threshold value or optimum current threshold values IPosThresh and UNegThresh, the control device is optimised so that either efficiency is maximised and/or the level of electromagnetic interferences is minimised. Through the measurement and processing of the actual current Ip-act and the voltage potentials P1 and P2, the control signals G1 to G4 of the switching means are thus matched to the frequency of the series oscillator circuit, as a result of which the inverter frequency in mode A follows the resonant frequency of the series oscillator circuit.
The control device continuously compares the desired current Ip-ref to be set with the actual current Ip-act and generates a setting signal which, together with further control signals, serves to control the de-activation release of the two switching means which implement the freewheeling of the series oscillator circuit in mode B. As soon as the current Ip-act has exceeded a certain threshold value Ip-max, the two switching means are prevented from de-activation by means of corresponding de-activation release signals so that they implement the necessary bipolar short circuit wherein the series oscillator circuit freewheels over the switching means and the current in the oscillator circuit decreases. As soon as the actual current Ip-act has again fallen below a lower threshold value Ip-min, a switchback to mode A is again effected. So that the correct polarity always prevails during the switchover to mode A, it is necessary for mode B to be maintained for integral oscillation periods. The shortest time for which mode A can be active is a half-oscillation period.
The inverter according to the invention is explained in detail below with reference to drawings and circuit diagrams, in which:
a: shows a full-bridge inverter according to the invention for a parallel resonant oscillator circuit, of which the input current Iic is constant and which sets the voltage Up present on the parallel oscillator circuit via the mode changeover;
a: shows the phase response for a series oscillator circuit;
a shows the circuit diagram of the inverter according to the invention, if said inverter is loaded on the output side with a parallel oscillator circuit LS-CS. In contrast to the inverter with a series oscillator circuit, the voltage Up present on the parallel oscillator circuit, rather than the current Ip, is set here by means of the reverse-blocking switching means S1 to S4. In this case, the inverter is fed by means of a constant current source which injects the current Iic. In mode A, the inverter operates in its normal mode, wherein the control device is matched accordingly to the setting variable. In mode B, the parallel oscillator circuit is decoupled from the current source initially through the generation of a short circuit of the current source Iic by means of a bridge arm S1 and S2 or S3 and S4. The switching means of the respective other bridge arm are then blocking, so that the parallel oscillator circuit can freewheel in mode B, as a result of which the voltage Up temporally decreases. If a lower voltage threshold value Up-min is attained, switchback to mode A is again effected, wherein mode A is maintained until an upper voltage threshold value Up-max is attained and switchback to mode B is effected.
The current Ip is integrated by means of the integrator 24, as a result of which a signal Ip90° is generated which is processed by a zero transition detection element 25 to produce the blocking signal Block. The blocking signal Block is connected to an input of the AND gate 14 and an input of the AND gate 16. The blocking signal Block is simultaneously negated by means of the NOT gate 21 and is connected as
An optional D-flip-flop 30 can be used for the synchronisation and ensures that switching is not effected by means of the setting signal/set from one mode to the other during a switching process of switching means.
a shows the phase response for a resonant oscillator circuit. With a specific phase angle Φ, which is settable or predefinable by means of the current threshold values IPosThresh and INegThresh, an operating frequency fA is set at which the current Ip oscillates. A phase angle Φ equal to ZERO produces an operating frequency of the inverter which is equal to the resonant frequency f0 of the oscillator circuit. At a higher operating frequency fA, an inductive phase position in relation to the resonant frequency f0 can be achieved.
If, as shown above, mode A is activated in each case for a full period, the intermediate circuit capacitor undergoes no DC offset and is thus less loaded. However, the disadvantage exists with a timing of this type that the control resolution is less than in the method shown in the lower diagram, in which mode A is active in each case for a half-oscillation period only, and mode B in each case for a full oscillation period. The pulse duty factor is 1:2 with this timing of the modes also. However, the intermediate circuit capacitor disadvantageously undergoes a DC offset.
The control device generates the gate signals G1 to G4 for the switching means S1 to S4.
The gate signals G1 to G4 are generated by means of the flip-flops 1, 2, 3, 4 which are set or reset by means of the activation release signals 6, 7, 10, 11 and the de-activation release signals 5, 8, 9, 12. The de-activation release signals 5, 8, 9, 12 are determined by the characteristic of the current Up so that the gate signals G1 to G4 control the switching means S1 to S4 in synchronism with the current Up. To do this, the control device has two comparators 23′ and 26′ which determine the polarity of the voltage Up on the basis of the predefined threshold values UPosThresh and UNegThresh. The output of the comparator 23′ which determines the positive voltage state of the voltage Up is connected to the AND gates 14 and 16 which generate the de-activation release signals 5, 9 for the switches S2 and S3. The output of the comparator 26′ which determines the negative voltage state of the voltage Up, is connected to the AND gates 13 and 15 which generate the de-activation release signals 8, 12 for the switches S1 and S4.
The voltage Up is integrated by means of the integrator 24′, as a result of which a signal Up90° is generated which is processed by a zero transition detection element 25′ to produce the blocking signal Block. The blocking signal Block is connected to an input of the AND gate 14′ and an input of the AND gate 16′. The blocking signal Block is simultaneously negated by means of the NOT gate 21 and is connected as
An optional D-flip-flop 30′ can be used for the synchronisation and ensures that switching is not effected by means of the setting signal/set from one mode to the other during a switching process of switching means.
In mode B, either the bridge arm S1-S2 is current-conducting and the other bridge arm S3 and S4 is switched to a blocking state so that the parallel oscillator circuit is decoupled from the current source Iic. The voltage Up drops while mode B is active. If the controller 22′ is designed as a two-step controller, switchback to mode A is effected as soon as the voltage Up falls below a lower limit value. Mode A then remains active again until the voltage Up has exceeded an upper limit value, after which the control device then switches to mode B.
The previously described control device cannot control the inverter correctly until the oscillator circuit has started to oscillate. Additional measures can therefore be taken which disable the control device for the time of the oscillation build-up. The oscillation build-up of oscillator circuits is already known from the prior art.
The integrator 24, 24′ will not supply a usable signal until the oscillator circuit has started to oscillate. It can be replaced during the oscillation build-up phase by an inverted differentiator. The latter provides a 90° phase shift, but is EMC-sensitive. It is therefore better for the stability of the circuit to switch over to integrator mode only as from a specific oscillator circuit current or a specific oscillator circuit voltage. Since the phase shift is used for signal blocking only, the integrator can be replaced with a constant dead-time element Tdead for a narrower frequency range. The inverter thus clocks in the oscillation build-up process over this operating time only and has the clock frequency f=1/Tdead until the other signals are generated from the current and voltage. This solution is simple in structure, but operates in a relatively smaller frequency interval only.
Number | Date | Country | Kind |
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10 2011 122 103.8 | Dec 2011 | DE | national |
Filing Document | Filing Date | Country | Kind |
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PCT/EP2012/076217 | 12/19/2012 | WO | 00 |