Controlled frequency power factor correction circuit and method

Abstract

A power factor correction (PFC) circuit (10) includes a latch (16) having an output that initiates a coil current (ICOIL) in response to a transition edge of a clock signal (CLOCK) to generate a PFC signal (VOUT). An input receives a control signal (TERM). A current modulation circuit (14) has a first input (36) coupled for receiving the PFC signal to establish a charging time (TCH) of the coil current. A second input senses the coil current to establish a duty cycle of the coil current over a period of the clock signal, and an output (38) provides the control signal as a function of the charging time and the duty cycle.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention relates in general to integrated circuits and, more particularly, to integrated power factor correction circuits.

[0002] Integrated power factor correction (PFC) circuits are switching circuits that ensure that an alternating current (AC) line is loaded with an in-phase, substantially sinusoidal current. Without PFC correction, many electrical systems draw current from the AC line voltage only near the peak voltage levels of the AC line. The aggregate effect of loading the AC line with large currents at the voltage peaks and zero current at other times is to produce distortion of the AC line voltage. In addition, systems without PFC can cause high neutral currents to flow in three-phase distribution networks. To avoid these problems so that electrical devices function properly, the distribution networks of regional utility companies must be oversized, which necessitates a large capital investment. Several governments are mandating that PFC be incorporated in the power supplies used in some or all electrical devices.

[0003] PFC circuits typically switch current through an inductor or coil from the AC line at a frequency much higher than the frequency of the AC line to magnetize or charge a coil. For example, systems may use a switching frequency of at least one hundred kilohertz when the AC line frequency is fifty hertz. The energy stored in the coil is discharged into a capacitor to generate an intermediate PFC direct current (DC) supply voltage to power an electrical device or system. To attain a substantially sinusoidal AC current, the average value over a switching period of the current switched through the coil is made proportional to the current voltage on the AC line. The result is a high effective power factor for the AC line.

[0004] Most previous PFC circuits operate in a free-running mode in which a current is switched to charge the coil as soon as the coil current stored in the previous cycle has been discharged across the capacitor. As a result, the previous PFC circuits switch at a frequency that varies with the current AC line voltage as well as the system's load current. Such variable switching frequencies are difficult to filter out in order to suppress or remove electromagnetic interference generated by the switched coil currents. Such filtering requires complex filters which dissipate power and substantially increase the manufacturing cost of a system.

[0005] Hence, there is a need for a PFC circuit and method of correcting the power factor that operates at a fixed or nearly fixed frequency in order to reduce a system's electromagnetic interference while maintaining a low fabrication cost of the PFC circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 is a schematic diagram of a power factor correction (PFC) circuit;

[0007] FIG. 2 is a timing diagram showing waveforms of the PFC circuit;

[0008] FIG. 3 is a schematic diagram of a duty cycle sensor of the PFC circuit;

[0009] FIG. 4 is a schematic diagram of a current modulator of the PFC circuit; and

[0010] FIG. 5 is a schematic diagram of the current modulator in an alternate embodiment.

DETAILED DESCRIPTION OF THE DRAWINGS

[0011] In the figures, elements having the same reference number have similar functionality.

[0012] FIG. 1 is a schematic diagram of a power factor correction (PFC) circuit 100 controlled by a PFC control circuit 10 and including a diode bridge 20, resistors 22-24, an inductor or coil 25, a diode 26, an output capacitor 27, a timing capacitor 28 and a switching transistor 29. PFC circuit 100 receives a sinusoidal voltage VAC from an alternating current (AC) line and produces a direct current (DC) PFC output signal VOUT at a node or output 30. In one embodiment, PFC circuit 100 functions as a step up switching regulator that receives VAC at a value of about two hundred twenty volts root-mean-square (RMS) and a frequency of about fifty hertz and produces PFC output voltage VOUT with a value of about four hundred volts DC. In some regions, VAC has a value of about one hundred ten volts RMS and VOUT a frequency of sixty hertz. VAC has a typical range of about plus and minus, twenty percent.

[0013] Diode bridge 20 is a standard full-wave bridge rectifier that rectifies line voltage VAC and produces a rectified sine wave voltage VIN at a node 32 with a frequency of twice the frequency of VAC or about one hundred hertz and a peak value of about three hundred ten volts. A capacitor (not shown) may be connected across diode bridge 20 to reduce VAC noise peaks.

[0014] Coil 25 has a typical inductance L=100.0 microhenries and a low equivalent series resistance for high efficiency operation.

[0015] Transistor 29 is a high current n-channel metal-oxide-semiconductor field effect transistor that switches a coil current ICOIL through coil 25. In one embodiment, transistor 29 is a power transistor able to switch peak values of coil current ICOIL greater than two amperes. These currents are small near the zero crossing point of VAC and large near the VAC voltage peaks. Transistor 29 typically has a large gate capacitance greater than five hundred picofarads.

[0016] Coil current ICOIL has a component charging current ICH and a component discharging current IDSCH. Charging current ICH flows through coil 25 to store magnetic energy in coil 25 when transistor 29 is on. When transistor 29 switches off, the stored magnetic energy flows as discharge current IDSCH from coil 25 through diode 26 to capacitor 27 to develop PFC voltage VOUT on node 30.

[0017] Coil current ICOIL has a return path through resistor 22 to diode bridge 20 which develops a current sense voltage VIS on a node 31 to monitor when ICOIL is flowing. In one embodiment, resistor 22 has a resistance of about 0.2 ohms, so VIS has a value of about −0.2 volts when ICOIL has a magnitude of one ampere. Alternatively, the conduction time of ICOIL can be measured using a voltage sensing technique, rather than the current sensing arrangement shown in FIG. 1. For example, coil 25 can be formed as a primary winding of a transformer whose secondary winding has a terminal coupled at node 31 to the input of duty cycle sensor 12, typically through a resistor, the other secondary winding terminal being grounded. The secondary winding generates current sense voltage VIS with a positive voltage when ICOIL is charging, a negative voltage while ICOIL is discharging, and with substantially zero volts when ICOIL is zero.

[0018] The magnitude of ICOIL is a function of PFC output voltage VOUT, and is controlled by feeding back VOUT through a voltage divider formed with resistors 23 and 24. This voltage divider samples VOUT and provides a sense voltage VSENSE on a node 36. Resistors 23 and 24 have resistances of R23 and R24, respectively.

[0019] PFC control circuit 10 includes a duty cycle sensor 12, a current modulator 14, a flip-flop or latch 16 and an output buffer 18. Current modulator 14 produces a timing current ITIMING that charges an external capacitor 28 to develop a timing voltage VTIMING that controls the period of charging current ICH, and therefore its peak amplitude, as described below. In one embodiment, PFC control circuit 10 is formed on a semiconductor substrate as an integrated circuit.

[0020] Output buffer 18 is a standard non-inverting amplifier that is capable of driving the high capacitive load presented by transistor 29.

[0021] Latch 16 is a standard R-S flip-flop that has a Q output providing a digital switching signal VSW which is set on a transition edge of a clock signal CLOCK and reset on a transition edge of a digital termination signal TERM. To achieve a high power factor, CLOCK preferably operates at a frequency much greater than the frequency of VIN. In one embodiment, VIN has a frequency of about one hundred hertz, or a period of about ten milliseconds, and CLOCK pulses are generated at a controlled or substantially constant frequency of about one hundred kilohertz, or a period of about ten microseconds. When VSW is set, transistor 29 turns on through output buffer 18 to initiate charging component ICH of coil current ICOIL to magnetize or store energy in coil 25. When VSW is reset, transistor 29 is turned off through output buffer 18, terminating charging component ICH and initiating discharging component IDSCH of ICOIL, which flows through diode 26 to transfer energy from coil 25 to capacitor 27.

[0022] Duty cycle sensor 12 monitors coil current ICOIL. and produces a digital coil current sense signal COILON at an output 34 which is logic high when ICOIL has a substantially nonzero value and logic low when ICOIL is zero. A comparator compares current sense signal VIS with a reference signal VREF2 to generate COILON. In one embodiment, duty cycle sensor 12 includes a preamplifier that increases the magnitude of VIS to improve noise immunity. Since VSW is set on each CLOCK pulse to begin a new cycle, the portion of a CLOCK period in which COILON is logic high is indicative of the duty cycle of ICOIL.

[0023] Current modulator 14 has an input at node 36 that monitors PFC signal VOUT through sense signal VSENSE to establish a time TCH for the charging portion ICH of coil current TCOIL. An input at node 34 senses when ICOIL is flowing to provide a digital signal COILON that establishes a duty cycle of ICOIL over a CLOCK period. Current modulator 14 includes an error amplifier that amplifies the difference between VSENSE and a reference voltage VREF1 to produce a correction signal VERR for setting the magnitude of ICOIL, and therefore the time TCH. This amplification is integrated with COILON over a period of CLOCK to produce termination signal TERM at an output at node 38 to terminate charging current ICH and initiate discharging current IDSCH. Hence, TERM is produced as a function of TCH and the duty cycle. In one embodiment, TERM is produced so as to maintain a constant product of TCH and the duty cycle of ICOIL

[0024] Switching cycles of PFC control circuit 10 are initiated by clock signal CLOCK which preferably operates at a constant or nearly constant frequency. Since the period of CLOCK is much smaller than the period of VIN, a substantially constant voltage VIN appears across coil 25 when transistor 29 turns on. Coil current ICOIL increases linearly with a slope approximately equal to VIN/L, so its peak value is IPEAK=TCH*VIN)/L, where TCH is the duration of charging current ICH. Similarly, the slope of discharging current IDSCH is approximately equal to (VOUT−VIN)/L, and its duration TDSCH=L*IPEAK/(VOUT−VIN). Hence, the total period when ICOIL is nonzero is given by equation 1), 1$\begin{array}{cc}{T}_{\mathrm{COIL}}=T_{\mathrm{CH}}+T_{\mathrm{DSCH}}=L·I_{\mathrm{PEAK}}·\frac{V_{\mathrm{OUT}}}{V_{\mathrm{IN}}·\left(V_{\mathrm{OUT}}-V_{\mathrm{IN}}\right)}.& 1)\end{array}$

[0025] It can be shown that the average coil current TCOIL—CLOCK over a CLOCK period TCLOCK is given by equation 2), 2$\begin{array}{cc}{I}_{\mathrm{COIL\_CLOCK}}=\frac{V_{\mathrm{IN}}·T_{\mathrm{CH}}}{2·L}·\frac{\left(T_{\mathrm{CH}}+T_{\mathrm{DSCH}}\right)}{T_{\mathrm{CLOCK}}}=\frac{V_{\mathrm{IN}}}{2·L}\left(T_{\mathrm{CH}}·D_{\mathrm{CYCLE}}\right)& 2)\end{array}$

[0026] where DCYCLE=(TCH+TDSCH)/TCLOCK. A high power factor is achieved when the average coil current ICOIL—CLOCK follows the rectified sinusoidal shape of VIN, which occurs if TCH*DCYCLE is made constant.

[0027] The operation of PFC control circuit 10 can be seen by referring to FIG. 2, which is a timing diagram showing selected waveforms of PFC control circuit 10. Initially, at time T0, assume that clock signal CLOCK, switching signal VSW, termination signal TERM and coil current sense signal COILON are all low. Further assume that coil current ICOIL, current sense voltage VIS, timing current ITIMING and timing voltage VTIMING each are equal to zero.

[0028] At time T1, a low to high transition edge of CLOCK sets latch 16 to induce a low to high transition of VSW, turning on transistor 29 through buffer 18 to initiate coil current ICOIL. Note that the component of ICOIL that begins to flow at time T1 is charging current ICH. Since the period of CLOCK is much less than the period of VIN, and the voltage drop across transistor 29 typically is small, a substantially constant voltage VIN is applied across coil 25 to cause ICOIL to increase linearly or ramp up at a rate VIN/L as shown. ICOIL flows through resistor 22 to develop current sense voltage VIS, which also ramps linearly but in a negative voltage direction as shown. The low to high VSW transition sets COILON high to enable timing current ITIMING, which charges capacitor 28 to develop timing voltage VTIMING as a linear ramp.

[0029] At time T2, VTIMING reaches a threshold voltage to generate a low to high transition of termination signal TERM, which resets latch 16. This threshold voltage may be a predetermined voltage or a variable voltage, as described in detail below. A high to low transition of VSW terminates charging current ICH and initiates discharging current IDSCH of TCOIL to transfer energy from coil 25 to capacitor 27. VSW also closes a switch that discharges capacitor 28 and shunts ITIMING to ground to reduce VTIMING to zero as shown. IDSCH decreases in a linear fashion with a slope (VOUT−VIN)/L until the magnetic energy stored in coil 25 is fully discharged.

[0030] At time T3, ICOIL decreases to zero. Current sense signal VIS also ramps to zero, which produces a high to low transition of coil current sense signal COILON. ICOIL remains substantially zero for the remainder of the CLOCK period until time T4, when the next cycle begins.

[0031] FIG. 3 shows a schematic diagram of duty cycle sensor 12 coupled to resistor 42, including an amplifier 44, a comparator 45, a latch 46 and resistors 42-43. Duty cycle sensor 12 receives sense signal VIS at node 31 through resistor 42 to monitor the flow of coil current ICOIL. An output is coupled to node 34 to produce coil current sense signal COILON with a logic low value when ICOIL is substantially zero and a logic high value when ICOIL is nonzero.

[0032] At time T1, a logic low to high transition of clock signal CLOCK sets switching signal VSW to a logic high value to initiate coil current ICOIL. Latch 46 is set to produce a low to high logic transition of COILON on node 34 to indicate that ICOIL is flowing, i.e., has a nonzero value. Concurrently, sense signal VIS ramps from zero to a negative value.

[0033] Amplifier 44 and resistors 42-43 function as a gain stage that amplifies VIS to increase the system noise immunity. In one embodiment, resistor 43 has a value of about ten kilohms and resistor 42 has a value of about one kilohm, which results in an amplified signal on a node 41 whose value is about (−10*VIS). Hence, node 41 ramps from zero to a positive level until time T2, when its value begins to decrease toward zero volts as coil 25 discharges. When the potential on node 41 decreases to a value less than VREF2, comparator 45 generates a logic low to high transition of a reset signal VR, which resets latch 46 to produce a high to low logic transition of COILON that indicates that ICOIL has discharged to substantially zero. In practice, VREF2 may be set to a small positive nonzero value to avoid an oscillatory condition in comparator 45 that effectively introduces noise in VR. In one embodiment, VREF2 is set to 0.1 volts, which corresponds to a value of ICOIL=0.05 amperes.

[0034] FIG. 4 is a schematic diagram showing current modulator 14 in further detail, including amplifiers 47-48, a comparator 49, switches 50-51, resistors 52-53, capacitors 54-55 and a current source 56. Resistors 52 and 53 have resistances R52 and R53, respectively, while capacitors 54 and 55 have capacitances C54 and C55, respectively.

[0035] Amplifier 47 functions as an error amplifier that compares sense signal VSENSE to reference voltage VREF1 and amplifies their difference to produce correction signal VERR on node 72. In effect, amplifier 47 amplifies the difference between the desired value of VOUT=VREF1*(1+R23/R24) and the actual current value of VOUT. PFC control circuit 10 effectively regulates VOUT by maintaining VSENSE substantially equal to VREF. Capacitor 54 and resistors 23-24 function as an integrator or low pass filter which filters out either one hundred hertz or one hundred twenty hertz ripple in VSENSE which may be present in PFC signal VOUT, depending on the local or regional frequency of VAC. Capacitor 54 and resistors 23-24 produce an integration time constant R23*R24*C54/(R23+R24) that attenuates VSENSE fluctuations having a shorter duration. In one embodiment, the time constant is at least five times the period of VIN so, for example, when VIN has a period of ten milliseconds, the time constant is set to be at least fifty milliseconds. Hence, VERR is considered to be substantially constant over a period of VIN.

[0036] Correction signal VERR is effectively divided by the duty cycle of ICOIL in a gain stage 70 that includes amplifier 48, resistors 52-53, capacitor 55 and switch 50. Gain stage 70 functions as an integrator whose time constant is set by resistors 52-53 and capacitor 55 to filter out switching transients present when switch 50 is opened and closed at the frequency of clock signal CLOCK. This time constant preferably has a value in the range of five times the period of CLOCK or greater. For example, if a period of CLOCK is ten microseconds, the time constant of resistors 52-53 and capacitor 55 preferably is at least fifty microseconds. A control or threshold signal VTON is provided at a node 74.

[0037] The operation of gain stage 70 is as follows. When COILON is high, such as from time T1 to time T3 (ICOIL is nonzero), switch 50 is open. Verr functions as a reference voltage coupled to the non-inverting input of amplifier 48. VTON is coupled to the inverting input through resistors 52 and 53 and the difference (VERR−VTON) is integrated with a time constant TSW0=C55*(R52+R53). When COILON is low, such as from time T3 to T4 (ICOIL is zero), switch 50 is closed and the voltage across switch 50 is approximately zero. Substantially zero volts is then applied to the inverting input of amplifier 48 through resistor 52. VERR still acts as a reference voltage at the noninverting input of amplifier 48, and the difference (VERR−0.0 volts) is integrated with an integration time constant TSW1=C55*R52. Resistor 53 is selected to be much smaller than resistor 52, so TSW0=TSW1, approximately, to produce substantially equal integration time constants regardless of the position of switch 50. Timeconstants TSW0 and TSW1 are preferably selected to be higher than the period of CLOCK, so a time-weighted average voltage VTON*(T3−T1)/(T4−T1)=VTON*DCYCLE is present at the inverting input of amplifier 48, where DCYCLE=(T3−T1)/(T4−T1) is the duty cycle of ICOIL over a CLOCK period. The regulation of VOUT by PFC circuit 100 ensures that VERR=VTON*DCYCLE or VTON=VERR/DCYCLE at the respective inputs of amplifier 48. Since VERR is substantially constant over a period of CLOCK, so is the product VTON*DCYCLE, which results in ICOIL having a sinusoidal shape and PFC circuit 100 having a high power factor.

[0038] VTIMING is generated by charging a capacitance C28 with a constant current ITIMING, and therefore has a ramp shape that is a linear function of ITIMING. VTON is coupled to an input of comparator 49 to control the trip point at which timing voltage VTIMING sets termination signal TERM to logic high to terminate charging current ICH.

[0039] Note that ITIMING is held substantially constant while correction voltage VERR is adjusted by COILON to generate threshold voltage VTON so that the product TCH*DCYCLE is substantially constant. As indicated above, when TCH*DCYCLE is constant, the average value of ICOIL is sinusoidal and in phase with AC line voltage VAC, which results in a high power factor. The high power factor is achieved while switching coil current ICOIL at a constant frequency with clock signal CLOCK to reduce the level of electromagnetic interference or to facilitate its attenuation by filtering.

[0040] FIG. 5 is a schematic diagram showing current modulator 14 in an alternate embodiment. In this embodiment, correction voltage VERR is coupled directly to the inverting input of comparator 49 to control the switching threshold of VTIMING, while ITIMING is adjusted by duty cycle DC of ICOIL to maintain the product TCH*DCYCLE constant.

[0041] Amplifier 60 operates as an integrator with integration time constant TSW=C61*R68, where C61 is the capacitance of capacitor 61 and R68 is the resistance of resistor 68. Capacitor 61 and resistor 68 preferably are selected so that Tsw is much greater than the period of CLOCK.

[0042] From T1 to T3, when ICOIL is nonzero, COILON is high, switch 50 is open and reference current IREF1 is routed through a resistor 66 to develop a voltage V66=IREF1*R66 on a node 77, where R66 is the resistance of resistor 66. From T3 to T4, when ICOIL is zero, COILON is low, switch 50 is closed, and voltage V66=0.0 volts on node 77. When integrated over a period of CLOCK, the time weighted average value of voltage V66 is IREF1*R66*DCYCLE=V66*DCYCLE.

[0043] The output of amplifier 60 controls the base current of a transistor 65 in conjunction with a resistor 69. This arrangement produces a collector current I65 which is subtracted from a reference current IREF2 to produce a current IOUT that develops a voltage V67 across resistor 67. Collector current I65 provides a feedback path that maintains V66 and V67 at the same effective average potential, so IOUT=IREF1*DCYCLE*R66/R67. Timing current ITIMING is mirrored to IOUT and scaled to a factor K by a current mirror 63, so that ITIMING=K*IOUT=K*IREF1*DCYCLE*R66/R67. Hence, ITIMING is proportional to duty cycle DCYCLE.

[0044] ITIMING charges capacitor 28 as described above to produce timing voltage VTIMING as a ramp which is compared to VERR in comparator 49 to produce control signal TEMP. Since ITIMING is substantially constant over a period of VIN and VTIMING=ITIMING*TCH=K*IREF1*DCYCLE*TCH*R66/R67, the product TCH*DCYCLE is substantially constant. Therefore, ICOIL has an average current that is sinusoidal and PFC circuit 100 has a high power factor.

[0045] In summary, the present invention provides a PFC circuit that is capable of operating at a constant or nearly constant frequency, thereby facilitating the reduction of electromagnetic interference through filtering. A latch has an output that initiates a coil current in response to a transition edge of a clock signal to generate a PFC signal. A current modulation circuit senses the PFC signal to establish a charging time of the coil current, and senses the coil current to establish a duty cycle of the coil current over a period of the clock signal. An output of the current modulation circuit is applied to an input of the latch to provide a control signal that is a function of the charging time and the duty cycle.

Claims

1. A power factor correction (PFC) circuit, comprising: a first latch having an output for initiating a coil current in response to a transition edge of a clock signal to generate a PFC signal, and an input for receiving a control signal; and a current modulation circuit having a first input coupled for receiving the PFC signal to establish a charging time of the coil current, a second input coupled for sensing the coil current to establish a duty cycle of the coil current over a period of the clock signal, and an output for providing the control signal as a function of the charging time and the duty cycle.

2. The PFC circuit of claim 1, wherein the current modulation circuit includes: a first amplifier having a first input for receiving the PFC signal and a second input for receiving a reference signal; and a second amplifier having a first input coupled to an output of the first amplifier and an output for providing the control signal.

3. The PFC circuit of claim 2, wherein the current modulation circuit further includes a first switch operating in response to a sense signal applied at the second input of the current modulation circuit for switching a second input of the second amplifier from the output of the second amplifier to a reference node to establish the duty cycle.

4. The PFC circuit of claim 3, wherein the current modulation circuit further comprises a reactive component coupled for averaging a potential at the output of the second amplifier to produce the control signal.

5. The PFC circuit of claim 4, wherein the reactive component is a capacitor that sets a time constant of the current modulation circuit to a value greater than the period of the clock signal.

6. The PFC circuit of claim 3, wherein the current modulation circuit further includes: a comparator having a first input coupled to an output of the second amplifier and an output for providing the control signal; a current source coupled to a second input of the comparator for charging a capacitance; and a second switch coupled to the current source and responsive to the output of the first latch for discharging the capacitance to terminate the charging portion of the coil current.

7. The PFC circuit of claim 1, further comprising a current sensor having an input coupled for sensing the coil current and an output for providing the sense signal.

8. The PFC circuit of claim 7, wherein the current sensor includes: a first amplifier having a first input coupled to the input of the current sensor and a second input for establishing a threshold level of the coil current; and a second latch having a first input coupled to the output of the first latch, a second input coupled to an output of the first amplifier and an output (34) coupled to the second input of the current modulation circuit for generating the sense signal as a first logic state on the transition edge of the clock signal and as a second logic state when the coil current falls below the threshold level.

9. The PFC circuit of claim 8, wherein the current modulation circuit includes: a comparator having a first input coupled for receiving a ramp signal and an output for providing the control signal; a second amplifier having a first input for receiving the PFC signal, a second input for receiving a reference signal, and an output coupled to a second input of the comparator; and an averaging circuit having an input coupled to the output of the second latch for averaging a first reference current over the period of the clock signal to produce an averaging current indicative of the duty cycle.

10. The PFC circuit of claim 9, wherein the averaging circuit includes: a switch for switching the first reference signal with the sense signal to produce a duty cycle signal; and an integrator having a first input coupled for receiving the second reference signal, a second input for receiving the duty cycle signal, and an output for providing the averaging current.

11. The PFC circuit of claim 10, wherein the averaging current is for charging a capacitance to produce the ramp signal.

12. A method of correcting a power factor, comprising the steps of: initiating a coil current at the beginning of a clock period to generate a power factor corrected (PFC) signal; sensing the coil current to determine a duty cycle of the coil current over the clock period; and terminating a charging portion of the coil current with a control signal that is a function of the PFC signal and the duty cycle.

13. The method of claim 12, wherein the step of terminating includes the steps of: amplifying a difference between the PFC signal and a first reference signal to produce a correction signal; and dividing the correction signal by the duty cycle to produce the control signal.

14. The method of claim 13, wherein the step of multiplying includes the steps of: routing the correction signal to a first input of an amplifier; switching a second input of the amplifier to an output of the amplifier while the coil current flows; and switching the second input of the amplifier to a reference node when the coil current terminates.

15. The PFC circuit of claim 14, wherein the step of dividing further includes the step of filtering the control signal with a time constant greater than the clock period.

16. The method circuit of claim 12, wherein the step of terminating includes the steps of: charging a capacitance with a reference current at the beginning of the clock period to generate a ramp signal; and comparing the control signal with the ramp signal to produce a termination signal that initiates a discharging portion of the coil current.

17. The method of claim 12, further comprising the steps of: dividing a reference current by the duty cycle to produce a ramp current; charging a capacitance with the ramp current to produce a ramp voltage; and comparing the ramp voltage with a reference signal to produce the termination signal.

18. An integrated power factor correction (PFC) circuit, comprising: a driver circuit having a first input for receiving clock pulses to initiate a coil current, a second input for receiving a control signal to terminate a charging portion of the coil current, and an output for generating a PFC signal with the coil current; and a modulation circuit having a first input coupled for sensing the PFC signal to set an amplitude of the coil current, a second input for monitoring the coil current over a period of the clock pulses to produce a duty cycle signal, and an output for providing the control signal as a function of the amplitude and the duty cycle signal.

19. The integrated PFC circuit of claim 18, wherein the modulation circuit includes: an averaging circuit having a first input coupled for sensing the PFC signal, and an output for producing the control signal; and a switch operating in response to the duty cycle signal for switching a second input of the averaging circuit between the output of the averaging circuit and a reference signal.

20. The integrated PFC signal of claim 19, wherein the modulation circuit includes an error amplifier having a first input coupled for receiving the PFC signal, a second input coupled for receiving a reference signal, and an output coupled to the first input of the averaging circuit.