Controller for providing a corrected signal to a sensed peak current through a circuit element of a power converter

Abstract

A controller for a power converter and method of operating the same. In one embodiment, the controller includes a peak detector, coupled to a circuit element of the power converter, configured to produce a signal corresponding to a peak current through a circuit element. The controller also includes an adjustable reference circuit responsive to a difference between the signal and a reference signal corresponding to a desired peak current to produce a corrected signal corresponding to the peak current.

Description

TECHNICAL FIELD

The present invention is directed, in general, to power electronics and, more specifically, to a controller for a power converter and method of operating the same.

BACKGROUND

A switched-mode power converter (also referred to as a “power converter” or “regulator”) is a power supply or power processing circuit that converts an input voltage waveform into a specified output voltage waveform. DC-DC power converters convert a direct current (“dc”) input voltage that may be derived from an alternating current (“ac”) source by rectification into a dc output voltage. Controllers associated with the power converters manage an operation thereof by controlling conduction periods of power switches employed therein. Some power converters include a controller coupled between an input and output of the power converter in a feedback loop configuration (also referred to as a “control loop” or “closed control loop”) to regulate an output characteristic of the power converter.

Typically, the controller measures the output characteristic (e.g., an output voltage, an output current, or a combination of an output voltage and an output current) of the power converter, and based thereon modifies a duty cycle or an on time (or conduction period) of a power switch of the power converter to regulate the output characteristic. To increase an efficiency of a flyback power converter, a capacitor is coupled across a power switch to limit a voltage of the power switch while a transformer of the power converter is reset when the power switch is turned off. A flyback power train topology may be configured as a quasi-resonant flyback power converter.

In a common application of a flyback power converter, an output current of the power converter is regulated. With conventional design approaches, however, it is difficult to achieve quasi-resonant power converter operation and, at the same time, regulate an output current of the power converter. In one conventional approach, an on time of a diode on a secondary side of the power converter is sensed and a peak value of primary current is held constant, the output current is kept constant by controlling an off time of a power switch on a primary side of the power converter. This process may defeat quasi-resonant switching operation of the power converter.

In another approach, an output current is sensed and a power switch on a primary side of the power converter is controlled employing an optocoupler to transmit a signal of the secondary side of the power converter to a controller referenced to the primary side of the power converter. This approach increases power converter cost due to the presence of the optocoupler. In yet another approach, a regulation of an output current is implemented through the controller by calculating an output current employing an average of input current and a duty cycle of a power switch on a primary side of the power converter. This approach preserves quasi-resonant switching without the need for an optocoupler, but requires a complex calculation in the controller.

In a switched-mode power converter, it is generally beneficial to limit a peak current in a primary winding of a magnetic circuit element (or device) such as a power transformer or an inductor. This prevents magnetic saturation in the magnetic circuit element, to protect a power switch employed therein, or to limit a maximum level of output power from the power converter. If a peak current in a winding of the magnetic circuit element is not limited or otherwise controlled to a constant level, this can have an unwanted effect on output of the power converter (e.g., an output ripple can increase), and a primary-controlled output current limit can exhibit an unwanted level of variation.

It is common practice in the design of a switched-mode power converter to use a comparator to limit a peak current to a desired current limit in a primary winding of the magnetic circuit element. The comparator sends a signal to control logic when a voltage at a shunt resistor or other current-sensing circuit element becomes higher than a reference voltage. Then the control logic switches off a power switch. The comparator, the control logic and the power switch, however, operate with inherent delays that can be variable as a function of the operating environment and sensed voltages. Due to these inherent and variable delays, current in the power switch and the magnetic circuit element continues to rise with the result that the peak of the current becomes higher than the desired current limit by a variable amount that is generally dependent on an input voltage to the power converter. A higher input voltage generally produces a higher current difference between the peak of the current and the desired current limit.

Thus, a peak current limiter that limits a peak current of a power converter that produces a constant level thereof still presents unresolved design challenges. Accordingly, what is needed in the art is a design approach and related method to implement a controller that determines and limits a peak current for a power converter without compromising end-product performance and that can be advantageously adapted to high-volume manufacturing techniques.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by advantageous embodiments of the present invention, including a controller for a power converter and method of operating the same. In one embodiment, the controller includes a peak detector, coupled to a circuit element of the power converter, configured to produce a signal corresponding to a peak current through a circuit element. The controller also includes an adjustable reference circuit responsive to a difference between the signal and a reference signal corresponding to a desired peak current to produce a corrected signal corresponding to the peak current.

The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a schematic diagram of an embodiment of portions of a power converter that provides an environment for application of the present invention;

FIG. 2 illustrates a schematic diagram of an embodiment of a power converter including a controller constructed according to the principles of the present invention;

FIGS. 3 and 4 illustrate schematic diagrams of portions of the power converter of FIG. 2, introducing embodiments of a controller constructed according to the principles of the present invention;

FIG. 5 illustrates a graphical representation of selected waveforms demonstrating an exemplary operation of a power converter according to the principles of the present invention;

FIGS. 6 to 8 illustrate diagrams of embodiments of portions of a primary peak current circuit employable with a power converter constructed according to the principles of the present invention;

FIG. 9 illustrates a schematic diagram of an embodiment of portions of a power converter that provides an environment for application of the principles of the present invention;

FIG. 10 illustrates a schematic diagram of an embodiment of portions of a power converter including a controller constructed according to the principles of the present invention;

FIG. 11 illustrates waveform diagrams demonstrating an exemplary operation of the power converter of FIG. 10; and

FIGS. 12 to 16 illustrate schematic diagrams of embodiments of portions of power converters including a controller constructed according to the principles of the present invention.

Corresponding numerals and symbols in the different FIGUREs may refer to corresponding parts, and may not be redescribed in the interest of brevity after the first instance. The FIGUREs are drawn to illustrate the relevant aspects of exemplary embodiments.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the present exemplary embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to exemplary embodiments in a specific context, namely, a controller for a power converter (e.g., a flyback power converter) including a peak detector coupled to a circuit element (e.g., a power switch) of the power converter configured to produce a signal corresponding to a peak current through the power switch, and an adjustable reference circuit responsive to a difference between the signal and a reference signal corresponding to a desired peak current to produce a corrected signal corresponding to the peak current. The controller may further comprise a current limiter coupled to the peak detector and the adjustable reference circuit configured to disable conductivity of the power switch when the signal exceeds the corrected signal. While the principles of the present invention will be described in the environment of a power converter, any application that may benefit from a power converter including a motor drive or a power amplifier is well within the broad scope of the present invention.

Turning now to FIG. 1, illustrated is a schematic diagram of an embodiment of portions of a power converter (e.g., a quasi-resonant flyback power converter) that provides an environment for application of the present invention. A power train of the power converter includes a power switch Q1 coupled to a source of electrical power such as a dc input power source that provides an input voltage V_in, represented by a battery. The dc input power source supplies input power to an isolating transformer or transformer T1. The transformer T1 has primary winding with primary turns Np and a secondary winding with secondary turns Ns that are selected to provide an output voltage V_out with consideration of a resulting duty cycle and stress on power train components. The power switch Q1 (e.g., an n-channel metal-oxide semiconductor field-effect transistor (“MOSFET”)) is controlled by a controller (e.g., a pulse-width modulation (“PWM”) controller) 110 that periodically controls the power switch Q1 to be conducting for a duty cycle D with a frequency f_s.

When the power switch Q1 is switched off, energy stored in magnetizing and leakage inductances of transformer T1 causes a current to continue flowing in the primary winding of the transformer T1 that produces a charge in a primary resonant capacitor C_R1. A voltage built up across terminals of the primary resonant capacitor C_R1 contributes to resetting the magnetic flux in the core of transformer T1. The power switch Q1 conducts alternately with the switching frequency f_s in response to a gate-drive signal G_D produced by the PWM controller 110. The duty cycle D is adjusted by the PWM controller 110 to regulate an output characteristic of the power converter such as output voltage V_out, an output current I_out, or a combination of the two. Energy stored in the magnetizing inductance of transformer T1 also produces a pulsating forward current in a diode D1 that provides an output current I_out of the power converter. The ac voltage appearing on the secondary winding of the transformer T1 is rectified by the diode D1, and the dc component of the resulting waveform is coupled to the output of the power converter through a low-pass output filter formed with an output filter capacitor Cout to produce the output voltage V_out. A secondary resonant capacitor C_R2 is also frequently coupled across terminals of the diode D1 in a quasi-resonant flyback power converter to limit a peak inverse voltage produced across terminals of the diode D1 when the power switch Q1 is turned on.

In general, the duty cycle D of the power switch Q1 may be adjusted by the PWM controller 110 to maintain a regulation of the output voltage V_out or the output current I_out of the power converter. Those skilled in the art should understand that the PWM controller 110 may include an isolation device such as an optocoupler with its attendant cost to provide metallic isolation between the primary and secondary sides of the power converter.

Turning now to FIG. 2, illustrated is a schematic diagram of an embodiment of a power converter (e.g., a quasi-resonant flyback power converter) including a controller (e.g., a PWM controller) 210 constructed according to the principles of the present invention. The PWM controller 210 senses a current in a power switch Q1 employing a sense resistor R_sense coupled in series with a source of the power switch Q1, illustrated in FIG. 2 as a MOSFET. In an alternative embodiment, a current in the power switch Q1 may be sensed with a current-sense transformer, employing circuit structures well known in the art. The PWM controller 210 also senses a drain voltage V_drain of the power switch Q1. In an alternative embodiment, the PWM controller 210 senses an auxiliary voltage V_aux across an auxiliary winding N_aux of a transformer T1 in lieu of the drain voltage V_drain.

The PWM controller 210 regulates an output current I_out of the power converter. To calculate the primary peak current Ip through a primary winding of a transformer T1 to control an on time of the power switch Q1, the PWM controller 210 estimates a time interval t_sec of current flow in the secondary winding of the transformer T1 through a diode D1 to an output filter capacitor Cout, and the duration of one switching cycle t_s=1/f_s. The duration of one switching cycle t_s is generally known by the PWM controller 210 because the PWM controller 210 initiates the beginning of each switching cycle.

The average output current is calculated employing equation (1):I_out=I_p·(t_sec/t_s)·(Np/Ns)·η/2  (1)where Ip=primary peak current,

I_out=average output current that is desired to be controlled,

Np=number of primary turns of the primary winding of the transformer T1,

Ns=number of secondary turns of the secondary winding of the transformer T1, and

η=power conversion efficiency.

The primary and secondary turns Np, Ns are generally constant, and efficiency η is effectively constant over a range of output currents I_out and is generally known from modeling and prototype models of the power converter. Thus, the primary peak current Ip for a constant output current I_out can be represented by equation (2):Ip=(t_s/t_sec)·k  (2)where the parameter k is a constant representative of the particular power converter design. Thus, if the primary peak current Ip is controlled to be proportional to t_s/t_sec, the output current I_out of the power converter will be constant. For an explanation of the other components of the power converter, see the description of the power converter illustrated with respect to FIG. 1.

Turning now to FIG. 3, illustrated is a schematic diagram of portions of the power converter of FIG. 2, introducing an embodiment of a controller (e.g., the PWM controller) 210 constructed according to the principles of the present invention. The controller 210 includes first and second comparators CM1, CM2, an offset corrector 310, a primary peak current circuit 320, a summer 330 and a set-reset (“S-R”) flip-flop 340. To initiate conduction of the power switch Q1, the S-R flip-flop 340 turns on the power switch Q1 (via a gate-drive signal G_D) in response to a signal S_CM2 from the second comparator CM2 detecting a drain voltage V_drain of the power switch Q1 falling below a threshold voltage V_thresh, which occurs upon termination of current flow in the secondary winding of the transformer T1 of the power converter. Termination of current flow in the secondary winding of the transformer T1 is described further hereinbelow with reference to FIG. 5.

To terminate conduction of the power switch Q1, thereby setting the primary peak current Ip through the primary winding of the transformer T1 to the correct value to produce the desired output current I_out, the first comparator CM1 compares a sense voltage V_sense at a sense resistor R_sense in series with the power switch Q1 with an offset reference voltage Voref produced by a primary peak current circuit 320 and corrected by an offset corrector 310. The sense voltage V_sense at the sense resistor R_sense is proportional to the primary peak current Ip that flows through the primary winding of the transformer T1. The output of the first comparator CM1 is coupled to a reset input of the S-R flip-flop 340. When the sense voltage V_sense at the sense resistor R_sense exceeds the offset reference voltage Voref, the power switch Q1 is turned off by the action of a signal S_CM1 from the first comparator CM1 to the S-R flip-flop 340 and a gate-drive signal G_D from the S-R flip-flop 340 to the power switch Q1.

Two reference voltages are calculated according to equations (3) and (4):Vref=(I_out/η)(t_s/t_sec)R_sense*2  (3)Voref=Vref−Vofs  (4)wherein I_out corresponds to a desired output current of the power converter, η is the assumed power conversion efficiency, and Vofs is an offset voltage that compensates the generally unknown power converter delays. The primary peak current circuit 320 provides computation of the reference voltage Vref according to equation (3). The summer 330 provides subtraction according to equation (4). It should be understood that analog and/or digital circuits may perform the computation described by equation (3) in accordance with the primary peak current circuit 320. For example, an integrated circuit designated AD534 produced by Analog Devices, Inc. and described in data sheet entitled “Internally Trimmed Precision IC Multiplier,” 1999, which is incorporated herein by reference, can be employed to perform the calculation of equation (3).

The offset corrector 310 provides a mechanism to compensate for the uncertain delays in the power converter elements such as the first comparator CM1 and the turn-on time of the power switch Q1. The offset corrector 310 computes the value of the offset voltage Vofs to provide this compensation. When the sense voltage V_sense exceeds the reference voltage Vref, then the output of an offset comparator CM_OS provides a current to an offset capacitor C_OS through an offset diode D_OS and a first offset resistor R_OS1, thereby incrementing the voltage across terminals of the offset capacitor C_OS. The voltage across the terminals of the offset capacitor C_OS is continually decreased by a second offset resistor R_OS2. As a result, if the sense voltage V_sense (e.g., maximum sense voltage V_sense) at the sense resistor R_sense exceeds the reference voltage Vref during a switching cycle, then the offset voltage Vofs is increased. If the sense voltage V_sense (e.g., maximum sense voltage V_sense) at the sense resistor R_sense does not exceed the reference voltage Vref during a switching cycle, the offset voltage Vofs is slowly decreased. Thus, the offset voltage Vofs is a function of the reference voltage Vref and the sense voltage V_sense. In this manner, the output of the offset corrector 310 is continually adjusted so that the peak value of the sense voltage V_sense slightly exceeds the reference voltage Vref computed in the primary peak current circuit 320. The offset corrector 310 thereby compensates for uncertain delays in the power converter.

Turning now to FIG. 4, illustrated is a schematic diagram of portions of the power converter of FIG. 2, introducing an embodiment of a controller (e.g., the PWM controller) 210 constructed according to the principles of the present invention. In this embodiment, the offset voltage Vofs is detected with a peak-sensing circuit that employs a counter 430 to provide compensation and adjustment of a sense voltage V_sense (e.g., maximum sense voltage V_sense) at the sense resistor R_sense during each switching cycle. If an offset comparator CM_OS detects the sense voltage V_sense exceeds a reference voltage Vref during a switching cycle, then a counter logic 420 increments the counter 430. If the sense voltage V_sense does not exceed the reference voltage Vref during a switching cycle, then the counter logic 420 decrements the counter 430. A digital-to-analog (“D/A”) converter 440 converts the stored value in the counter 430 to an analog offset voltage Vofs, which is then coupled to a summer 330. As a result, the offset corrector 410 compensates for uncertain circuit delays. For an explanation of the other components of the controller, see the description of the controller illustrated with respect to FIG. 3.

Turning now to FIG. 5, illustrated is a graphical representation of selected waveforms demonstrating an exemplary operation of a power converter (e.g., the quasi-resonant flyback power converter of FIG. 2) according to the principles of the present invention. A waveform of a gate-drive signal G_D provides an on time t_on for a power switch Q1 with a switching period t_s. FIG. 5 also illustrates waveforms of a sense voltage V_sense of a sense resistor R_sense and a drain voltage V_drain of the power switch Q1. When the sense voltage V_sense exceeds an offset reference voltage Voref, the on time t_on of the power switch Q1 is terminated. When the power switch Q1 is turned off at the time t₁ and current is delivered to an output filter capacitor Cout through a diode D1 due to energy stored in the magnetizing inductance of a transformer T1, the drain voltage rises to a level:V_in+V_out·(Np/Ns).When the energy stored in the magnetizing inductance of transformer T1 is exhausted, the drain voltage V_drain, falls below a threshold voltage V_thresh at time t₂, and reaches a value such as a minimum value at time t₃. At the time t₃, the controller initiates a new switching cycle. The time interval beginning at the time t₁ and terminating at the time t₂ defines the time interval t_sec during which current flows through the diode D1 to an output of the power converter via the output filter capacitor Cout.

Turning now to FIGS. 6 and 7, illustrated are schematic diagrams of embodiments of a portion of a primary peak current circuit (see, e.g., FIGS. 3 and 4) employable with a power converter (e.g., the quasi-resonant flyback power converter of FIG. 2) constructed according to the principles of the present invention. Beginning with FIG. 6, a timing circuit may be incorporated into the primary peak current circuit and estimates a time interval t_sec during which an output current I_out is delivered to an output of the power converter via an output filter capacitor Cout due to energy stored in the magnetizing inductance of a transformer T1. A timing comparator CM_T compares a drain voltage V_drain, with a threshold voltage V_thresh as described above with respect to FIG. 5. When the drain voltage V_drain exceeds the threshold voltage V_thresh, the timing comparator CM_T provides current to a timing capacitor C_T through a timing diode D_T and a timing resistor R_T. Accordingly, the voltage across the timing capacitor C_T increases at a rate that may be represented by the equation:dV/dt=i_RT/C_T,wherein,

dV/dt is the rate at which the voltage across the timing capacitor C_T increases,

i_RT is the current through the timing diode D_T and the timing resistor R_T, which can be estimated from the output voltage of the timing comparator CM_T minus the voltage across the timing capacitor C_T and minus the forward voltage drop of the timing diode D_T, and

C_T in the equation above represents the capacitance of the timing capacitor C_T.

Thus, the timing capacitor C_T performs an integration of the current that flows thereto. Preferably, the R·C time constant of the timing resistor R_T and the timing capacitor C_T is long enough to obtain reasonably accurate integration of the current flowing into the timing capacitor C_T. A sample-and-hold circuit 620 acquires a voltage such as the maximum voltage across the timing capacitor C_T, which is proportional to the time interval t_sec. The sample-and-hold circuit 620 accordingly produces an estimate of the time interval t_sec. A control switch S1, illustrated in FIG. 6 as a MOSFET, is coupled to a gate-drive signal GD and periodically discharges the timing capacitor C_T to enable the integration performed in the timing capacitor C_T to start over (i.e., the control switch S1 resets the integration operation). A delay circuit 610 enables the sample-and-hold circuit 620 to acquire the voltage such as the maximum voltage across the timing capacitor C_T before the timing capacitor C_T is discharged by the control switch S1.

Additionally, and as illustrated in the timing circuit of FIG. 7, a constant current source CS may be employed in lieu of the timing resistor R_T to augment an accuracy of current control and a similar circuit as described herein may be employed to estimate a switching cycle t_s of a power switch Q1 of a power converter employing the primary peak current circuit (see, e.g., FIGS. 2 to 4). Assuming a timing circuit with a current source CS as described herein is employed to estimate the time interval t_sec and the switching cycle t_s, the values of the current source CS and the timing capacitor C_T should substantially match for purposes of low tolerance. While the absolute values of the time constants for both timing circuits (i.e., one timing circuit to estimate the time interval t_sec and another timing circuit to estimate the switching cycle t_s) may differ, the ratio of the time constants should be substantially constant. As a result, the timing circuits and primary peak current circuit may be embodied in an integrated circuit (e.g., an application specific integrated circuit) because matching components in such integrated circuits is quite achievable while still maintaining high absolute tolerances.

Turning now to FIG. 8, illustrated is a block diagram of an embodiment of a portion of a primary peak current circuit (see, e.g., FIGS. 3 and 4) employable with a power converter (e.g., the quasi-resonant flyback power converter of FIG. 2) configured to provide a reference voltage Vref in accordance with a switching cycle t_s of a power switch Q1 of the power converter and a time interval t_sec during which an output current I_out is delivered to an output of the power converter. The primary peak current circuit to provide the reference voltage Vref includes a switching cycle timing circuit 810 and a time interval timing circuit 820 analogous to the timing circuit illustrated and described with respect to FIGS. 6 and 7. The primary peak current circuit to provide the reference voltage Vref also includes a divider 830 and a limiter 840. The divider 830 multiples a constant “k” with a ratio of t_s/t_sec to provide an initial reference voltage Vrefi, wherein the constant “k” is expressed as a voltage as illustrated in equation (3) above. The limiter 840 thereafter limits a value of the initial reference voltage Vrefi to a predefined range to provide the reference voltage Vref. As a result, the reference voltage Vref is limited to prevent too high of a primary peak current during, for instance, a start up of the power converter when the values of the switching cycle t_s and the time interval t_sec are not available.

Thus, a controller for a power converter (e.g., a quasi-resonant flyback power converter) has been introduced that controls a power switch thereof. In one embodiment, the controller includes a primary peak current circuit configured to produce a reference voltage corresponding to a primary peak current through a primary winding of a transformer of a power converter, and an offset corrector configured to provide an offset voltage to compensate for delays in the power converter. The offset voltage may be a function of the reference voltage from the primary peak current circuit and a sense voltage from a sense resistor in series with the power switch. The offset corrector may include an offset comparator, an offset capacitor, an offset diode and an offset resistor or, alternatively, an offset comparator, a counter, counter logic and a digital-to-analog converter.

The controller also includes a summer configured to provide an offset reference voltage as a function of the reference voltage and the offset voltage, and a comparator configured to produce a signal to turn off the power switch coupled to the primary winding of the transformer as a function of the offset reference voltage. The comparator is configured to produce the signal to turn off the power switch when a sense voltage from a sense resistor in series with the power switch exceeds the offset reference voltage. The controller further includes a set-reset flip-flop configured to provide a gate drive signal to the power switch responsive to the signal from the comparator. The set-reset flip-flop is also configured to turn on the power switch responsive to a signal from another comparator detecting a drain voltage of the power switch falling below a threshold voltage.

In a related, but alternative embodiment, a primary peak current circuit of the controller includes a timing circuit configured to estimate a time interval when an output current is delivered to an output of the power converter. The primary peak current circuit also includes a divider configured to multiply a constant with a ratio of a switching frequency of the power switch and the time interval to provide an initial reference voltage. The constant may include a desired output current of the power converter divided by a power conversion efficiency of the power converter. The primary peak current circuit still further includes a limiter configured to limit a value of the initial reference voltage to a predefined range to provide a reference voltage corresponding to a primary peak current through the primary winding of the transformer of the power converter.

The timing circuit of the primary peak current circuit includes a comparator configured to provide a current to a timing capacitor when a drain voltage of the power switch exceeds a threshold voltage, wherein the timing capacitor is configured to perform an integration of the current. The primary peak current circuit also includes a sample-and-hold circuit configured to acquire a voltage across the timing capacitor that is proportional to and produces the estimate of the time interval, and a control switch configured to discharge the timing capacitor to enable the integration to start over as a function of a gate drive signal to the power switch. The primary peak current circuit still further includes a delay circuit configured to enable the sample-and-hold circuit to acquire the voltage across the timing capacitor before the timing capacitor is discharged by the control switch. The comparator is configured to provide the current to the timing capacitor through a timing resistor or a current source when the drain voltage of the power switch exceeds the threshold voltage. Additionally, the primary peak current circuit may include a timing circuit configured to estimate the switching frequency of the power switch.

Turning now to FIG. 9, illustrated is a schematic diagram of an embodiment of portions of a power converter (an exemplary flyback power converter) that provides an environment for application of the principles of the present invention. A power train of the power converter includes a power switch Q1 coupled to a source of electrical power such as a dc input power source that provides an input voltage V_in, represented in FIG. 9 by a battery. The dc input power source supplies input power to an isolating transformer or transformer T1. The transformer T1 is formed with a primary winding with primary turns Np and a secondary winding with secondary turns Ns that are selected to provide an output voltage V_out and an output current I_out with consideration of a resulting duty cycle and stress on power train components. The power switch Q1 (which may be formed as an n-channel MOSFET) is controlled by a controller (e.g., a PWM controller) formed with a comparator comp1 coupled to control logic CL that periodically controls the power switch Q1 to conduct for a duty cycle D with a frequency f_s to regulate, for example, the output voltage V_out. The control logic CL and other circuit elements are powered from a bias voltage source Vdd coupled to a bypass capacitor C2.

To limit a primary peak current in the primary winding of the transformer T1, a non-inverting input of comparator comp1 is coupled to a sense resistor R_sense in series with the power switch Q1 that produces a ramp voltage proportional to a current of the power switch Q1. The power switch Q1 is typically (but not necessarily) turned on by the control logic CL in response to a clock pulse. When a ramp voltage produced across the sense resistor R_sense exceeds a reference voltage (e.g., a constant reference voltage) Vrf that is coupled to the inverting input of the comparator comp1, the output voltage of comparator comp1 goes high, and the power switch Q1 is turned off by the control logic CL, which terminates the duty cycle D. In this manner, a current in the transformer T1 is limited to a peak level.

The circuit to limit the primary peak current in the primary winding of the transformer T1 generally operates with a modest, but significant difference between a peak value of a sensed current and the desired peak current due to logic and power switch circuit delays. A conventional technique that is employed to minimize the difference between the peak value of the sensed current such as a primary peak current in the primary winding of the transformer T1 and the desired peak current is to superimpose a variable dc offset voltage on the sensed voltage at the sense resistor R_sense. The variable dc offset voltage is generally proportional to the input voltage V_in. This can be done as illustrated in FIG. 9 with a voltage divider formed with a series circuit arrangement of voltage divider resistors R2, R3 coupled to the input voltage V_in of the power converter. The variable dc offset voltage produced by the voltage divider is functionally added to the reference voltage Vrf and is coupled to the inverting input of comparator comp1. A higher variable dc offset voltage would generally be produced by a higher input voltage V_in. Due to the variable dc offset voltage, the comparator comp1 sends a signal to the control logic CL to control a variable time before the sensed voltage at the sense resistor R_sense is higher than the reference voltage Vrf. The variable dc offset voltage is employed to turn off the power switch Q1 at a slightly earlier, but variable time. The variable dc offset voltage produced by the voltage divider compensates the effect of a more rapid rise of current in the power switch Q1 and/or a magnetic circuit element (e.g., the transformer T1) for a higher input voltage V_in to the power converter.

Another technique to minimize the difference between the peak of a sensed current and the desired current limit is described by Ralf Schroeder, in German patent application Publication Number DE 100 18 229, Application Number DE2000101822920000412, filed Apr. 12, 2000, which is incorporated herein by reference. In this technique, a sensed voltage at a sense resistor (e.g., the sense resistor R_sense illustrated in FIG. 9) is compared with a time-dependent reference voltage. The time-dependent reference voltage is low when the power switch such as the power switch Q1 illustrated in FIG. 9 is switched on and rises during the on time of the power switch. As a result, the voltage such as the sensed voltage produced across the sense resistor R_sense illustrated in FIG. 9 exceeds the reference voltage Vrf earlier if the input voltage V_in to the power converter is high because the slope of the current is steeper. If the slope of the reference voltage Vrf is adjusted to compensate the variable slope of the sensed current and the respective delays in down-stream circuit elements that control the power switch, the primary peak current of the primary winding of the transformer T1 can be controlled to be less dependent on the input voltage V_in.

Both of the techniques described above are dependent on delays in down-stream circuit elements and the slope of the sensed current. If these delays or the inductance of magnetic circuit elements varies due to component tolerances and aging and/or temperature changes, the peak of the current also changes. Although variation of the peak current is reduced, it is not entirely eliminated.

The first of the two techniques described above employs the two voltage-divider resistors R2, R3, one of which (resistor R3) is coupled to the input voltage V_in to the power converter. If the input voltage V_in is a high voltage relative to semiconductor processes employed to produce an integrated circuit in control logic, the voltage-divider resistors R2, R3 are not included within the integrated circuit unless the integrated circuit is formed with high-voltage capability. As a result, the voltage-divider resistors R2, R3 are formed as discreet resistors external to the integrated circuit, which increases size and cost of the power converter. The voltage-divider resistors R2, R3 also produce a power loss that is independent of load power, which increases the no-load input power to the power converter.

An alternative version of the first technique uses a lower voltage that is produced at a winding of the magnetic circuit element (e.g., the transformer) to generate the variable dc offset voltage. In this case, a high-voltage resistor is not needed, and the increase of the no-load input power is significantly reduced. This alternative version, however, is more expensive due to the additional winding that is required in the transformer.

Turning now to FIG. 10, illustrated is a schematic diagram of an embodiment of portions of a power converter (an exemplary flyback power converter) including a controller 1010 constructed according to the principles of the present invention. As introduced herein, the peak value of a sensed voltage produced by a sense resistor R_sense or other current-sensing circuit element such as a current-sense transformer in a controller 1010 is measured and stored by a peak detector. The peak detector is formed with a current sensor (sense resistor R_sense or other current-sensing circuit element), amplifier ampl1, diode D2, and capacitor C3 to produce a signal 1020 corresponding to a peak current through the sense resistor R_sense. An adjustable reference circuit in the controller 1010 formed with an inverting amplifier ampl2 responds to a difference between the signal 1020 produced by the peak detector and a reference signal (e.g., a constant reference voltage Vrf) to produce a corrected signal (a corrected reference voltage Vrf1).

The inverting amplifier ampl2 illustrated in FIG. 10 is formed with a compensation network including a resistor R2 and a feedback circuit element such as integrating feedback capacitor C4. The difference between the reference signal Vrf and the signal 1020 produced by the peak detector is amplified, integrated, and inverted to produce the corrected reference voltage Vrf1 that is coupled to an input of a comparator comp1. The comparator comp1 produces a signal 1030 that is coupled to control logic CL to turn off a power switch Q1 when the signal corresponding to the primary peak current through a component such as the primary winding of the transformer T1 or the power switch Q1 exceeds the corrected reference voltage Vrf1. As a result, the corrected reference voltage Vrf1 is adjusted until the peak value of the sensed voltage produced by the sense resistor R_sense is equal to the reference voltage Vrf, thereby substantially removing any error caused by unknown delays in logic or by delays in the power switch Q1. Thus, the offset corrector described previously hereinabove to provide an adjustable offset voltage to compensate for delays in a power converter to limit a primary peak current in a transformer, switch or other circuit element is applicable to many converter topologies.

To enable the signal (e.g., a voltage) 1020 from the peak detector to follow the peak value of the sensed voltage produced by a sense resistor R_sense when the corresponding peak current is reduced (e.g., if the input voltage V_in becomes lower), the capacitor C3 is at least partly discharged a short time before the peak occurs via a resistor R4 and a switch (a peak detector switch) S2. Whenever the power switch Q1 is switched on, the switch S2 is also switched on and the resistor R4 discharges energy from the capacitor C3. Thus, the peak detector includes the resistor R4 and the switch S2 whose conductivity is switched, without limitation, at a switching frequency of the power converter to provide a discharge path for the capacitor C3. The compensation network formed with the resistor R2 and the capacitor C4 can be adjusted to avoid unwanted oscillations. The compensation network can be constructed with further refinements if the response time of the circuit must be very fast.

Different from the circuit illustrated in FIG. 9, a bias voltage return connection V_ss of the control logic CL or at least of the output driver thereof should be connected to the power switch Q1 in a manner so that the gate-drive signal (e.g., current) of the power switch Q1 does not flow through the sense resistor R_sense and cause an error in the measurement of the peak current. The sensed voltage at the sense resistor R_sense is measured negative with respect to ground of the control logic CL so the gate-drive signal does not go through the sense resistor R_sense.

To avoid magnetic circuit element (e.g., transformer) saturation, or to limit a peak current through a semiconductor device, the peak current flowing therethrough should not exceed a certain current level dependent on the design of the magnetic circuit element or the semiconductor device. Accordingly, the corrected reference voltage Vrf1 should be limited, for example, to a level that is not higher than the reference signal (e.g., the constant reference voltage Vrf).

Turning now to FIG. 11, illustrated are waveform diagrams demonstrating an exemplary operation of the power converter of FIG. 10. The diagrams represent the conduction period of the power switch Q1 and a sensed voltage V(Ip) through the sense resistor R_sense representative of the primary peak current Ip through the transformer T1 or other circuit element (e.g., the power switch Q1). As a result of the operation of the controller 1010, the control logic CL turns off the power switch Q1 when the signal (sensed voltage V(Ip)) corresponding to the primary peak current through a component such as the primary winding of the transformer T1 or the power switch Q1 exceeds the corrected reference voltage Vrf1. Due to circuit delays, the power switch Q1 is ultimately turned off when then the sensed voltage V(Ip) is substantially equal to the reference voltage Vrf. The principles as described herein apply to the controllers as introduced below.

Turning now to FIG. 12, illustrated is a schematic diagram of an embodiment of portions of a power converter (an exemplary flyback power converter) including a controller 1200 constructed according to the principles of the present invention. In the embodiment as illustrated in FIG. 12, the corrected reference voltage Vrf1 produced by the adjustable reference circuit is limited by two limiting diodes D3, D4. The limiting diode D4 is in an output path of the adjustable reference circuit and the limiting diode D3 is in a feedback path of the adjustable reference circuit. The limiting diode D3 couples the output voltage of amplifier ampl2 directly to the negative input of amplifier ampl2 when the output voltage of amplifier ampl2 is higher than the reference voltage Vrf plus the forward voltage of limiting diode D3. With inclusion of the limiting diode D3, the output voltage of amplifier ampl2 cannot get higher than the reference voltage Vrf plus the forward voltage of the limiting diode D3.

With inclusion of limiting diode D4 and resistor R3, the corrected reference voltage Vrf1 equals the output voltage of ampl2 minus the forward voltage of limiting diode D4. If limiting diodes D3, D4 have similar forward voltage drops, the maximum value Vrf1_max of the corrected reference voltage Vrf1 is substantially equal to the reference voltage Vrf, as illustrated below by Equation (5):Vrf1_max=Vrf+V(D3)−V(D4)  (5)If the forward voltage drops V(D3), V(D4) of the limiting diodes D3, D4 are equal, then the maximum value Vrf1_max of the corrected reference voltage Vrf1 will be equal to the reference voltage Vrf. Thus, the corrected reference voltage Vrf1 is limited by the adjustable reference circuit by inclusion of a diode in an output path of the circuit and another diode, preferably a matched diode, in a feedback circuit arrangement. The same matching effect can be achieved with two matching FETs in place of the limiting diodes D3, D4, as illustrated and described later hereinbelow with reference to the controller 1500 of FIG. 15.

The output of the peak detector does not always exactly represent the peak value of the sensed voltage produced across the sense resistor R_sense or by another current-sensing circuit element. A capacitor storing the output voltage (e.g., the corrected reference voltage Vrf1) in accordance with the controller as described herein should be slightly discharged before the next peak is measured. This is done with the switch S2 (whose conductivity is substantially synchronized with, or otherwise coordinated with, a switching frequency of power switch Q1) and the resistor R4 as illustrated in FIGS. 10 and 12. By employing this discharging technique, however, the average output voltage in accordance with the controller is slightly lower than the peak value of the sensed voltage. Therefore, the peak value of the sensed voltage will be limited to a slightly higher level than the reference voltage Vrf.

Turning now to FIG. 13, illustrated is a schematic diagram of an embodiment of portions of a power converter (an exemplary flyback power converter) including controller 1300 constructed according to the principles of the present invention. In the embodiment as illustrated in FIG. 13, further reduction of the error of regulating the peak value of the sensed voltage (again, across the sense resistor R_sense) to the reference voltage Vrf is achieved by including a switch S3 and a capacitor C5 in the circuit. The switch S3 is off when the switch S2 is on. Accordingly, the capacitor C5 is disconnected from the capacitor C3 most of the time when the voltage at the capacitor C3 is lower than the peak value of the sensed voltage. The effect of including the switch S3 is to cause the average voltage at the capacitor C5 to equal more exactly the peak value of the sensed voltage than does the voltage at the capacitor C3. As a result, the difference between the sensed voltage and the reference voltage Vrf is reduced. A further benefit of this circuit is the resistance of the resistor R4 can be reduced without producing a significant effect on the average voltage at the capacitor C5. This enables a faster response time when the peak current is being reduced.

Turning now to FIG. 14, illustrated is a schematic diagram of an embodiment of portions of a power converter (an exemplary flyback power converter) including controller 1400 constructed according to the principles of the present invention. In the embodiment illustrated in FIG. 14, a delay is incorporated in the circuit to further reduce the error between the peak value of the sensed voltage and the reference voltage Vrf. This delay ensures that a capacitor C5 is connected to the capacitor C3 only after the peak of the sensed voltage has occurred. An additional driver dry ensures that the capacitor C3 is not discharged while the capacitor C5 is charged. This ensures that the voltage at the capacitor C5 equals more closely the peak value of the sensed voltage.

Turning now to FIG. 15, illustrated is a schematic diagram of an embodiment of portions of a power converter (an exemplary flyback power converter) including controller 1500 constructed according to the principles of the present invention. In the embodiment illustrated in FIG. 15, the diodes D2, D3, D4 are replaced by switched (e.g., field-effect transistors) M1, M2, M3. Bipolar transistors could be used in place of these field-effect transistors. The field-effect transistor M2 is in an output path of the adjustable reference circuit and the field-effect transistor M3 is in a feedback path of the adjustable reference circuit. The diode D2 can be omitted if the lower half of the push-pull driver of amplifier ampl1 is removed. Only the upper half of the driver functionally remains in the circuit with inclusion of the field-effect transistor M1. Since the field-effect transistor M1 is a source follower, it cannot pull down its output (source) voltage. Therefore, the diode D2 is no longer necessary.

The limiting diode D3 can be replaced by the field-effect transistor M3 if the transistor M3 matches the transistor M2 and the diode D4 is also removed. The field-effect transistor M2 is the upper half of the push-pull output driver of amplifier ampl2. The resistor R3 replaces the lower half of the push-pull driver to simplify the implementation. The resistor R3 can be replaced by the lower half of the push-pull driver without a negative effect on its operation.

Turning now to FIG. 16, illustrated is a schematic diagram of an embodiment of portions of a power converter (an exemplary flyback power converter) including controller 1600 constructed according to the principles of the present invention. In the embodiment illustrated in FIG. 16, a comparator comp2 is employed to detect if the desired peak current through the power switch Q1 was reached during a switching cycle. If not, the corrected reference voltage Vrf1 of the controller is increased. Otherwise, the corrected reference voltage Vrf1 is decreased by logic 1610 and up-down converter 1620 and analog-to-digital converter 1630 (as part of an adjustable reference circuit). By implementing an appropriate step size and logic, a frequency jitter can be implemented to improve EMI. Up-down converter 1620 may be formed with digital logic such as a microprocessor.

The field-effect transistor previously described to implement power switch Q1 is now replaced with a bipolar switch, but a field-effect transistor can be substituted. Several analog circuit elements illustrated in FIGS. 9 through 16 have been replaced with digital components. In particular, amplifier ampl1 is replaced by comparator comp2, and amplifier ampl2 is replaced by digital up-down counter 1620, logic circuit elements 1610, and digital-to-analog converter 1630. A transformer TX1 coupled to the power switch Q1 includes primary windings P1, P2, and a secondary winding S1.

Whenever the desired peak current level in the switch Q1 is reached during a switching period (as indicated by comparator comp2 output going high), the up-down counter 1620 counts down. If the desired peak current level is not reached, the up-down counter 1620 counts up. The logic circuit elements in the logic block 1610 can determine if the counter 1620 counts one or more digits per switching cycle. In an embodiment, the up-down counter 1620 counts one step per switching cycle (e.g., such a one-step process is slow but precise). In another embodiment, if two or more counts go into the same direction, then the number of counter increments per period is increased. This embodiment produces a faster response, but causes a larger output current ripple and frequency variation. Counting up of the up-down counter 1620 is disabled when all of its bits are high, and counting down of the up-down counter 1620 is disabled when all of its bits are low. The digital output of up-down counter 1620 is converted to the corrected reference voltage Vrf1 by digital-to-analog converter 1630 to produce the corrected reference voltage Vrf1. Preferably, the digital-to-analog conversion is performed with a fixed offset to reduce the required number of bits. The corrected reference voltage Vrf1 is coupled to the non-inverting input of comparator comp1, which generates a signal Is for the PWM control block to switch off power switch Q1 with the proper timing when the desired peak current level in power switch Q1 is reached.

Thus, as introduced herein, a controller is employed with an adjustable reference circuit to produce a corrected reference voltage to enable a current limiter to disable conductivity of a power switch when a voltage corresponding to a peak current through a power switch or other circuit element exceeds the corrected reference voltage. The technique can be advantageously employed to accurately limit a peak current in a circuit element such as a transformer at a desired level independent of variations in power converter input voltage, operating conditions, and/or tolerances and variations of delays and inductances of magnetic circuit elements. The technique can also be employed to reduce an output ripple of a switch-mode power converter. The technique can be employed to provide precise output current control without a secondary-side current monitor. Cost and no-load input power consumption can be reduced because the controller including the current limiter do not require a resistor to be connected to a high voltage such as an input voltage to the power converter.

Those skilled in the art should understand that the previously described embodiments of a controller for a power converter configured to control a power switch and related methods of operating the same are submitted for illustrative purposes only. While a controller has been described in the environment of a power converter, these processes may also be applied to other systems such as, without limitation, a power amplifier or a motor controller, which are broadly included herein in the term “power converter.”

For a better understanding of power converters, see “Modern DC-to-DC Power Switch-mode Power Converter Circuits,” by Rudolph P. Severns and Gordon Bloom, Van Nostrand Reinhold Company, New York, N.Y. (1985) and “Principles of Power Electronics,” by J. G. Kassakian, M. F. Schlecht and G. C. Verghese, Addison-Wesley (1991).

Also, although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. A controller employable with a power converter, comprising: a peak detector, coupled to a circuit element of said power converter, configured to produce a signal corresponding to a peak current through said circuit element; andan adjustable reference circuit responsive to a difference between said signal and a reference signal corresponding to a desired peak current to produce a corrected reference signal corresponding to said peak current.

2. The controller as recited in claim 1 wherein said circuit element is a power switch and said controller further comprises a comparator coupled to said peak detector and said adjustable reference circuit configured to disable conductivity of said power switch when said signal exceeds said corrected reference signal.

3. The controller as recited in claim 1 wherein said peak detector comprises a current sensor, an amplifier, a diode, and a capacitor.

4. The controller as recited in claim 3 wherein said current sensor comprises a resistor.

5. The controller as recited in claim 3 wherein said peak detector further comprises a resistor and a peak detector switch with conductivity switched at a frequency related to a switching frequency of said power converter to provide a discharge path for said capacitor.

6. The controller as recited in claim 1 wherein said adjustable reference circuit comprises an amplifier including a feedback capacitor.

7. The controller as recited in claim 1 wherein said adjustable reference circuit comprises digital logic and a digital-to-analog converter.

8. The controller as recited in claim 7 wherein said digital logic comprises an up-down counter.

9. The controller as recited in claim 1 wherein said corrected reference signal is limited by a first diode in an output path of said adjustable reference circuit and a second diode in a feedback path of said adjustable reference circuit.

10. The controller as recited in claim 1 wherein said corrected reference signal is limited by a first switch in an output path of said adjustable reference circuit and a second switch in a feedback path of said adjustable reference circuit.

11. A method employable with a power converter, comprising: producing a signal corresponding to a peak current through a circuit element of said power converter;producing a reference signal corresponding to a desired peak current associated with said circuit element; andproduce a corrected reference signal corresponding to said peak current responsive to a difference between said signal and said reference signal.

12. The method as recited in claim 11 wherein said circuit element is a power switch and further comprising disabling conductivity of said power switch when said signal exceeds said corrected reference signal.

13. The method as recited in claim 11 wherein said corrected reference signal is produced with digital logic and a digital-to-analog converter.

14. The method as recited in claim 11 further comprising limiting said corrected reference signal with a feedback circuit.

15. A power converter, comprising: a circuit element coupled to an input of said power converter; anda controller, coupled to said circuit element, comprising: a peak detector configured to produce a signal corresponding to a peak current through said circuit element, andan adjustable reference circuit responsive to a difference between said signal and a reference signal corresponding to a desired peak current to produce a corrected reference signal corresponding to said peak current.

16. The power converter as recited in claim 15 wherein said circuit element is a power switch and said controller further comprises a comparator coupled to said peak detector and said adjustable reference circuit configured to disable conductivity of said power switch when said signal exceeds said corrected reference signal.

17. The power converter as recited in claim 15 wherein said peak detector comprises a current sensor, an amplifier, a diode, and a capacitor.

18. The power converter as recited in claim 15 wherein said adjustable reference circuit comprises an amplifier including a feedback capacitor.

19. The power converter as recited in claim 15 wherein said adjustable reference circuit comprises digital logic and a digital-to-analog converter.

20. The power converter controller as recited in claim 15 wherein said corrected reference signal is limited by a first diode or a first switch in an output path of said adjustable reference circuit and a second diode or a second switch in a feedback path of said adjustable reference circuit.