Patent Application
20240364222
This application claims the priority of Chinese patent application number 202310486048.7, filed on Apr. 28, 2023, the entire contents of which are incorporated herein by reference.
The present invention relates to design of power converters and, in particular to, a controller, an isolated power converter and a control method for the isolated power converter.
Most flyback isolated power supplies are optical coupling-based ones mainly featuring a simplified secondary side, which, for example, can be implemented simply by a TL431 device. These optical coupling-based power supplies are disadvantageous in the occurrence of optical attenuation and inferior dynamic response compared with ripple-based ones. Despite better dynamic response than that of optical coupling-based ones, a secondary side of a ripple-based flyback isolated power supply requires a magnetic or capacitive coupling device for coupling a control signal to a primary-side regulator. As both magnetic and capacitive coupling are driven by electric power, during startup, energy must be transferred to the secondary side by a primary-side MOS under the control of the primary-side regulator. A secondary-side regulator can start normal operation to control a switch for the primary-side MOS to transfer energy to the secondary side, only after a voltage across a bypass capacitor in a secondary-side chip reaches a predetermined value.
A startup process of existing isolated power converters involves: connecting with an AC power source; rising of a power supply voltage of the primary-side chip; the primary-side chip starting operation and control of the primary-side MOS; generation of a voltage in a secondary-side winding, which supplies power to the secondary-side chip through a pin Forw; rising of a power supply voltage of the secondary-side chip; and the secondary-side chip starting operation and control of the primary-side MOS.
However, this process is associated with the disadvantages as follows: if the secondary-side chip has great VCC capacitance or a small high-voltage current through the pin Forw, overshooting of the output voltage tends to occur during startup.
It is an objective of the present invention to provide a controller, an isolated power converter and a control method, which can prevent an output voltage overshoot during startup.
In a first aspect of the present invention, there is provided a controller for use with an isolated power converter, the controller including a primary-side regulator and a secondary-side regulator, the secondary-side regulator including a secondary-side regulation signal generation module, which receives a feedback signal of an output voltage of the isolated power converter, generates a first control signal and couples the first control signal to the primary-side regulator, the primary-side regulator including:
a primary-side regulation (PSR) module, which receives a voltage signal across a winding in the isolated power converter and generates a second control signal for controlling a state of the primary-side power transistor, thereby executing a PSR mode;
a follow-up secondary-side regulation (SSR) module, which receives the first control signal and generates a third control signal for controlling the state of the primary-side power transistor, thereby executing an SSR mode; and a regulation switching module, which receives the first control signal and thereby executes a switching of the primary-side regulator between the PSR and SSR modes.
Optionally, the PSR module may receive the voltage signal across two terminals of an auxiliary winding in the isolated power converter, which is coupled to a primary-side winding in the isolated power converter. Alternatively, the PSR module may receive the voltage signal across two terminals of the primary-side winding in the isolated power converter.
Optionally, the PSR module may include:
Optionally, the primary-side regulator may include:
Optionally, the secondary-side regulation signal generation module may include:
Optionally, the secondary-side regulation signal generation module may include:
Optionally, the follow-up SSR module may include:
Optionally, the follow-up SSR module may include:
Optionally, the secondary-side regulation signal generation module may include:
Optionally, the secondary-side regulation signal generation module may include:
Optionally, the follow-up SSR module may include a second drive generator module, which receives the first control signal and generates the third control signal for controlling the state of the primary-side power transistor.
Optionally, when the primary-side regulator is in the PSR mode, upon the regulation switching module receiving the first control signal that is valid, then the primary-side regulator may switch from the PSR mode to the SSR mode, wherein when the primary-side regulator is in the SSR mode, if the regulation switching module does not receive the first control signal that is valid within a predetermined period of time, then the primary-side regulator switches from the SSR mode to the PSR mode.
Optionally, the PSR module may enable the PSR mode, in which the output voltage rises up to a first reference value, wherein the follow-up SSR module executes the SSR mode, in which the output voltage rises up to a second reference value, and wherein the first reference value is not greater than the second reference value.
In a second aspect of the present invention, there is provided an isolated power converter including the controller as defined above.
In a third aspect of the present invention, there is provided a control method for an isolated power converter, which includes:
In summary, the present invention provides a controller, an isolated power converter and a control method. The controller includes a primary-side regulator and a secondary-side regulator. The secondary-side regulator includes a secondary-side regulation signal generation module, which receives a feedback signal of an output voltage of the isolated power converter, generates a first control signal and couples the first control signal to the primary-side regulator. The primary-side regulator includes a PSR module, which receives a voltage signal across a winding of the isolated power converter and generates a second control signal for controlling a state of the primary-side power transistor, thereby executing a PSR mode. The primary-side regulator also includes a follow-up SSR module, which receives the first control signal and generates a third control signal for controlling the state of the primary-side power transistor, thereby executing an SSR mode. The primary-side regulator also includes a regulation switching module, which receives the first control signal and thereby allows a switching of the primary-side regulator between the PSR and SSR modes. During startup of the isolated power converter, the PSR mode is first enabled by the PSR module, and a mode switching is then caused by the regulation switching module to allow the follow-up SSR module to enable the SSR mode. This can avoid overshooting of the output voltage during startup.
Those of ordinary skill in the art would appreciate that the accompanying drawings are provided to facilitate a better understanding of the present invention and do not limit the scope thereof in any sense, in which:
In these figures: 10—secondary-side regulator; 11—secondary-side regulation signal generation module; 20—primary-side regulator; 21—PSR module; 22—follow—up SSR module; 23—regulation switching module; 100—isolated power converter; 101—input terminal; 102—output terminal; 103—isolated transformer; 104—primary-side winding; 105—secondary-side winding; 106—auxiliary winding; 107—primary-side power transistor; 108—clamp circuit; 109—synchronous rectification circuit; 110—output capacitor; 111—coupler; 112—node; 113—second comparator; 114—first transmitter; 115—second operational amplifier; 116—second frequency control module; 117—second transmitter; 118—second logic circuit; 119—timing circuit; 120—third transmitter; 211—sample-and-hold module; 212—first operational amplifier; 213—first frequency control module; 214—turn-off control module; 215—first drive generator module; 2151—first comparator; 2152—first logic circuit; 221—frequency-based on-time control circuit; 222—second drive generator module.
Objectives, advantages and features of the present invention will become more apparent upon reading the following more detailed description of specific embodiments thereof with reference to the accompanying drawings. Note that the figures are provided in a very simplified form not necessarily drawn to exact scale and for the only purpose of facilitating easy and clear description of the embodiments. In addition, the structures shown in the figures are usually part of actual structures. In particular, as the figures tend to have distinct emphases, they are often drawn to different scales.
As used herein, the singular forms “a”, “an” and “the” include plural referents, unless the context clearly indicates otherwise. As used herein, the term “or” is generally employed in the sense of “and/or”, unless the context clearly indicates otherwise. As used herein, the term “a number of” is generally employed in the sense of “at least one”, unless the context clearly indicates otherwise. As used herein, the term “at least two” is generally employed in the sense of “two or more”, unless the context clearly indicates otherwise. Additionally, the use of the terms “first”, “second” and “third” herein is intended for illustration only and is not to be construed as denoting or implying relative importance or as implicitly indicating a numerical number of the referenced items. Accordingly, defining an item with “first”, “second” or “third” is an explicit or implicit indication of the presence of one or at least two such items.
In principle, the present invention seeks to provide a controller, an isolated power converter and a control method, which can prevent overshooting of an output voltage during startup of an isolated power converter.
The isolated power converter 100 includes an isolated transformer 103, the isolated transformer 103 includes a primary-side winding 104, a secondary-side winding 105 and an auxiliary winding 106. The isolated transformer 103 provides electrical isolation between the primary-side circuit and the secondary-side circuit of the isolated power converter 100.
The isolated power converter 100 further includes a primary-side regulator 20, a secondary-side regulator 10 and a primary-side power transistor 107. The primary-side regulator 20, the secondary-side regulator 10 and the primary-side power transistor 107 may be all incorporated in an integrated circuit (IC) package.
In one embodiment, in the IC package, the first and second IC chips may be encapsulated in an encapsulation body. The encapsulation body may be an enclosure or plastic film that wraps or encloses one or more IC chips and part of a lead frame. The first IC chip may include the primary-side regulator 20 and the primary-side power transistor 107, and the second IC chip may include the secondary-side regulator 10.
In an alternative embodiment, the IC package may include a first IC chip including the primary-side power transistor 107, a second IC chip including the primary-side regulator 20 and a third circuit chip including the secondary-side regulator 10.
The chip including the primary-side regulator 20 is electrically isolated from the chip including the secondary-side regulator 10. In this way, the secondary-side regulator 10 is electrically isolated from the primary-side regulator 20 and the primary-side power transistor 107. Although the primary-side regulator 20, the secondary-side regulator 10 and the primary-side power transistor 107 have been exemplified as being included in a single IC package, in other embodiments, one or more of the primary-side regulator 20, the secondary-side regulator 10 and the primary-side power transistor 107 may be included in an IC package.
The primary-side regulator 20 is coupled to primary-side circuit components in the isolated power converter 100, such as the primary-side power transistor 107 and a clamp circuit 108. The secondary-side regulator 10 is coupled to secondary-side circuit components in the isolated power converter 100. For example, the secondary-side regulator 10 is coupled to the secondary-side winding 105, the output terminal 102, a synchronous rectification circuit 109 and other circuit components. The primary-side regulator 20 and the secondary-side regulator 10 control the circuitry of the isolated power converter 100 and hence energy transfer from the input terminal 101 to the output terminal 102.
Although the primary-side regulator 20 and the secondary-side regulator 10 are electrically isolated from each other, the secondary-side regulator 10 can transfer a control signal to the primary-side regulator 20. For example, an isolated coupler 111 (e.g., a magnetic or capacitive coupling element) may be used to couple or transfer a control signal to the primary-side regulator 20. The primary-side power transistor 107 may be a high-voltage power switch. In one embodiment, the primary-side power transistor 107 may be a power metal-oxide-semiconductor field-effect transistor (MOSFET). During operation, the primary-side regulator 20 controls a current through the primary-side power transistor 107 and the primary-side winding 104. In general, the primary-side power transistor 107 may be in an ON state (e.g., serving as a turned-on switch) or an OFF state (e.g., as a turned-off switch), depending on a switch drive signal generated by the primary-side regulator 20.
The clamp circuit 108 is coupled to the primary-side winding 104 of the isolated transformer 103. As a result, a maximum voltage on the primary-side power transistor 107 can be limited during transitions of the primary-side power transistor 107 between the ON and OFF states. In one embodiment, in response to a transition of the primary-side power transistor 107 from the ON state to the OFF state, the synchronous rectification circuit 109 is turned on under the control of the secondary-side regulator 10, allowing efficient charging of the output capacitor 110.
In this embodiment, the secondary-side regulator 10 includes a secondary-side regulation signal generation module 11, the secondary-side regulation signal generation module 11 receives a feedback signal of the output voltage of the isolated power converter 100, generates a first primary-side power transistor control signal Vcontrol and couples the first control signal to the primary-side regulator 20.
The secondary-side regulator 10 includes multiple terminals connected to the secondary-side circuit. In
The primary-side regulator 20 includes a primary-side regulation (PSR) module 21, a follow-up secondary-side regulation (SSR) module and a regulation switching module 23. The PSR module 21 receives a voltage signal from the winding of the isolated power converter 100 and generates a second control signal for controlling the state of the primary-side power transistor 107, thereby executing a PSR mode. The follow-up SSR module 22 receives the first control signal and generates a third control signal for controlling the state of the primary-side power transistor 107, thereby executing an SSR mode. The regulation switching module 23 receives the first control signal and thereby executes a switching of the primary-side regulator 20 between the PSR and SSR modes.
It is to be noted that the PSR module 21 generates the second control signal for controlling the state of the primary-side power transistor 107 and the follow-up SSR module 22 generates the third control signal for controlling the state of the primary-side power transistor 107. Accordingly, in
During startup of the isolated power converter 100 in this embodiment, at first, the PSR module 21 generates the second control signal that controls the state of the primary-side power transistor 107 and thereby executes the PSR mode. After that, the regulation switching module 23 performs a mode switching based on the first control signal that it receives. As a result, the follow-up SSR module 22 generates the third control signal that controls the state of the primary-side power transistor 107 and thereby executes the SSR mode. That is, during startup of the isolated power converter 100, it operates first in the PSR mode and then in the SSR mode. This can prevent overshooting of the output voltage during the process of startup.
In one embodiment, referring to
The PSR module 21 further includes a first drive generator module 215. Alternatively, the first drive generator module 215 may be included in the primary-side regulator 20. The first drive generator module 215 receives the primary-side frequency control signal PSR_fs, the primary-side on-time control signal PSR_Vlimit and a primary-side current sample signal Vcs. Moreover, it provides a turn-on instruction to the primary-side power transistor based on the primary-side frequency control signal PSR_fs and a turn-off instruction to the primary-side power transistor 107 based on the primary-side on-time control signal PSR_Vlimit and the primary-side current sample signal Vcs. Further, it outputs the second control signal PSR_Gate to the primary-side power transistor 107.
Specifically, the voltage signal Vdeg is transmitted to an input terminal of the sample-and-hold module 211, and the output voltage sample signal is output from an output terminal of the sample-and-hold module 211 to an inverting input terminal of the first operational amplifier 212. The first reference value Vref1 is input to a non-inverting input terminal of the first operational amplifier 212, and the primary-side amplified error signal Comp_PSR is output from an output terminal of the first operational amplifier 212 to an input terminal of the first frequency control module 213 and an input terminal of the turn-off control module 214. The primary-side frequency control signal PSR_fs is output from an output terminal of the first frequency control module 213 to an input terminal of the first drive generator module 215 to control the frequency of the primary-side power transistor 107, that is, to control a turn-on timing of the primary-side power transistor 107. The primary-side on-time control signal PSR_Vlimit is output from an output terminal of the turn-off control module 214 to another input terminal of the first drive generator module 215 to control the on-time of the primary-side power transistor 107, that is, to control a turn-off timing of the primary-side power transistor 107. The second control signal PSR_Gate is output from an output terminal of the first drive generator module 215 to control turn-on and turn-off of the primary-side power transistor 107.
Specifically, the primary-side current sample signal Ves is input to a non-inverting input terminal of the first comparator 2151, and the primary-side on-time control signal PSR_Vlimit is input to an inverting input terminal of the first comparator 2151. The first comparison result is output from an output terminal of the first comparator 2151 to a reset terminal R of the flip-flop. The primary-side frequency control signal PSR_fs is input to a set terminal of the flip-flop, and the second control signal PSR_Gate is output from an output terminal of the flip-flop. The second control signal PSR_Gate controls turn-on and turn-off timings of the primary-side power transistor 107 and hence the state of the primary-side power transistor 107, thereby executing the PSR mode.
For example, when the primary-side current sample signal Vcs has a higher level than the primary-side on-time control signal PSR_Vlimit, a high level is output from the output terminal of the first comparator 2151 to a reset terminal R of the first logic circuit 2152, and a low level is output from an output terminal of the first logic circuit 2152. As a result, the primary-side power transistor 107 is turn off.
In the SSR mode, the secondary-side regulator includes the secondary-side regulation signal generation module, receives a feedback signal of the output voltage of the isolated power converter, generates the first control signal and couples the first control signal to the primary-side regulator. The primary-side regulator includes the follow-up SSR module, receives the first control signal and generates the third control signal that controls the state of the primary-side power transistor. The first control signal Vcontrol may contain only a signal indicating a turn-on timing of the primary-side power transistor. At the secondary side, a comparator or error amplifier may produce a turn-on signal for the primary-side power transistor. After the turn-on timing is received at the primary side, a timing circuit or frequency-based on-time control circuit may produce a turn-off signal.
In a first example, the secondary-side regulation signal generation module 11 includes a second comparator, which compares the feedback signal with a second reference value and outputs a second comparison result. The first control signal indicating a turn-on timing of the primary-side power transistor is produced from the second comparison result. In a second example, the secondary-side regulation signal generation module 11 includes a second operational amplifier and a second frequency control module. The second operational amplifier amplifies an error between the feedback signal and the second reference value and outputs a secondary-side amplified error signal. The second frequency control module receives the secondary-side amplified error signal and outputs the first control signal that indicates the turn-on timing of the primary-side power transistor.
In any of the first and second examples, the follow-up SSR module 22 may include a frequency-based on-time control circuit and a second drive generator module. The frequency-based on-time control circuit may receive the first control signal and output a secondary-side on-time control signal for controlling the on-time of the primary-side power transistor. The second drive generator module may receive the first control signal, the secondary-side on-time control signal and the primary-side current sample signal and output the third control signal to the primary-side power transistor.
In any of the first and second examples, the follow-up SSR module 22 may include a timing circuit and the second drive generator module. The timing circuit may receive the first control signal and output, after a predetermined period of time elapses after the primary-side power transistor is turned on under the action of the first control signal, the secondary-side on-time control signal for controlling the on-time of the primary-side power transistor. The second drive generator module may receive the first control signal and the secondary-side on-time control signal and output the third control signal to the primary-side power transistor.
In some other examples, the first control signal Vcontrol may include not only a signal for generating a turn-on timing of the primary-side power transistor but also a signal for generating a turn-off timing of the primary-side power transistor. At the primary side, a comparator or error amplifier may produce a turn-on signal for the primary-side power transistor, and a timing circuit may produce a turn-off signal for the primary-side power transistor. That is, differing from the above example, the turn-off signal may be produced by the timing circuit.
In a first example, the secondary-side regulation signal generation module 11 includes a second comparator, a timing circuit and a second logic circuit. The second comparator compares the feedback signal with a second reference value and outputs a second comparison result indicating a turn-on timing of the primary-side power transistor. The timing circuit starts a timer based on the turn-on timing of the primary-side power transistor. After the elapse of a predetermined period of time, it outputs a secondary-side on-time control signal that controls the on-time of the primary-side power transistor. The second logic circuit generates the first control signal based on both the second comparison result and the secondary-side on-time control signal.
In a second example, the secondary-side regulation signal generation module 11 includes a second operational amplifier, a second frequency control module, a timing circuit and a second logic circuit. The second operational amplifier amplifies an error between the feedback signal and the second reference value and outputs a secondary-side amplified error signal. The second frequency control module receives the secondary-side amplified error signal and outputs a second frequency control signal indicating a turn-on timing of the primary-side power transistor. The timing circuit starts a timer based on the turn-on timing of the primary-side power transistor and outputs, after the elapse of a predetermined period of time, a secondary-side on-time control signal that controls the on-time of the primary-side power transistor. The second logic circuit produces the first control signal based on the second frequency control signal and the secondary-side on-time control signal.
In any of the first and second examples, the follow-up SSR module 22 may include a second drive generator module, the second drive generator module receives the first control signal and generates the third control signal that controls the state of the primary-side power transistor.
The present invention will be further described below by way of several specific examples. For the sake of brevity, the following examples do not cover all possible combinations of the above-described features of the primary-side and secondary-side regulators.
The follow-up SSR module 22 includes a frequency-based on-time control circuit 221 and a second drive generator module 222. The frequency-based on-time control circuit 221 receives the first control signal Vcontrol from the first transmitter 114 and outputs a secondary-side on-time control signal SSR_Vlimit for controlling the on-time of the primary-side power transistor 107. The second drive generator module 222 receives the first control signal Vcontrol, the secondary-side on-time control signal SSR_Vlimit and a primary-side current sample signal Vcs and outputs the third control signal SSR_Gate.
In this example, the secondary-side regulation signal generation module 11 outputs the first control signal Vcontrol that carries only the turn-on timing of the primary-side power transistor 107 and is coupled to the primary-side regulator 20. The follow-up SSR module 22 in the primary-side regulator 20 receives the first control signal Vcontrol and obtains a control signal that contains and controls the on-time of the primary-side power transistor 107 by configuring the frequency-based on-time control circuit 221. As such, the third control signal SSR_Gate capable of controlling turn-on and turn-off of the primary-side power transistor 107 is eventually output to the primary-side power transistor 107.
Specifically, the secondary-side frequency control signal SSR_fs output from the second frequency control module 116 controls the frequency, and hence the turn-on timing, of the primary-side power transistor 107. The secondary-side regulation signal generation module 11 further includes a second transmitter 117, which receives the secondary-side frequency control signal SSR_fs and transmits the first control signal Vcontrol that contains the turn-on timing of the primary-side power transistor 107.
The follow-up SSR module 22 includes a frequency-based on-time control circuit 221 and a second drive generator module 222. The frequency-based on-time control circuit 221 receives the first control signal Vcontrol and outputs the secondary-side on-time control signal SSR_Vlimit for controlling the on-time of the primary-side power transistor 107. The second drive generator module 222 receives the first control signal Vcontrol, the secondary-side on-time control signal SSR_Vlimit and a primary-side sample signal Vcs and outputs the third control signal SSR_Gate.
In this example, the secondary-side regulation signal generation module 11 outputs the first control signal Vcontrol that only contains the turn-on timing of the primary-side power transistor 107 and is coupled to the primary-side regulator 20. The follow-up SSR module 22 in the primary-side regulator 20 receives the first control signal Vcontrol and obtains a control signal that contains and controls the on-time of the primary-side power transistor 107 by configuring the frequency-based on-time control circuit 221. As such, the third control signal SSR_Gate capable of controlling turn-on and turn-off of the primary-side power transistor 107 is eventually output to the primary-side power transistor 107.
For more details about the second drive generator module, reference can be made to the above description of the first drive generator module, and further description thereof is omitted here.
In this example, the second logic circuit 118 is preferred to be an RS flip-flop. The second comparison result PoReq_S is received at a reset terminal R of the RS flip-flop, and a signal COTGate_S for controlling turn-on and turn-off of the primary-side power transistor 107 is output from an output terminal Q of the RS flip-flop. The timing circuit 119 receives the signal COTGate_S for controlling turn-on and turn-off of the primary-side power transistor 107 and outputs the secondary-side on-time control signal Vcot_S for controlling the primary-side power transistor 107 to a set terminal S of the flip-flop.
The secondary-side regulation signal generation module 11 further includes a third transmitter 120, which receives the signal COTGate_S for controlling turn-on and turn-off of the primary-side power transistor 107 and outputs the first control signal Vcontrol that contains both the turn-on and turn-off timings of the primary-side power transistor 107.
The follow-up SSR module 22 includes a second drive generator module 222, which receives the first control signal Vcontrol and outputs the third control signal SSR_Gate. The third control signal SSR_Gate contains information about the turn-on and turn-off timings of the primary-side power transistor 107.
In this example, the secondary-side regulation signal generation module 11 outputs the first control signal Vcontrol that contains the turn-on and turn-off timings of the primary-side power transistor 107 and is coupled to the primary-side regulator 20. In the primary-side regulator 20, only a drive generator module is included. As such, the third control signal SSR_Gate capable of controlling turn-on and turn-off of the primary-side power transistor 107 is eventually output to the primary-side power transistor 107.
In the control method employed in the above-discussed examples of
In one example, in the PSR mode enabled by the PSR module 21, the output voltage can rise up to a first reference value Vref1, and in the SSR mode enabled by the follow-up SSR module 22, the output voltage can rise up to a second reference value Vref2. The first reference value Vref1 is not greater than the second reference value Vref2. As a result, during startup of the isolated power converter, the output voltage can rise smoothly without overshooting, enhancing reliability and security of the system.
The present invention also provides a control method for the above-discussed isolated power converter. The control method includes:
In summary, the present invention provides a controller, an isolated power converter and a control method. The controller includes a primary-side regulator and a secondary-side regulator. The secondary-side regulator includes a secondary-side regulation signal generation module, which receives a feedback signal of an output voltage of the isolated power converter, generates a first control signal and couples the first control signal to the primary-side regulator. The primary-side regulator includes a PSR module, which receives a voltage signal across a winding of the isolated power converter and generates a second control signal for controlling a state of the primary-side power transistor, thereby executing a PSR mode. The primary-side regulator also includes a follow-up SSR module, which receives the first control signal and generates a third control signal for controlling the state of the primary-side power transistor, thereby executing an SSR mode. The primary-side regulator also includes a regulation switching module, which receives the first control signal and thereby allows a switching of the primary-side regulator between the PSR and SSR modes. During startup of the isolated power converter, the PSR mode is first enabled by the PSR module, and a mode switching is then caused by the regulation switching module to allow the follow-up SSR module to enable the SSR mode. This can avoid overshooting of the output voltage during startup.
The description presented above is merely that of a few preferred embodiments of the present invention and is not intended to limit the scope thereof in any sense. Any and all changes and modifications made by those of ordinary skill in the art based on the above teachings fall within the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310486048.7 | Apr 2023 | CN | national |
