Patent Grant
10537000
This application claims priority to Chinese Patent Application No. 201810351017.X, titled “Controller, Light Source Driving Circuit and Method for Controlling Light Source Module,” filed on Apr. 18, 2018, with the National intellectual Property Administration of the People's Republic of China (CNIPA),
Compared with traditional incandescent lamps, light-emitting diode (LED) light sources offer several advantages such as low power conservation, environmental friendliness, high power efficiency, and long lifespan. Therefore, there is a trend to replace incandescent lamps with LED light sources. An LED bulb is one type of LED lamp. The LED bulb has a shape and size similar to traditional incandescent lamps. LED light sources and control chips are integrated within an LED bulb. A conventional LED light source driving circuit includes two control chips, where one is operable for regulating the brightness of the light source and the other is operable for regulating the color of the light source. Because the conventional LED light source driving circuit uses two individual control chips, the cost of manufacturing is increased.
Embodiments in accordance with the present invention provide a controller, a light source driving circuit and a method for controlling a light source module.
In one embodiment, a controller for controlling a light source module includes a current input terminal, a switch monitoring terminal, a first control terminal, a second control terminal and a current monitoring terminal. The current input terminal is coupled to a power source through a rectifier and is operable for receiving electric power from the power source. The switch monitoring terminal is coupled to a power switch and is operable for receiving a switch monitoring signal indicating the on/off state of the power switch. The power switch is coupled between the rectifier and the power source. The first control terminal is operable for turning on or turning off a first light source in the light source module based on the switch monitoring signal. The second control terminal is operable for turning on or turning off a second light source in the light source module based on the switch monitoring signal. The current monitoring terminal is operable for monitoring a current flowing through the first light source and a current flowing through the second light source.
In one embodiment, a light source driving circuit includes a light source module and a controller. The light source module includes a first light source and a second light source. The controller is coupled to the light source module and is operable for receiving electric power from a power source through a rectifier to power the light source module. The controller includes a memory module. The controller is operable for generating a first control signal to turn on or turn off the first light source based on data stored in the memory module, and generating a second control signal to turn on or turn off the second light source based on data stored in the memory module.
In yet another embodiment, a method for controlling a light source module that includes a first light source and a second light source includes the following steps: receiving electric power from a power source, to power the light source module via the controller; reading data stored in a memory module; and generating a first control signal by the controller, based on data stored in the memory module to turn on or turn off the first light source; and generating a second control signal by the controller, based on data stored in the memory module to turn on or turn off the second light source.
Features and advantages of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds, and upon reference to the drawings, wherein like numerals depict like parts, and in which:
Reference will now be made in detail to the embodiments of the present invention. While the invention will be described in combination with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims.
Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.
Some portions of the detailed descriptions that follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. In the present application, a procedure, logic block, process, or the like, is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those utilizing physical manipulations of physical quantities. Usually, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computing system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as transactions, bits, values, elements, symbols, characters, samples, pixels, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present disclosure, discussions utilizing terms such as “receiving,” “calculating,” “recording,” “reading,” “acquiring,” “selecting,” “determining,” “increasing,” “decreasing,” “receiving,” “generating,” updating,” “writing,” or the like, refer to actions and processes of a controller or computing system or similar electronic computing device or processor. A controller or computing system or similar electronic computing device manipulates and transforms data represented as physical (electronic) quantities within the computing system memories, registers or other such information storage, transmission or display devices.
The light source driving circuit 100 further includes a controller 110. The controller 110 is coupled to the light source module 130, receives electric power from a power source 102 through a rectifier 106, and supplies electric power to the light source module 130. The controller 110 includes a memory module (shown in
The terminals of the controller 110 include a current input terminal DRAIN, a switch monitoring terminal VDD, a first control terminal SW1, a second control terminal SW2 and a current monitoring terminal CS. The current input terminal DRAIN is coupled to the power source 102 through the rectifier 106 and receives electric power from the power source 102. The switch monitoring terminal VDD is coupled to a power switch 104 and is operable for receiving a switch monitoring signal SWMON that indicates the on/off state of the power switch 104. In one embodiment, the switch monitoring signal SWMON is the voltage at the switch monitoring terminal VDD. The switch monitoring terminal VDD also acts as the power terminal of the controller 110 and receives electric power from the power source 102. The power switch 104 is coupled between the rectifier 106 and the power source 102. The first control terminal SW1 is coupled to the first light source 111 and is operable for turning on or turning off the first light source 111 based on the switch monitoring signal SWMON. The second control terminal SW2 is coupled to the second light source 112 and is operable for turning on or turning off the second light source 112 based on the switch monitoring signal SWMON. The current monitoring terminal CS is coupled to the light source module 130 through a resistor 109 and an inductor 108, and is operable for monitoring a current flowing through the first light source 111 and a current flowing through the second light source 112.
Specifically, the current detection unit 210 is coupled to the current monitoring terminal CS, detects a current flowing through the first light source 111, and detects a current flowing through the second light source 112 (e.g., a current flowing through the first switch Q1 and/or a current flowing through the second switch Q2). If the first switch Q1 is on, the current detection unit 210 detects a current flowing through the first switch Q1. If the second switch Q2 is on, the current detection unit 210 detects a current flowing through the second switch Q2. If the first switch Q1 and the second switch Q2 are both on, the current detection unit 210 detects a sum of the current flowing through the first switch Q1 and the current flowing through the second switch Q2. The error amplifier 208 compares an output signal of the current detection unit 210 with a preset reference signal ADJ, and outputs an error signal to the comparator 206. The comparator 206 compares the error signal with a sawtooth wave signal output from the sawtooth wave signal generating unit 204, and outputs a comparison result to the logic control module 202. The logic control module 202 generates the third control signal DRV3 based on the comparison result, and controls the duty cycle of the third switch Q3 via a driving unit 212, thereby regulating the total current of the light source module 130.
If the third switch Q3 is on, then the fourth switch Q4 is also on, and a current from the power source 102 flows from the current input terminal DRAIN through the fourth switch Q4, the third switch Q3, the current monitoring terminal CS, the resistor 109 and the inductor 108, to ground. During this period, the inductor 108 stores electric power. If the third switch Q3 is off and the first switch Q1 is on, then the inductor 108 discharges, and a current flows from one end of the inductor 108 through the first light source 111, the first control terminal SW1, the first switch Q1, and the current monitoring terminal CS to the other end of the inductor 108. If the third switch Q3 is off and the second switch Q2 is on, the inductor 108 discharges, and a current flows from one end of the inductor 108 through the second light source 112, the second control terminal SW2, the second switch Q2, and the current monitoring terminal CS to the other end of the inductor 108.
With reference also to
The logic unit 310 includes a counter 312 operable for storing a count value. The counter 312 updates the count value based on the trigger signal DIMCLK. In one embodiment, the count value increases by one in response to each negative pulse in the trigger signal DIMCLK.
Specifically, when the power switch 104 is turned on, the voltage at the switch monitoring terminal VDD increases. When the voltage at the switch monitoring terminal VDD increases to a first voltage V1, the power supply unit 306 provides a voltage greater than a write threshold VW-TH (e.g., the first voltage V1) to allow the reading and writing unit 304 to write to the memory module 308. If the voltage at the switch monitoring terminal VDD increases to the first voltage V1, the logic unit 310 outputs the write enable signal W_EN in a first state (e.g., at a high level) at time tW. If the regulating signal DIMSTATE is also in the first state (e.g., at a high level), then the reading and writing unit 304 writes the count value of the counter 312 to the memory module 308. At time tR, which is later than time tW, the logic unit 310 outputs the read enable signal R_EN in a first state (e.g., at a high level), and the reading and writing unit 304 reads the data from the memory module 308 to generate the first control signal DRV1 and the second control signal DRV2. In one embodiment, if the first control signal DRV1 is in the first state (e.g., at a high level), then the first switch Q1 is on and the first light source 111 is turned on; if the first control signal DRV1 is in a second state (e.g., at a low level), then the first switch Q1 is off and the first light source 111 is turned off. If the second control signal DRV2 is in the first state (e.g., at a high level), then the second switch Q2 is on and the second light source 112 is turned on; and if the second control signal DRV2 is in the second state (e.g., at a low level), then the second switch Q2 is off and the second light source 112 is turned off.
At time tC, which is later than time tR, the logic unit 310 outputs a clamp signal CLAMP in a first state (e.g., at a high level) to the power supply unit 306, causing the power supply unit 306 to clamp the voltage at the switch monitoring terminal VDD to a second voltage V2, to enable components associated with a dimming function in the controller 110 of
In one embodiment, to write to the memory unit 401 (e.g., write a logical “0”), the reading and writing unit 304 applies a voltage difference greater than the write threshold VW-TH between the E terminal and the W terminal. For example, the reading and writing unit 304 applies a high voltage on the E terminal and causes the W terminal to be grounded, and the voltage difference VEW between the E terminal and the W terminal is greater than the write threshold VW-TH. Because the area of the first MOS capacitor 501 is greater than the area of the second MOS capacitor 502, and because the capacitance of the first MOS capacitor 501 is much greater than the capacitance of the second MOS capacitor 502, the voltage of the node 510 between the gate of the first MOS capacitor 501 and the gate of the second MOS capacitor 502 is relatively high. As a result, electrons flow into the node 510 and are stored at the node 510. Thus, even if the voltage difference between the E terminal and the W terminal is removed, the NMOSFET 503 remains in a high threshold state because the node 510 stores electrons having negative charges. In another embodiment, the reading and writing unit 304 applies a same voltage at both the E terminal and the W terminal, and the difference between that voltage and the source voltage of the NMOSFET 503 is greater than the write threshold VW-TH. As a result, the voltage of the node 510 is relatively high, and electrons flow into the node 510 and are stored at the node 510. Thus, even if the voltage at the E terminal and at the W terminal is removed, the NMOSFET 503 remains in a high threshold state because the node 510 stores electrons having negative charges.
In one embodiment, to write to the memory unit 401 (e.g., write a logical “1”), the reading and writing unit 304 applies a high voltage on the W terminal and causes the E terminal to be grounded, and the voltage difference VWE between the W terminal and the E terminal is greater than the write threshold VW-TH. Because the area of the first MOS capacitor 501 is greater than the area of the second MOS capacitor 502, and because the capacitance of the first MOS capacitor 501 is greater than the capacitance of the second MOS capacitor 502, the voltage of the node 510 between the gate of the first MOS capacitor 501 and the gate of the second MOS capacitor 502 is relatively low. As a result, a tunnel current is generated at the gate of the second MOS capacitor 502 and electrons flow from the node 510 to the W terminal, leaving holes having positive charges at the node 510. Thus, even if the voltage difference between the W terminal and the E terminal is removed, the NMOSFET 503 remains in a low threshold state because the node 510 stores positive charges.
Even if the system is out of power for a long time, the structure of the memory unit 401 described above enables the memory unit 401 to maintain its state after the write operation.
To read the data stored in the memory unit 401, a current source 512 is connected to the drain of the NMOSFET 503 (the connection point is labeled as C in
As described above, in one embodiment, when the voltage difference VEW is greater than the write threshold VW-TH, a logical “0” is written to the memory unit 401. In another embodiment, when the voltage at the E terminal and the voltage at the W terminal are the same and the difference between that voltage and the source voltage of the NMOSFET 503 is greater than the write threshold VW-TH, a logical “0” is written to the memory unit 401. When the voltage difference VWE is greater than the write threshold VW-TH, a logical “1” is written to the memory unit 401. The data stored in the memory unit 401 can be read from the node C via the inverter 514.
In step 602, the power switch 104 is turned on for the first time. In step 604, the reading and writing unit 304 reads the data stored in the memory module 308 and generates a first control signal DRV1 and a second control signal DRV2 accordingly, to place the light source module 130 in a corresponding mode (e.g., mode A, B or C). In step 606, the power switch 104 is turned off. In step 608, a determination is made as to whether the power switch 104 is turned on within a preset time period. If the power switch 104 is turned on within the preset time period, then in step 610, the reading and writing unit 304 writes a count value of the counter 312 to the memory module 308. In step 612, the reading and writing unit 304 reads the data stored in the memory module 308 and places the light source module 130 in the corresponding mode. In step 614, the power switch 614 is turned off. In step 616, the count value of the count 312 increases by one and the flowchart goes to step 608.
Returning to step 608, if the power switch 104 is not turned on within the preset time period after being turned off, then the flowchart proceeds to step 618 to determine whether the voltage at the switch monitoring terminal VDD decreases to a turn-off threshold. If not, then the flowchart proceeds to step 620, where the power switch 314 is turned on. Then, the flowchart further goes to step 604. Otherwise, the flowchart proceeds to step 622, and the count value of the counter 312 is reset to the default value (e.g., zero). Then the flowchart returns to step 602.
When the switch power 104 is turned on at time to, the voltage at the switch monitoring terminal VDD increases to V1 and the power supply unit 306 provides a voltage greater than the write threshold VW-TH to enable the reading and writing unit 304 to write to the memory module 308. Because the voltage at the switch monitoring terminal VDD increases to the first voltage V1, the logic unit 310 outputs a write enable signal W_EN in a first state (e.g., at a high level) at time tW1, which is later than time t0. At that time, the regulating signal DIMSTATE is in an initial state (e.g., at a low level), so the reading and writing unit 304 does not write to the memory module 308. At time tR1, which is later than time tW1, the logic unit 310 outputs the read enable signal R_EN in a first state (e.g., at a high level), and the reading and writing unit 304 reads the data from the memory module 308 to generate the first control signal DRV1 and the second control signal DRV2. At time tC1, which is later than the time tR1, the logic unit 310 outputs the clamp signal CLAMP in the first state (e.g., at a high level) to the power supply unit 306, which clamps the voltage at the switch monitoring terminal VDD to the second voltage V2 to enable the components associated with the dimming function in the controller 110 (e.g., the current detection unit 210, the error amplifier 208, the comparator 206, the sawtooth wave signal generating unit 204, etc., of
When the switch power 104 is turned off at time t1, the voltage at the switch monitoring terminal VDD decreases. A negative pulse appears in the trigger signal DIMCLK, which causes the state of the regulating signal DIMSTATE to change to a first state (e.g., a high level) and causes the count value of the counter 312 to increase by one, for example, changing from the default value zero to one. States of the write enable signal W_EN, the read enable signal R_EN and the clamp signal CLAMP all change to a second state (e.g., a low level).
The switch power 104 is turned on for the second time at time t2, and the voltage at the switch monitoring terminal VDD increases to V1. The power supply unit 306 provides a voltage greater than the write threshold VW-TH, which enables the reading and writing unit 304 to write to the memory module 308. Because the voltage of the switch monitoring terminal VDD increases to the first voltage V1, the logic unit 310 outputs a write enable signal W_EN in a first state (e.g., a high level) at time tW2, which is later than time t2. At that time, the regulating signal DIMSTATE is in the first state (e.g., a high level), so the reading and writing unit 304 writes the count value (e.g., one) of the counter 312 to the memory module 308 and stores it in binary format (e.g., as “01”) in the memory module 308. At time tR2, which is later than time tW2, the logic unit 310 outputs the read enable signal R_EN in the first state (e.g., a high level), and the reading and writing unit 304 reads the data “01” from the memory module 308 to generate the first control signal DRV1 and the second control signal DRV2. At time tC2, which is later than time tR2, the logic unit 310 outputs the clamp signal CLAMP in the first state (e.g., a high level) to the power supply unit 306, which clamps the voltage at the switch monitoring terminal VDD to the second voltage V2 to enable the components associated with the dimming function in the controller 110 to turn on the light source module 130. According to the data (e.g., “01”) read from the memory module 308, the light source module 130 is set to mode A after it is turned on.
The switch power 104 is turned off at time t3 and at time t5, and at each of those times the count value of the counter 312 increases by one in response to the trigger signal DIMCLK. At time t3, the count value is two, which is stored in the memory module 308 as binary “10”, and at time t5, the count value is three, which is stored in the memory module 308 as binary “11”. Therefore, when the power switch 104 is turned on at time t4 and time t6, the mode of the light source module 130 is mode B and mode C, respectively. When the power switch 104 is turned off after time t6, the count value stored in the memory module 308 will be set to binary “00”, and the sequence shown in
In step 902, electric power is received from the power source 102 and powers the light source module 130 using the controller 110.
In step 904, data stored in the memory module 308 is read using the reading and writing unit 304.
In step 906, a first control signal is generated based on the data stored in the memory module 308 to turn on or turn off the first light source 111, and a second control signal is generated based on the data stored in the memory module 308 to turn on or turn off the second light source 112 by the controller 110.
As described above, embodiments according to the present invention disclose a controller for controlling a light source module, a light source driving circuit and a method for controlling a light source module. The present invention can adjust the mode of the light source module with a power switch to adjust the color or brightness of the light source module. Because an additional dimming device is not needed and is eliminated, the cost is reduced. In addition, the mode of the light source module can be memorized by the memory module integrated in the controller. That is, even if the system is out of power for a long time, when the power switch is turned on again, the controller can read the data stored in the memory module directly and enable the mode of the light source module instantly set to the mode that the user used last time according to the data. While the foregoing description and drawings represent embodiments of the present invention, it will be understood that various additions, modifications and substitutions may be made therein without departing from the spirit and scope of the principles of the present invention as defined in the accompanying claims. One skilled in the art will appreciate that the invention may be used with many modifications of form, structure, arrangement, proportions, materials, elements, and components and otherwise, used in the practice of the invention, which are particularly adapted to specific environments and operative requirements without departing from the principles of the present invention. The presently disclosed embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims and their legal equivalents, and not limited to the foregoing description.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2018 1 0351017 | Apr 2018 | CN | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 10076011 | Amidi | Sep 2018 | B1 |
| 20150181668 | Chang | Jun 2015 | A1 |
| 20160088697 | Yan | Mar 2016 | A1 |
| 20160212815 | Watanabe | Jul 2016 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20190327805 A1 | Oct 2019 | US |
