Controller of electronic device, bus control device

Abstract

Processing ability can be easily decreased in a processor connected by a bus to a device that is a bus master. A controller of an electronic device has a processor and a bus controller that is the bus master of the processor, the bus controller including a mode determining section that determines mode based on a state of the processor, and a performance controller that, for a prescribed mode, inserts a wait time in an acknowledgement signal to be output to the processor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an outline of a configuration of a controller installed in a printer;

FIG. 2 is a flow diagram explaining mode switch processing of a CPU performance controller;

FIG. 3 is a timing diagram showing processing of the CPU performance controller for normal performance mode;

FIG. 4 is a timing diagram showing processing of the CPU performance controller for reduced performance mode; and

FIG. 5 is a timing diagram showing processing of the CPU performance controller for reduced performance mode.

Claims

1. A controller of an electronic device comprising: a processor; anda bus controller that is a bus master of the processor, wherein the bus controller includes: a mode determining section that determines mode based on a state of the processor, anda performance controller that, for a prescribed mode, inserts a wait time in an acknowledgement signal to be output to the processor.

2. A bus controller that is a bus master of a processor, the bus controller comprising: a mode determining section that determines mode based on a state of the processor; anda performance controller that, for a prescribed mode, inserts a wait time in an acknowledgement signal to be output to the processor.

3. A bus controller according to claim 2, wherein the mode that is determined is a mode related to temperature of the processor, and the prescribed mode is a mode indicating that the temperature has become high.

4. A bus controller according to claim 2, wherein the acknowledgement signal comprises at least one of an address acknowledgement signal and a data acknowledgement signal.

5. A printer controller that outputs image data to a print engine, the controller comprising: a central processing unit ; anda memory control device that is a bus master of the central processing unit, wherein the memory control device includes: a mode determining section that determines mode in accordance with a temperature state of the central processing unit; anda performance controller that, for a mode indicating that the temperature state of the central processing unit is high, inserts a wait time in an acknowledgement signal to be output to the central processing unit.

6. A printer controller according to claim 5, wherein the wait time is at least within a time in which the central processing unit can generate the image data that is requested by the print engine.

7. A printer in which the printer controller according to claim 5 is installed.