Controlling circuit power consumption through body voltage control

TECHNICAL FIELD

[0002] The present invention is generally related to the control of circuit power consumption and, more particularly, is related to systems and methods for reducing static power consumption and/or delay of digital circuits.

BACKGROUND OF THE INVENTION

[0003] Electronic systems and circuits form the basis of many devices upon which people depend. For example, electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems are common in many homes and offices. Such electronic systems are often implemented by or through semiconductor devices.

[0004] A semiconductor device, generally, may be thought of as an electronic device that makes use of semiconductor material. In essence some of the electronic technologies implemented in such devices use semiconductor materials to build the electronic technologies. Semiconductor materials are basically materials that have an electric resistance that is somewhere between a pure conductor (such as copper wire) and an insulator (such as plastic); hence the name “semiconductor.” Silicon is a common semiconductor material employed extensively in modern electronic devices.

[0005] When a semiconductor material is used to construct electronic devices, the conductivity of the semiconductor material is often altered through a process known as “doping.” “Doping” involves the process of introducing impurities into the semiconductor. The impurity added to the semiconductor is called a “dopant.” Through “doping,” the conductivity of the semiconductor material can be controlled in a precise and predictable manner.

[0006] The process of “doping” places mobile, charged carriers for conducting electricity in the semiconductor crystal lattice. When semiconductor materials are “doped” so as to add negative charge carriers to the semiconductor lattice, the material is referred to as an “n-type” semiconductor. Conversely, when semiconductor materials are doped so as to add positive carriers to the semiconductor lattice, the material is then referred to as a “p-type” semiconductor.

[0007] One type of electronic device that implements semiconductor material is a transistor. One particular type of transistor is the field-effect transistor (“FET”). The FET gets its name from the way it physically operates. The mechanism that controls current through an FET is based upon an electric “field” established by a voltage applied to a particular portion of the FET.

[0008] A Metal-oxide semiconductor field-effect transistor (“MOSFET”) is a particular type of FET. As the name suggests, a MOSFET was traditionally made from growing a silicon dioxide layer on a semiconductor substrate and positioning a metal gate on the silicon dioxide layer. Thus, the MOSFET made use of a metal, an oxide, and a semiconductor to create a FET. Of course, now, MOSFETs are constructed in a variety of ways, not necessarily employing a metal gate.

[0009]
FIG. 1A depicts a typical MOSFET device 10. This figure demonstrates the basic elements of a MOSFET 10 as it is most commonly constructed and implemented. As with any such device, it is possible to manufacture and/or implement a MOSFET in a variety of ways. The MOSFET 10 of FIG. 1A is merely one example of a MOSFET for demonstrative purposes only.

[0010] The most prominent portion of the MOSFET device 10 is a substrate, or “body” 12 of the device 10. Typically, the substrate 12 is a doped silicon material. The silicon of the body 12 may be either doped such as to be an n-type material, or a p-type material. Once the doped substrate 12 is prepared, two heavily doped regions 13, 14 are created in the substrate 12. One of these regions is typically called the “source” 13 and the other of the regions is typically called the “drain” 14. If the substrate silicon 12 is doped so as to be a p-type material, then the source 13 and drain 14 are usually doped to be n-type materials. A device configured in this manner is referred to as an “NFET” transistor. Conversely, if the substrate 12 is doped to be an n-type material, then the source 13 and drain 14 are doped so as to be p-type materials. A device configured in this manner is referred to as a “PFET” transistor.

[0011] An insulating layer 16, usually a silicon dioxide material, is grown onto a surface of the substrate 12 between the source 13 and the drain 14. Then, a metal material 17, or more commonly a polycrystalline silicon material, is deposited onto the insulating layer 16. This metal material 17 serves as what is known as a “gate electrode.” Metal contacts 18, 19 are also made to the source region 13 and the drain region 14, respectively.

[0012] Additionally, a metal contact 21 is typically made to the substrate body 12 of the MOSFET 10. The body contact could be positioned in a number of different ways. As depicted in FIG. 1A, the body contact is what is known as an ohmic contact. The contact is connected to a portion of the body 20 that has been doped so as to be the same material as the substrate, only the doping is heavier than the substrate. This type of connection is common when the MOSFET is configured into an Integrated Circuit (“IC”) chip.

[0013] Terminals 22, 23, 24, and 26 are brought away from each of the metal contacts.

[0014] Therefore, the typical MOSFET 10 has four terminals: a source terminal 22, a gate terminal 23, a drain terminal 24, and a body terminal 26.

[0015] As mentioned above, the MOSFET 10 depicted in FIG. 1 and described above is merely one typical implementation of a MOSFET device. There may be other configurations possible, as well as other terminal configurations and dopings. FIG. 1A is exemplary only.

[0016] As noted above, the FET portion of the MOSFET's name comes from the manner in which the device operates. The term “field-effect” in the name MOSFET is related to the application of an “electromotive field,” or voltage, to the gate terminal 23.

[0017] Application of this voltage causes carriers, either electrons or “holes,” to gather in the region of the substrate 12 immediately under the insulating layer 16. Additionally, a capacitance across the insulating layer 16 is formed.

[0018] The carriers collecting in the substrate 12 form a conductive “channel” 27 through which current can flow from the source 13 to the drain 14, or vice versa. The amount of voltage applied to the gate terminal 23 controls the size of the conductive channel 27.

[0019] Consequently, a gate voltage can be used to control the source-drain current through the channel 27 in a MOSFET 10.

[0020] There is a value of voltage applied to the gate terminal 23 that will induce a channel 27 and permit current to flow from source 13 to drain 14, or vice versa. At gate voltages below this value, only a very small current flows through the transistor. This current is called the “subthreshold current.” At gate voltages above this value, current may freely pass from source 13 to drain 14, or vice versa. This current can be referred to as the “on” current for the transistor. This value of gate voltage is known as the “threshold voltage.”

[0021]
FIG. 1B depicts the circuit diagram symbols used to represent an NFET 28 and a PFET 29. The terminals of the MOSFETS are represented by the letters S, G, D, and B.

[0022]
FIG. 2 depicts a circuit diagram of a typical configuration of a Complementary Metal Oxide Semiconductor (“CMOS”) circuit, or CMOS “gate” 30. The particular “gate” 30 depicted in FIG. 2B is a CMOS circuit known as a “NOT gate,” or a CMOS “inverter.” This CMOS circuit combines a PFET 34 and an NFET 33 in the manner indicated.

[0023] In this gate 30, the voltage applied to the gate terminals 31 of the NFET 33 and the PFET 34 of the CMOS inverter 30 may be considered a type of “input” voltage. The voltage at the drain terminals 32 of the NFET 33 and the PFET 34 of the CMOS inverter 30 may be considered an “output” voltage of the gate 30. If the voltage at the gate terminals 31 is set to a low level, such as zero or ground, then the output of this CMOS gate 30 will be a high voltage, such as the supply voltage. In essence, when the “input” voltage is zero, the NFET 33 of the “NOT gate” will be “off” such that only negligible drain current flows through the NFET 33. However, the PFET 34 will be “on” such that current, an “on-current” will flow from the source 36 to drain 37 of the PFET.

[0024] On the other hand, if the gate voltage is set to a high level, such as the supply voltage to the circuit, then the output of this CMOS gate 30 will be a low voltage, such as zero. In essence, when the “input” voltage is high, the PFET 34 of the “not gate” 30 will be “off” such that only negligible on-current flows through the PFET 34. However, the NFET 33 will be “on” such that drain current will flow between the NFET source 38 and the NFET drain 39.

[0025] As noted above, the current passing from the drain to the source when the gate voltage is larger than the threshold voltage is called the “on-current.” Generally, the on-current is related to the temperature of the circuit. As the circuit operates, its temperature naturally increases. Of course, the temperature of the circuit may also increase (or decrease) due to a change in the ambient temperature of the environment. Regardless of the source of the temperature increase (or decrease), as the temperature of the circuit increases, the on-current also changes.

[0026] At one particular value of supply voltage, the on-current is independent of the temperature. This voltage is know as the Zero-Temperature-Coefficient (“ZTC”) voltage of the circuit. At supply voltages below the ZTC voltage, the on-current has a positive relationship to the temperature change. That is, as temperature increases, on-current increases. However, at supply voltages above the ZTC voltage, as the temperature increases, the on-current decreases.

[0027] The ZTC voltage for most MOSFETs currently in use is about 1V, and therefore, circuits with power supply voltages below 1V have a positive temperature dependence of the on-current. Currently, it is typical for CMOS circuits to operate with supply voltages above 1V, that is, above the ZTC voltage. However, the International Technology Roadmap for Semiconductors (“ITRS”) has published data on the projected future of semiconductors. This data projects that by as early as 2004, CMOS circuits will be operating with supply voltages below 1V. The value of supply voltages used for CMOS circuits will likely continue to decrease in the years following 2004. Therefore, in the future, the supply voltage of CMOS circuits may be below the ZTC of the circuit such that as the temperature of the circuit increases, the on-current will also increase. As noted above, the temperature of a circuit may increase because of a number of different reasons. For example, the operation of the device may increase the temperature of the circuit, or the ambient temperature may either increase or reduce the temperature of the circuit.

[0028] An increase in on-current is typically desired. Increasing the on-current decreases the delay of the circuit, thereby typically making the circuit faster.

[0029] The on-current freely flows through a transistor, or circuit, when the gate voltage is above the threshold voltage of the transistor, or circuit. However, when the gate voltage is below the threshold voltage, there is still some current that flows through the circuit. This current is call the “subthreshold” drain current. It is typically desirable to minimize this current as it is basically a “leakage” current. This is typically an unwanted source of static power consumption by a circuit.

[0030] The total power consumption of a digital circuit is generally composed of three parts: the dynamic power consumption, the static power consumption, and the short circuit power consumption. The dynamic power consumption is largely due to dynamic charging and discharging of load capacitance in the circuit. The static power consumption, sometimes called the “leakage current power,” largely results from leaking diodes and transistors. Finally, the short circuit power consumption generally results from the flow of current from the supply to ground during the switching of the circuit.

[0031] The main contributor to static power consumption within future generations of circuits will likely be the subthreshold drain current, or “leakage” current. That is, the leakage current when the circuit is operating with a gate voltage below the threshold voltage will likely be the primary source of static power consumption. Additionally, as the temperature of a circuit increases, the subthreshold current, and therefore the static power consumption, should also increase. The subthreshold current is a function of temperature and increases as the temperature of a circuit increases. Unlike the on-current for a circuit, the relationship between temperature and the subthreshold drain current is not a function of the supply voltage. It is, of course, desirable to minimize static power consumption of a circuit.

[0032] Scaling the dimensions of MOSFETs is typically required in order to continue the trend toward reducing the power and increasing the speed of electronic devices.

[0033] Although the power dissipation of a single gate may be reduced, the total power dissipation of a chip will likely be increased because of the increasing complexity of a chip. This makes it more difficult for the overall package to transfer this power to the environment.

[0034] On the other hand, to increase the speed of the chip, it is known that the threshold voltage should be reduced, which will increase the static power dissipation exponentially.

[0035] Therefore, the static power dissipation will likely be a big fraction of the total power consumption of the chip in the future. As such, static power consumption will likely be an increasing fraction of the total power consumption of digital circuits in coming years.

[0036] Thus, a heretofore unaddressed need exists in the industry to reduce the static power consumption, and thus the total power consumed, by a circuit operating with supply voltages below the ZTC voltage. Furthermore, a heretofore unaddressed need exists in the industry to reduce the delay of a circuit by controlling the circuit static power consumption when the supply voltage of the circuit is below the ZTC voltage.

SUMMARY OF THE INVENTION

[0037] Embodiments of the present invention provide systems and methods for reducing circuit power consumption and reducing circuit delay by adjusting the body voltage to the circuit as the temperature of the circuit changes with time.

[0038] Briefly described, one embodiment of such a method, among others, can be broadly summarized by the following steps: detecting a temperature change at the circuit; and adjusting a body voltage to a transistor in the circuit such that the power consumption is controlled.

[0039] Briefly described, one embodiment of a system for controlling the power consumption of a circuit can be implemented with a device having structure for detecting a temperature change at the circuit and for adjusting a body voltage to the circuit responsive to said temperature change at the circuit.

[0040] Other systems, methods, features, and advantages of the present invention will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present invention, and be protected by the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Many aspects of the invention can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present invention. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

[0042]
FIG. 1A is a cut-away side view of a typical MOSFET circuit.

[0043]
FIG. 1B is circuit diagram of typical NFET and PFET type MOSFETs.

[0044]
FIG. 2 is a circuit diagram of a CMOS “NOT gate,” or “inverter.”

[0045]
FIG. 3A is a flow chart showing the steps employed by a control circuit for reducing the power consumption of a circuit by monitoring the circuit delay in order to detect a change in circuit temperature.

[0046]
FIG. 3B is a continuation of the flow chart of FIG. 3A.

[0047]
FIG. 4 is a flow chart showing the steps employed by a control circuit for reducing the power consumption of a circuit by monitoring the circuit temperature directly.

[0048]
FIG. 5A is a flow chart showing the steps employed by a control circuit for reducing the delay of a circuit by monitoring the circuit delay in order to detect a change in circuit temperature.

[0049]
FIG. 5B is a continuation of the flow chart of FIG. 5A.

[0050]
FIG. 6 is a flow chart showing the steps employed by a control circuit for reducing the delay of a circuit by monitoring the circuit temperature directly.

[0051]
FIG. 7 is a plot of threshold voltage versus the temperature of an exemplary 70 nm CMOS circuit using the preferred system and method described herein.

[0052]
FIG. 8 is a plot of the drain subthreshold current versus the temperature of an exemplary 70 nm CMOS circuit using the preferred system and method described herein.

[0053]
FIG. 9 is a plot of the on-current versus temperature of an exemplary 70 nm CMOS circuit using the preferred system and method described herein.

DETAILED DESCRIPTION

[0054] Broadly described, the embodiments described herein comprise systems and methods for controlling power consumption of a circuit. Specifically, the systems and methods of the disclosed embodiments deal with reducing static power consumption and/or the delay of digital circuits comprising MOSFETs. Furthermore, the systems and methods are particularly tailored to reduce static power consumption and/or delay of a circuit operating with supply voltages below the Zero-Temperature-Coefficient (“ZTC”) voltage of the MOSFET. The reductions in delay and/or static power consumption are performed by controlling the static power consumed by a given circuit.

[0055] The systems and methods described herein are based upon observations about the way in which MOSFET transistors, and circuits comprising these transistors, operate with changing temperature. It has been realized that a change in the temperature of the circuit has ramifications to the operation of the circuit. These realizations, as seen below, can be utilized to control the static power consumption of a circuit, thereby either reducing the static power consumption or reducing the delay of a circuit.

[0056] Static Power Consumption Increases with Increasing Temperature

[0057] First, it can be demonstrated that the static power consumption of a MOSFET, or a circuit comprising MOSFETs, varies with temperature. Of course, as noted above, it is well known that the overall power consumption of a circuit is generally composed of the dynamic power consumption, the static power consumption, and the short circuit power consumption. Stated in a mathematical equation, the total power consumption of an individual CMOS gate, or an overall circuit comprised of MOSFETs, may be expressed as:

P=P

dy

+P

st

+P

sc
(1)

[0058] where Pdy is the dynamic power, Pst is the static power and Psc is the short circuit power.

[0059] The static power consumption of an individual MOSFET, as noted above, is currently, or will likely be in the future, largely due to the leakage current of the transistor. Therefore, the static power consumption of a circuit may be expressed by the following relationship:

P

st

=V

dd

×I

Leak
(2)

[0060] where ILeak is the leakage current of the MOSFET transistor and Vdd is the power supply voltage of the circuit.

[0061] Where most of the leakage current is subthreshold current, therefore, the equation for static power consumption may be expressed as:

P

st

=V

dd

×I

sub
(3)

[0062] where ISub is the subthreshold current and Vdd is the power supply voltage applied to the circuit.

[0063] As is known, the subthreshold leakage current is a function of the temperature of a circuit. Or, in other words:

I

sub
=ƒ(T) (4)

[0064] Therefore, from equation (3), the static power consumption of the circuit is also a function of the temperature of the circuit. Indeed, it is known that the subthreshold current of a circuit increases exponentially with temperature. Therefore, the static power consumption also increases exponentially with increasing temperature. Stated another way, the “worst-case” static power dissipation of a circuit occurs at the highest operating temperature of the circuit.

[0065] Mobility and Threshold Voltage Vary with Temperature

[0066] The next realization that contributes to the present systems and methods is that mobility and threshold voltage are two parameters of a MOSFET transistor, which also change with the changing temperature of the circuit. These relationships may be expressed as:

μ=ƒ(T), and (5)

V

TH
=ƒ(T) (6)

[0067] where μ is the mobility of the circuit and VTH is the threshold voltage of the circuit.

[0068] It is also known that as the temperature of a circuit increases, the mobility of the circuit is reduced. Similarly, an increase in the temperature of a circuit, or a transistor, results in a lower threshold voltage of the circuit, or a transistor. So, as the temperature of a circuit comprising MOSFETs increases, both the mobility and the threshold voltage of the circuit are reduced. Changes in the threshold voltage and the mobility affect the value of the on-current in a circuit comprising MOSFETs.

[0069] Overall, as outlined above, the effect of increasing temperature on the on-current is dictated by the particular supply voltage applied to the circuit. At levels of the supply voltage above the ZTC voltage, the overall effect of increasing temperature on the on-current will be to reduce the on-current of the circuit, or individual MOSFET. However, at levels of supply voltage below the ZTC voltage, the overall effect of increasing temperature on the on-current will be to increase the on-current of the circuit, or individual MOSFET.

[0070] In contrast, however, the effect that temperature has on the subthreshold drain current does not depend on the supply voltage to a particular MOSFET. Indeed, it is known, and can be shown, that the subthreshold drain current of a particular MOSFET is a function of temperature and will increase with increasing temperature regardless of the supply voltage.

[0071] The Delay of a Circuit Decreases with Increasing Temperature

[0072] Another observation that may be made is that the delay of a circuit comprised of MOSFET type transistors decreases as the temperature of the circuit increases. The delay of a circuit reflects how fast a circuit can switch its output. The switching of output generally involves the charging or discharging of the load capacitance of the circuit.

[0073] The gate delay is a function of the on-current, the supply voltage and the load capacitance. This relationship can be shown mathematically as:

\begin{matrix} Delay \approx \frac{C_{L} V_{dd}}{I_{on}}, & (7) \end{matrix}

[0074] where CL is the load capacitance and Ion is the “on-current.”

[0075] As explained above, for supply voltages below the ZTC voltage, it has been observed that as the temperature of a circuit increases, the on-current of the circuit also increases. Therefore, based on the above relationship, as the on-current increases with increasing temperature, the gate delay of the circuit decreases. Generally, the load capacitance and the supply voltage do not change with changing temperature.

[0076] Hence, the lowest drain current, which results in the “worst-case” gate delay, occurs at the lowest operating temperature of the circuit. The gate delay is reduced and the leakage power is increased by increasing the temperature. Therefore, the “worst-case” static power consumption of a circuit is at the maximum operating temperature of the circuit, while the “worst-case” delay of the same circuit is at the minimum operating temperature of the circuit.

[0077] The Preferred Embodiments

[0078] Recognizing the above features and qualities of digital circuits relating to changing temperature of the circuit, the present systems and methods are directed to changing the body voltage of a circuit as the temperature of the circuit changes. Changing the body voltage of a circuit can be used to control the static power consumed by the circuit. Particularly, the adjustment in the body voltage can be used to reduce the power consumption of the circuit and/or to reduce the delay of the circuit. Either result is potentially desirable for different applications of a particular circuit. Preferably, these embodiments are implemented with a circuit that is operating with a supply voltage less than the ZTC voltage of the MOSFET.

[0079] In a first preferred embodiment of the static power control technique, an adjustment to the body voltage of a circuit is performed in such a manner that the circuit delay becomes independent of the circuit temperature. In this embodiment, the delay is preferably held constant, or nearly constant, at its “worst-case” value. That is, the delay of a circuit is set equal to the typical circuit delay when the circuit is operating at the lowest operating temperature of the circuit. Then, by decreasing the body voltage of the circuit NFETs and increasing the body voltage of the circuit PFETs as the temperature of the circuit increases, the delay of the circuit is held constant.

[0080] The product of changing the body voltage in this manner, of course, increases the threshold voltage of the MOSFET, which, in turn, decreases the static power consumption of the circuit. Indeed, increasing the threshold voltage reduces the subthreshold drain current exponentially. For this reason, the first preferred embodiment is referred to as a Leakage Reduction Technique (“LRT”).

[0081] Additionally, as also shown above, the static power is a function of the subthreshold current. Therefore, the overall power consumption of the CMOS circuit will be reduced through the modification of the circuit body voltage.

[0082] In a second preferred embodiment of the static power control technique, the an adjustment to the body voltage of a circuit is also performed in such a manner that the circuit delay becomes independent of the circuit temperature. In this embodiment, the delay is preferably held constant, or nearly constant, at its “best-case” value. That is, the circuit delay is set equal to the typical circuit delay when the circuit is operating at the highest operating temperature of the circuit. Then, by decreasing the body voltage of the circuit NFETs and increasing the body voltage of the circuit PFETs as the temperature of the circuit increases, the delay of the circuit is held constant at this “best case” value.

[0083] For this reason, this preferred embodiment will be referred to as a Delay Reduction Technique (“DRT”).

[0084] Additionally, with the DRT, the “worst-case” static power consumption of the circuit remains unchanged. Setting the delay of the circuit at the “best-case” delay of the circuit increases the subthreshold drain current of the circuit at most of the operating temperatures of the circuit. However, the adjustments to the body voltage of the circuit keep the “worst-case” subthreshold drain current, and hence the “worst-case” static power consumption, the same as for a circuit, which is not using the second preferred The static power, in essence, will be controlled.

[0085] The two preferred embodiments briefly discussed above both involve the control of static power consumption due to adjustments in body voltage. These two embodiments also preferably involve maintaining the delay of the circuit at a constant value. Therefore, the two embodiments can be combined in order to tailor a desired amount of subthreshold current adjustment, and thereby reduced power consumption, while also reducing the delay of the circuit by a desired amount.

[0086] One with ordinary skill in the art will easily be able to implement the two embodiments in such a manner as to tailor the circuit characteristics as desired. As one example, the delay of the circuit can be set to a value between the “best-case” and the “worst-case” delay values of the circuit. Then, the delay can be held constant at this level. Such a combined embodiment would render both speed advantages and power consumption advantages.

[0087] On a general level, the first step of both preferred methods is to detect a temperature change in the circuit. Then, as the temperature changes, then next step in the preferred methods is to change the body voltage to the circuit in response to the temperature change such that the static power of the circuit is controlled in a certain manner. Of course, the static power is controlled in such a manner that either the total power consumption is reduced, or the delay of the circuit is “reduced,” as opposed to the typical delay at that operating temperature.

[0088] A change in the temperature of the circuit can be detected in a number of ways. Of course, the temperature can be monitored directly. On the other hand, other values or characteristics of the circuit may be monitored in order to detect a change in temperature. In other words, temperature may be monitored indirectly.

[0089] The method of controlling circuit power consumption and or reducing circuit delay will preferably be implemented by some control structure. The control structure may, for example, comprise a control circuit or other control hardware, among many other possibilities. The control circuit will detect the changing temperature of the circuit, and, responsive to this temperature change, will adjust the body voltage to the circuit. As will be noted below, the control circuit may also be employed with a timing device.

[0090] The First Preferred Embodiment Implemented by Monitoring Delay

[0091] The steps of the first preferred embodiment 50 of the disclosed method are demonstrated in FIG. 3A and FIG. 3B. The depicted and described method will be preferably implemented by a control device, such as a control circuit. The control device may be a separate control circuit specifically designed for the purpose of implementing the preferred method, or it may be a portion of a larger circuit that may, for example, accomplish other tasks. The actual implementation of the control circuit is not critical to the preferred method.

[0092] The control circuit preferably has a system for measuring the delay of the circuit. As delay is a function of circuit temperature, measuring the delay is an indirect measurement of the temperature of the circuit. This measuring system may be a part of the control circuit, or may simply be associated with the control circuit. In the first preferred embodiment, the control circuit has an apparatus that will issue an electronic pulse of a set length and monitor the pulse. This pulse mechanism can be used to measure time.

[0093] The control circuit of the first preferred embodiment also includes a series of test gates built into the same substrate as the circuit to be controlled. This series of test gates can be of any type. For example, the gates may comprise a series of “NOT gates,” a series of “AND gates,” or most preferably, a mixture of different types of logic gates.

[0094] These test gates will be used by the control circuit to monitor the delay of the circuit to be controlled in an indirect manner. A series of gates is preferably used by the control circuit because it is easier to measure the delay of a series of gates. The delay of a typical single gate is usually quite small. It is, therefore, more difficult to measure the very small delay of a single gate.

[0095] The first step in the preferred method, as shown in FIG. 3A, is to compute the “worst-case” delay of the test gates (Block 51). As noted above, the “worst-case” delay of a circuit is the delay of the circuit at the minimum operating temperature of the circuit. The minimum operating temperature of the test gate circuit is known by the manufacturer of the circuit based on the particular characteristics of the circuit. One with ordinary skill in the art can easily determine the minimum operating temperature of the test gate circuit.

[0096] The actual computation of the “worst-case” delay can be accomplished by the control circuit by reference to look up table, database, or by computation based on a functional relationship between the temperature of the circuit and the delay. On the other hand, the “worst-case” delay could be computed by another device, such as for example based on experimentation with the test gates or simulation, and this value stored in a memory register.

[0097] The control circuit sets the length of the electrical pulse equal to the value of the “worst-case” delay of the circuit (Block 52).

[0098] The next two steps (Blocks 53 and 54) of the preferred method are implemented at the same time by the control circuit. The control circuit issues an electronic pulse of a known duration (Block 53). The duration of the pulse, as noted just above, is set to be equivalent to the length of the “worst-case” delay of the test gate circuit.

[0099] At the same time the pulse is started, the control circuit begins switching the test gates (Block 54). For example, the gate voltage of the first gate is changed from a low value (zero) to a high value (one). Of course, this effectively switches the output of the gate. For example, if the first gate is a “NOT gate,” such as the gate depicted in FIG. 2, then the NFET of the first test gate is switched from an “off” configuration, to an “on” configuration and the PFET of the first test gate is switched from an “on” configuration, to an “off” configuration. Thus, in this example, the “output” voltage of the first gate will be switched from an initial value of high voltage to a very low voltage. From a digital perspective, the gate voltage will be switched from a zero to a one, and the output of the first test gate will be switched from a one to a zero.

[0100] The output of this first gate will affect the second gate and cause the second gate to also switch its output. Similarly, the change in the output of the second gate will affect the third gate, and so on until the last test gate is reached.

[0101] The control circuit monitors the electronic pulse and the switching of the test gates. The control circuit preferably compares when the pulse ends to when the last gate in the test gates switches output (Block 56).

[0102] As shown in FIG. 3B, the circuit first tests for the rare case in which the length of the pulse is equivalent to the switching time, or delay, of the test gates (Block 63). If the two times are not equal, then the control circuit determines which finished first (Block 57). If the pulse finished first, this means that the delay of the test gates is greater than the “worst-case” delay (Block 57). Of course, if the last gate switched output prior to the completion of the pulse, then the delay of the test gates is less than the “worst-case” delay (Block 57).

[0103] A change to the delay of the test gates reflects a change to the delay of the overall circuit to be controlled. In the first embodiment, it is the goal of the method to maintain the delay of the test gates equivalent to the “worst-case” delay of the test gates. This will, likewise, maintain the delay of the overall circuit to be controlled at a relatively high level, near or at the “worst-case” delay of the overall circuit. Therefore, if the delay of the test gates decreases, as will happen with increasing circuit temperature, the body voltages of the MOSFETs that make up the circuit to be controlled and the MOSFETs that make up the test gates are adjusted.

[0104] In order to maintain the delay at or near the “worst-case” delay, if the pulse finishes later than the time when the last gate is switched, the control circuit increases a body voltage of the PFETs (Block 58) and decreases a body voltage of the NFETs (Block 59). Although opposite voltage adjustments are made, these adjustments have the same effect on the overall circuit. As noted above, NFETs and PFETs react in an opposite manner to voltages of the same sign. Therefore, in order to affect both NFETs and PFETs in the same manner, the voltage to each should preferably be adjusted in an opposite manner.

[0105] Further, increasing the body voltage of a PFET and decreasing the body voltage of an NFET increases the threshold voltage of both. An increased threshold voltage results in a decreased on-current, which, in turn, results in an increased delay. Thus, if the delay has decreased such that pulse finishes later than the time when the last gate is switched, the preferred method adjusts the body voltage in order to increase the delay back to a level at or near the “worst-case” delay.

[0106] The body voltage can be adjusted according to a relationship to the change in delay. For example, for a decrease in delay of a certain amount, the body voltage may be decreased for PFETs and increased for NFETs by a corresponding amount. Such a relationship can be implemented by an equation, in a look-up table, a database, or the like. However, it is much simpler, and preferable, to merely change the body voltage by a set amount if the delay has changed at all. For example, in the preferred embodiment, the body voltage is changed by 0.01 Volt for every change in the delay of the test gate circuit.

[0107] Of course, if the last gate switches after the pulse has finished, this means that the temperature of the circuit has decreased, and that the delay has increased to a value greater than the computed “worst-case” delay. Therefore, the control circuit decreases the body voltage of the PFETs (Block 61) and increases the body voltage of the NFETs (Block 62).

[0108] Once the adjustment to the body voltage is implemented, if any adjustment is made, the control circuit preferably pauses for approximately 1-2 seconds (Block 64).

[0109] Then, the process may begin again with issuing the electrical pulse (Block 53) and switching the gates of the test gate circuit (Block 54).

[0110] The method described above is only one possible way of measuring the delay of the circuit to be controlled. In essence the described method indirectly measures the delay of the circuit to be controlled by using a series of test gates. As another possible implementation, the control circuit can be configured to measure the delay of the entire circuit to be controlled directly. The control circuit, on the other hand, could measure the delay of only a portion of the circuit to be controlled. In such a case, the delay of the circuit to be controlled would be directly measured by the control circuit.

[0111] The temperature of the circuit likely increases over time from an initial temperature to a normal operating temperature. The above-described first embodiment adjusts the body voltage to the circuit as the temperature of the circuit increases. This, in turn, results in an increase in the threshold voltage of the circuit. As the threshold voltage increases, the subthreshold current will decline. Thus, the above-described technique results in lowering the subthreshold current, and thereby the power consumption of the circuit.

[0112] The First Preferred Embodiment Implemented by Monitoring Temperature

[0113] The first preferred embodiments of the systems and methods described above can also be effected by monitoring the temperature of the circuit to be controlled directly. For example, FIG. 4 reflects the steps involved for this implementation of the first preferred embodiment 70. As with the above-described implementation, the preferred method 70 is implemented by a control circuit for reducing static power consumption of the circuit.

[0114] In this embodiment 70, the first step is to measure the temperature of the circuit (Block 71). The temperature of the circuit is typically measured by a temperature sensor.

[0115] Any temperature sensor can be used by the control circuit. However, the temperature sensor preferably takes the form of a sensor located on the semiconductor.

[0116] After measuring the temperature (Block 71), the control circuit computes the appropriate body voltage value to apply to the circuit (Block 72). The amount of the new body voltage can be computed from an awareness of the particular characteristics of the specific circuit involved. On the other hand, in the preferred embodiment, the control circuit refers to a look-up table or other data structure to arrive at an appropriate body voltage for a given temperature of the circuit. The look-up table may be generated by simulations of the circuit, or actual test data from the circuit.

[0117] As noted, this method implements the first preferred embodiment. Therefore, it is the desire of the method and apparatus to maintain the delay of the circuit at a constant value equivalent to the “worst-case” delay of the circuit. Delay is a function of temperature. As the temperature of the circuit increases, the delay of the circuit decreases. Conversely, as the temperature of the circuit decreases, the delay of the circuit increases. So, in this implementation of the first preferred embodiment, the body voltage is computed such that at the measured temperature, the delay of the circuit is approximately the “worst-case” delay of the circuit.

[0118] Once the new body voltage is computed, the control circuit applies the body voltage (Block 73). Generally, if the temperature of the circuit is greater than the lowest operating temperature of the circuit, the body voltage to the PFETs will be increased, and the body voltage to the NFETs will be decreased in order to hold the delay of the circuit at a steady, “worst-case” level.

[0119] Once the body voltage is adjusted, the control circuit preferably waits for a specified period of time before taking another temperature measurement (Block 74).

[0120] After a period of time has elapsed, the entire process 70 begins again. The pause (Block 74) may be on the order of 1-2 seconds. Of course, the measurement, and corresponding adjustment process could be continuous.

[0121] The Second Preferred Embodiment Implemented by Monitoring Delay

[0122] The steps of the second preferred embodiment 90 of the disclosed method are demonstrated in FIG. 5A and FIG. 5B. As briefly explained above, in the second preferred embodiment, the power consumption of the transistor is controlled in such a manner that the delay of the circuit is kept at a constant level equal to the “best-case” delay of the circuit. That is, the delay is kept constant at the value of the delay at the maximum operating temperature of the circuit, and therefore, maximum subthreshold current of the circuit.

[0123] As with the first preferred embodiment above, the depicted and described method will be preferably implemented by a control device, such as a control circuit. The control circuit preferably has a system for measuring the delay of the circuit. In the second preferred embodiment, the control circuit has an apparatus that will issue an electronic pulse of a set length and monitor the pulse. This pulse mechanism can be used to measure time.

[0124] The control circuit of the second preferred embodiment also includes a series of test gates built into the same substrate as the circuit to be controlled by the method described herein. This series of test gates can be of any type. For example, the gates may comprise a series of “NOT gates,” a series of “AND gates,” or most preferably, a mixture of different types of logic gates. As with the first preferred embodiment, these test gates will be used by the control circuit to monitor the delay of the circuit to be controlled in an indirect manner.

[0125] The first step in the preferred method, as shown in FIG. 5A, is to compute the “best-case” delay of the test gates (Block 91). The “best-case” delay of a circuit is the delay of the circuit at the maximum operating temperature of the circuit. The maximum operating temperature of the test gate circuit is known by the manufacturer of the circuit based on the particular characteristics of the circuit. One with ordinary skill in the art can easily determine the maximum operating temperature of the test gate circuit.

[0126] The actual computation of the “best-case” delay can be accomplished by the control circuit by reference to look-up table, database, or by computation based on a functional relationship between the temperature of the circuit and the delay. On the other hand, the “best-case” delay could be computed by another device, such as for example, by experimentation, and this value stored in a memory register based on experimentation with the test gates or simulations.

[0127] In the next step of the second preferred embodiment, the control circuit sets the length of the electrical pulse equal to this computed “best-case” delay (Block 92).

[0128] The next two steps (Blocks 93, 94) of the second preferred method are implemented at the same time by the control circuit. The control circuit issues an electronic pulse of a known duration (Block 93). The duration of the pulse, as noted just above, is set to be equivalent to the length of the “best-case” delay of the test gate circuit.

[0129] At the same time the pulse is started, the control circuit begins switching the test gates (Block 94). For example, the gate voltage of the first gate is changed from a low value (zero) to a high value (one). Of course, this effectively switches the output of the gate. Similarly, the change in the output of the second gate will affect the third gate, and so on until the last test gate is reached.

[0130] The control circuit monitors the electronic pulse and the switching of the test gates. The control circuit preferably compares when the pulse ends to when the last gate in the test gates switches output (Block 96).

[0131] As shown in FIG. 5B, the circuit first tests for the rare case in which the length of the pulse is equivalent to the switching time, or delay, of the test gates (Block 103). If the two times are not equal, then the control circuit determines which finished first (Block 97). If the pulse finishes first, this means that the delay of the test gates is greater than the “best-case” delay (Block 97). Of course, if the last gate switches output prior to the completion of the pulse, then the delay of the test gates is less than the “best-case” delay (Block 97).

[0132] The changes to the delay of the test gates reflects the changes to the delay of the overall circuit to be controlled. In the second embodiment, it is the goal of the method to maintain the delay of the test gates equivalent to the “best-case” delay of the test gates. This likewise maintains the delay of the overall circuit to be controlled at a relatively low level, near or at the “best-case” delay of the overall circuit. Therefore, if the delay of the test gates decreases, as will happen with increasing circuit temperature, the body voltages of the MOSFETs that make up the circuit to be controlled and the MOSFETs that make up the test gates are adjusted.

[0133] In order to maintain the delay at or near the “best-case” delay, if the pulse finishes later than the last gate is switched, the control circuit increases body voltage of the PFETs (Block 98) and decreases the body voltage of the NFETs (Block 99). Although opposite voltage adjustments are made these adjustments have the same effect on the overall circuit. As noted above, NFETs and PFETs react in an opposite manner to voltages of the same sign. Therefore, in order to affect both NFETs and PFETs in the same manner, the voltage to each should preferably be adjusted in an opposite manner.

[0134] Further, as outlined above in regard to the first preferred embodiment, increasing the body voltage of a PFET and decreasing the body voltage of an NFET increases the threshold voltage of both. An increased threshold voltage results in a decreased on-current, which, in turn, results in an increased delay. Thus, if the delay has decreased such that pulse finishes later than the time when the last gate is switched, the preferred method adjusts the body voltage in order to increase the delay back to a level at or near the “best-case” delay.

[0135] The body voltage can be adjusted according to a relationship to the change in delay. For example, for a decrease in delay of a certain amount, the body voltage may be decreased for PFETs and increased for NFETs by a corresponding amount. Such a relationship can be implemented by an equation, in a look-up table, a database, or the like. However, it is much simpler and preferable to merely change the body voltage by a set amount if the delay has changed at all. For example, in the preferred embodiment, the body voltage will be changed by 0.01 Volt for every change in the delay of the test gate circuit.

[0136] Of course, if the last gate switches after the pulse has finished, this means that the temperature of the circuit has decreased, and that the delay has increased to a value greater than the computed “best-case” delay. Therefore, the control circuit decreases the body voltage of the PFETs (Block 101) and increases the body voltage of the NFETs (Block 102).

[0137] Once the adjustment to the body voltage is implemented, if any adjustment is made, the control circuit preferably pauses for approximately 1-2 seconds (Block 104).

[0138] Then, the process may begin again with issuing the electrical pulse (Block 93) and switching the gates of the test gate circuit (Block 94).

[0139] The method described above is only one possible way of measuring the delay of the circuit to be controlled. In essence the described method indirectly measures the delay of the circuit to be controlled by using a series of test gates. As another possible implementation, the control circuit can be configured to measure the delay of the entire circuit to be controlled directly. The control circuit, on the other hand, could measure the delay of only a portion of the circuit to be controlled. In such a case, the delay of the circuit to be controlled would be directly measured by the control circuit.

[0140] In this second embodiment, the delay is maintained at a very low level, the “best case” delay of the circuit. This is done by adjusting the body voltage to achieve this delay. The adjustment to the body voltage, adjusts the threshold voltage. Basically, in order to decrease the delay from a normal delay at a give operating condition to the “best-case” delay, the threshold voltage should be adjusted. Thus, the power consumption of the circuit is controlled in such as manner is to have the same “worst-case” static power consumption for the circuit.

The Second Preferred Embodiment Implemented by Monitoring Temperature

[0141] The second preferred embodiment of the systems and methods described above can also be implemented by directly monitoring the temperature of the circuit to be controlled. FIG. 6 reflects the preferred steps involved for this implementation of the second preferred embodiment 75. As with the above-described implementation, the preferred method 75 is implemented by a control circuit for reducing the delay of the circuit.

[0142] In this embodiment 75, the first step is to measure the temperature of the circuit (Block 76). As described above with regard to the first preferred embodiment, the temperature may be measured in any appropriate manner.

[0143] After measuring the temperature (Block 76), the control circuit computes the appropriate body voltage value to apply to the circuit (Block 77). The amount of the new body voltage can be computed from an awareness of the particular characteristics of the specific circuit involved. On the other hand, in the preferred embodiment, the control circuit refers to a look-up table or other data structure to arrive at an appropriate body voltage for a given temperature of the circuit. The look-up table may be generated by simulations of the circuit, or actual test data from the circuit.

[0144] As noted, this method implements the second preferred embodiment. Therefore, it is the desire of the method and apparatus to maintain the delay of the circuit at a constant value equivalent to the “best-case” delay of the circuit. Delay is a function of temperature. As the temperature of the circuit increases, the delay of the circuit decreases. Conversely, as the temperature of the circuit decreases, the delay of the circuit increases. So, in this implementation of the first preferred embodiment, the body voltage will be computed such that at the measured temperature, the delay of the circuit is approximately the “best-case” delay of the circuit.

[0145] Once the new body voltage is computed, the control circuit applies the body voltage (Block 78). Generally, if the temperature of the circuit is greater than the lowest operating temperature of the circuit, the body voltage to the PFETs will be increased, and the body voltage to the NFETs will be decreased in order to hold the delay of the circuit at a steady, “best-case” level.

[0146] Once the body voltage is adjusted, the control circuit preferably waits for a specified period of time before taking another temperature measurement (Block 79). After a period of time has elapsed, the entire process 75 begins again. The pause (Block 79) may be on the order of 1-2 seconds. Of course, the measurement, and corresponding adjustment process could be continuous.

[0147] Graphical Representations of the Results of the Preferred Embodiments

[0148] As noted above, the first preferred embodiment is directed to reducing the static power consumption of the transistor by reducing the body voltage as a function of increasing temperature for NFETs in a circuit and increasing the body voltage as a function of increasing temperature for PFETs in a circuit. For this reason, this preferred embodiment may be referred to as a Leakage Reduction Technique (“LRT”).

[0149] The second preferred embodiment, as outlined above, controls the static power consumption of the transistor by keeping the delay constant at a “best-case” operation. At the best case delay, the subthreshold current is maintained at a “worst-case” value, which, in turn, maintains the same “worst-case” static power consumption of the circuit. Maintaining the delay of the circuit at a “best-case” value is a reduction of the typical delay at a particular temperature of operation, as the “best-case” delay only typically occurs at the maximum operating temperature of the circuit. The delay is reduced to its “best-case” value by a reduction in the body voltage of the circuit PFETs and an increase in the body voltage of the circuit NFETs. The body voltage to the NFETs and the PFETs of the circuit is then adjusted to keep the delay of the circuit at its “best-case” value. This preferred embodiment may be referred to as a Delay Reduction Technique (“DRT”).

[0150]
FIG. 7 is a plot of the threshold voltage of a circuit versus operating temperature of the circuit. This plot shows the changes to the threshold voltage for both the first preferred embodiment “LRT” and the second preferred embodiment “DRT.” Note that with the LRT, the threshold voltage is, of course, higher for each temperature. This effectively reduces the leakage current for the circuit at each temperature. Thus, the power consumption of the chip is reduced at each temperature.

[0151] The DRT plot, on the other hand, has a lower threshold voltage for each temperature point plotted. This is because the threshold voltage was lowered in order to decrease the delay of the circuit to its “best-case” value. This means that the subthreshold current has the same “worst-case” value. Then, as the temperature of the circuit increases toward its maximum operating temperature, the control circuit continues to increase the threshold voltage slightly in order to hold the delay of the circuit constant at its “best case” value. So, the control circuit slightly increases the threshold voltage, by modifying the body voltage of the circuit, in order to maintain a constant “best case” delay.

[0152]
FIG. 8 is a plot of subthreshold current of a circuit versus temperature. This figure shows normal operation of the circuit with changing temperature, and also shows the operation of the circuit under LRT and DRT. With the LRT, not surprisingly, the subthreshold current is reduced for each temperature value. This will result in an improvement of the static power dissipation of the circuit. For the situation of using the DRT, for most of the temperature range, the subthreshold current is more than the value of the subthreshold current for operation of the circuit without DRT. However, at the highest operating temperature of the circuit, the subthreshold current while using DRT becomes equal to the subthreshold current without using DRT, which means that the “worst-case” subthreshold current is the same.

[0153]
FIG. 9 is a plot of the on-current versus temperature. As with the two preceding figures, FIG. 8 shows normal operation of the circuit with changing temperature, and also shows the operation of the circuit under LRT and DRT.

[0154] Under LRT, the control circuit maintains a level, low on-current in the circuit. From equation 7 above, it was shown that the gate delay of a circuit is related to the value of the on-current. Thus, as the on-current is held constant with temperature, the gate delay will likewise be held at a constant level. As noted above, this is exactly the goal of the control circuit in the first preferred embodiment.

[0155] Under DRT, the on-current is still relatively level, however, it is much higher than under normal operation of the circuit. From equation 7 above, it was shown that the gate delay of a circuit is inversely proportional to the value of the on-current. Thus, a high value of on-current yields a low value of gate delay.

[0156] Reviewing all of the graphical figures, FIGS. 6-8, when using LRT, the figures show that the body voltage should be changed by 0.26V for the 70 mn ITRS technology generation. In this case, leakage is reduced by 3 times without any increase in the worst-case delay. Using this technique the power consumption is reduced, therefore, a less expensive package is required for the chip. It also enables us to use dynamic logic circuits in future, which suffer from high leakage currents.

[0157] When using DRT, the figures show that using the same 70 nm devices and DRT, the delay is decreased by 10% without any change in the worst-case leakage power.

[0158] It should be understood that the above-described plots are only examples of the results possible with a particular circuit and a particular implementation of the preferred apparatus and method. The preferred system and method are not limited to results in any particular range.

[0159] Use of the Preferred Method with Multiple Threshold Voltage Circuits

[0160] Multiple threshold voltage circuits are gaining more popularity with integrated circuit designers. In these types of integrated circuit or other types of chips, transistors having different threshold voltages are incorporated into the same chip. The theory of the design typically is to use low threshold voltage transistors in the critical path and high threshold voltage transistors in the remainder of the circuit.

[0161] Typically, only a small portion of the circuit comprises a critical path. Therefore most of the circuit is built of high threshold voltage transistors, which will result in low leakage current and low static power dissipation. As temperature is increased, threshold voltage is decreased, which will result in higher switching current or lower delay. The larger the threshold voltage is the higher the percentage change in switching current will be. Therefore circuits with higher threshold voltage are more sensitive to temperature and as a result the systems and methods as described above will be more effective for them.

[0162] Most of the circuit is made of high threshold voltage transistors therefore high power reduction could be achieved through using the preferred system and method for multiple threshold voltage circuits.

[0163] Partitioning the Integrated Circuit Chip

[0164] In the typical embodiment of an integrated circuit (“IC”) chip having many transistors on the chip, different parts of the chip may consume and dissipate different amounts of power. For this reason, the temperatures of different parts of the chip may be different. Obviously, the method disclosed herein depends on the temperature of the circuit. For this reason, it may be desirable to divide the chip into different units.

[0165] In essence, the IC chip can be divided into blocks and the preferred system and method can be applied to each block separately. Because the technique, and responsive reduction in body voltage, may be tailored to different temperature regions, the power consumption of the overall IC chip can be reduced even more by partitioning the chip and treating different groups of transistors separately. Or, if the DRT is used, partitioning the chip will enable the control circuit to reduce the delay of the overall IC chip even more. As a result of using this partitioning technique, different parts of the chip will have different body voltages.

[0166] This leads to the preferred implementation of having separate “wells” for each of the NMOS and PMOS devices of the CMOS circuits. In this way, the bodies of the individual MOS devices are separated and different body voltages can be applied to each if necessary.

[0167] It should be emphasized that the above-described embodiments of the present invention, particularly, any “preferred” embodiments, are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the invention. Many variations and modifications may be made to the above-described embodiment(s) of the invention without departing substantially from the spirit and principles of the invention. All such modifications and variations are intended to be included herein within the scope of this disclosure and the present invention and protected by the following claims.

Controlling circuit power consumption through body voltage control

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CPC

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