Controlling oscillator

Abstract

A voltage controlled oscillator includes a VCO chip that is a monolithic circuit with a Gunn diode and varactor diode intercoupled by a resonant circuit. A detector/discriminator/power divider chip is coupled to the VCO chip through a directional coupler and is a monolithic circuit having a pair of discriminator diodes and amplitude detector diode on a semi-insulating substrate with associated circuit components. Connected-together electrodes of the discriminator diodes are connected to one output of the power divider. An electrode of the amplitude detector diode is connected to the other output of the power divider. Stagger-tuned resonant circuits are coupled to the other electrodes of the discriminator diodes. Conducting portions forming low pass filters couple the amplitude detector diode and the discriminator detector diodes to respective outputs. The outputs of the discriminator and amplitude detector are coupled to respective inputs of an analog divider that provides a ratio signal that is coupled to the - input of a differential amplifier. The + input of the differential amplifier receives a frequency designating potential. The output of the differential amplifier is coupled to the varactor diode.

Description

The present invention relates in general to signal generating and more particularly concerns novel apparatus and techniques for controlling the frequency of an oscillator in the millimeter wave frequency range with exceptionally compact structure capable of being implemented in monolithic circuitry. The invention affords good frequency control with an amplitude insensitive system free of conventional limiters that is especially advantageous at millimeter wave frequencies and also useful at any frequency. Furthermore, novel monolithic circuitry according to the invention provides advantageous thermal, electrical and mechanical properties.

It is an important object of the invention to provide improved apparatus and techniques for signal generation.

According to the invention, there is oscillatory circuit means having a frequency controlling signal input for receiving a frequency controlling signal for controlling the frequency of oscillation of the oscillatory circuit, means for providing a feedback signal representative of the amplitude and frequency of the output signal provided by the oscillatory circuit means, discriminating means responsive to the feedback signal for providing an output signal representative of both frequency and amplitude of the output signal, amplitude detecting means for providing a signal representative of only the amplitude of the output signal, dividing means for combining the latter two signals to provide a ratio signal representative of the frequency of the output signal independently of its amplitude, and means for combining the ratio signal with a frequency designating signal to provide the control signal to maintain the frequency of the output signal substantially corresponding to that designated by the frequency designating signal.

In a specific form of the invention, the source of the feedback signal comprises a directional coupler coupled to power dividing means that provides a signal over parallel paths to the frequency discriminating means and the amplitude detecting means free of limiters. Preferably the oscillatory circuit means comprises a varactor diode and Gunn diode in a monolithic circuit including resonant circuit means for establishing the frequency of oscillation. A pair of diodes comprising the frequency discriminating means, a diode comprising the amplitude detecting means and conductors defining the power dividing means and transmission lines intercoupling the power dividing means, frequency discriminating means, and amplitude detecting means comprises a monolithic circuit.

Numerous other features, objects and advantages of the invention will become apparent from the following specification when read in connection with the accompanying drawing in which:

FIG. 1 is a combined block-schematic diagram of an embodiment of the invention:

FIG. 2 is a plan view of a layout of a package according to the invention schematically representing some components;

FIG. 3 is a plan view of the layout of a detector discriminator power divider chip according to the invention,

FIG. 4 is a plan view of the layout of a controlled oscillator chip according to the invention;

FIGS. 5A-5D illustrate the process of making monolithic circuits according to the invention; and

FIGS. 6A and 6B illustrate an alternate process for making monolithic circuits according to the invention.

With reference now to the drawing and more particularly FIG. 1 thereof, there is shown a combined block-schematic circuit diagram of an exemplary embodiment of the invention. An oscillatory circuit 11, typically comprising a varactor diode, Gunn diode and resonant circuit, has an output branch 12 that provides an output signal of controlled frequency in response to a control signal received on control signal input 13. A directional coupler 14 receives a small portion of the output signal on output 12 and delivers it to power divider 15. The signals from power divider 15 are coupled to discriminator 16 and amplitude detector 17 by transmission lines 18 and 19, respectively.

The signals from discriminator 16 and amplitude detector 17 are coupled to analog divider 21 by lines 22 and 23, respectively. The outpt of divider 21 is coupled to the - input of differential amplifier 24. The + input of differential amplifier 24 receives a frequency designating signal on terminal 25. The output of differential amplifier 24 is coupled to the frequency controlling input of oscillatory circuit 11.

Having described the structural arrangement of the circuit, its mode of operation will be described. Oscillatory circuit 11, typically comprising a varactor diode, Gunn diode and resonant circuit, provides a signal on output line 12, fraction of which is coupled by directional coupler 14 to power divider 15. Directional coupler 14 provides relatively loose coupling to power dividier 15 so that the oscillatory circuit 11 and its output are not adversely affected by the load connected to directional coupler 14 through power divider 15.

Power divider 15 takes the feedback signal provided by directional coupler 14 and divides it preferably substantially equally for delivery over transmission lines 18 and 19 to discriminator 16 and amplitude detector 17, respectively. Discriminator 16 typically comprises staggered tuned circuits arranged in a known manner to produce an S curve having a zero crossover at a predetermined center frequency typically at the center of the tuning range of oscillatory circuit 11. This signal V.sub.d is representative of both the amplitude and frequency of the output signal on output line 12, there being no limiter. Amplitude detector 17 provides a signal V.sub.p representative of only the amplitude of the output signal on output line 12. Analog divider 21 combines the signals from discriminator 16 and amplitude detector 17 to provide a ratio signal that is delivered to the - input of differential amplifier 24 representative of only the frequency of the output signal on output line 12, independently of its amplitude.

Differential amplifier 24 combines this ratio signal with the frequency designating signal V.sub.T applied to terminal 25 connected to the + input of differential amplifier 24 to provide a frequency controlling signal on frequency controlling line 13 that adjusts the frequency of oscillator circuit 11 until the difference between V.sub.T and the ratio signal is substantially zero. Since discriminator 16 is characterized by a linear relationship as a function of frequency for a signficant bandwidth between the resonant frequencies of the staggered tuned circuits, this circuitry establishes a linear relationship between the voltage on terminal 25 and the frequency on output line 12.

Although the invention is useful at all frequencies, it is especially useful at millimeter wave frequencies. It was discovered that limiting circuitry cascaded with a discriminator would not operate satisfactorily for frequency control. To develop adequate power for good limiting, coupling might have to be increased so that it would interfere with the impedance characteristics of the output circuit and/or reduce efficiency by diverting useful power from the local oscillator output to the frequency controlling circuitry.

Referring to FIG. 2, there is shown a plan view of a preferred physical layout of a system according to the invention, with some components schematically represented and some specific parameter values set forth. Certain elements in FIG. 2 may also not be described in detail in connection with the description of FIG. 2; however, illustrated elements may bear reference symbols corresponding to those used in other figures where these elements are described in greater detail. The package includes detector/discriminator chip 31 comprising power divider 15, discriminator 16, amplitude detector 17 and transmission lines 18 and 19. Chip 31 is adjacent to VCO chip 32 comprising oscillatory circuit 11. Circulator chip 33 includes a circulator for transmitting energy from the VCO chip 32 to probe 34 in quartz probe chip 35 that covers the opening in waveguide 36. The circulator on circulator chip 33 transmits energy to probe 34 while energy transmitted from probe 34 is carried to terminating resistance 30.

Analog divider 21 comprises a multipler chip, such as a type AD532 available from Analog Devices, having lines 22 and 23 from discriminator 16 and amplitude detector 17, respectively, connected to the indicated terminals on multiplier chip 21. Operational amplifier 24, may typically comprise an Analog Devices AD518 chip.

Terminal 25 receives the frequency controlling potential V.sub.T, terminal 38 is grounded, terminal 39 receives a 24 volt potential and terminal 40 receives the Gunn diode biasing potential, typically 5 volts, Zener diode Z1 limiting the Gunn diode biasing potential at typically 5.5 volts.

Referring to FIG. 3, there is shown the circuit-side layout of detector/discriminator chip 31. Power divider 15 comprises a directional coupler that delivers energy received from chip 37 to tansmission lines 18 and 19. Transmission line 18 is connected to the junction of diodes 41 and 42 of discriminator 16. Square conducting pads 43 and 44 comprise capacitive elements that resonate with inductive elements comprising conductive strips 45 and 46, respectively, to establish the staggered resonant circuits for establishing the S curve. A D.C. return to the conducting layer on the bottom of the chip is established through directional coupler terminating resistor 47 and via opening 48 filled with n+ material as discussed in greater detail below. Square conducting pad 51 provides the output from discriminator 16 carried on line 22 (FIGS. 1 and 2).

Transmission line 19 couples the other branch of power divider 15 to detecting diode 53. Square conducting pads 54 and 55 coact with inductive strip 56 to form a low-pass filter that provides a signal on pad 55 that is carried on line 23 (FIGS. 1 and 2). A D.C. return for detector diode 53 is established through directional coupler terminating resistor 52 connected through via opening 57 to the conducting layer on the bottom of the chip, typically being filled with n+ material as described below.

Referring to FIG. 4, there is shown the circuit-side layout of VCO chip 32. Gunn diode D1 is diffused into the side of the substrate and has one electrode connected to conducting pad 61 by inductive strip 62 that forms a low pass filter for carrying the Gunn diode bias from terminal 40 (FIG. 2). Varactor diode D2 is also diffused into the device side of the substrate and is coupled by strips 63 and 64, typically a quarter wavelength, to an inductive strip 65 connected to Gunn diode D1 to effectively form a resonant circuit of frequency related to the bias on varactor diode D2. Varactor diode D2 receives a biasing potential applied on pad 66 connected to strip 63 by inductive strip 67 to effectively form a low pass filter. Pad 66 is connected to line 13 (FIGS. 1 and 2).

Chips 31 and 32 typically comprise a semi-insulating substrate, such as gallium arsenide, with a conducting layer on the device side difining a ground plane.

In a process for making the invention for establishing connections between the two surfaces, it is convenient to etch through both sides, fill the etched cavity with n+ material, then grow n on the bottom surface, then etch leaving mesas for the Gunn and varactor diodes, then lay a conducting contact on the Gunn and a rectifying Schottky barrier contact for the varactor diode, then metalize the bottom surface, and lay the circuit on the top surface.

These techniques will be better understood from the following specific example of fabricating chip 32 as a monolithic circuit carrying both Gunn diode D1 and varactor diode D2. Referring to FIGS. 5A-5C, the process will be better understood. According to one aspect of the invention with specific reference to FIG. 5A, the process begins with a semi-insulating GaAs substrate with a grown thick n+ doped layer 62 approximately 15 micrometers thick and a thinner n- layer 63, typically three micrometers thick for a nominal 35 GHz Gunn device. The thickness and carrier concentration of the n- layer 63 is dependent upon the frequency of operation in accordance with known techniques. The n- layer 63 is used for both formation of Gunn diode D1 and varactor diode D2. The n+ layer 62 functions to establish contact to the two diodes. The semi-insulating substrate 61 functions to isolate the two diodes from each other and to be the substrate for the VCO circuitry. Ohmic metal 64 is then deposited on the device side of the substrate and patterned to form Gunn diode D1. A lift-off technique is used to establish the desired pattern in accordance with conventional techniques. The metal contact typically comprises a gold-germanium-nickel alloy deposited by conventional successive evaporations of a gold-germanium eutectic and nickel.

Referring to FIG. 5B, the next step involves etching via holes 65 and 66 from the circuit side of substrate 61 into the n+ epilayer 62. Via holes 65 and 66 are typically about 8 mils thick and stop within a 7 micrometer window. Ohmic metal is deposited in the vias to establish metal layers 67 and 68, and both the Gunn ohmic metal 67 and the varactor ohmic metal 68 are alloyed together over bridge 69.

Referring to FIG. 5C, Schottky metal 71 is deposited on n- layer 63 to form varactor diode D2.

Diodes D1 and D2 are then electrically isolated by mesa etching between the devices, or by etching a donut or ring, like a moat 72 and 73, around each device as shown in FIG. 5D. Circuitry may now be deposited on circuit side of the wafer in accordance with the pattern shown in FIG. 4.

The VCO is now complete, except for dicing into individual chips, bonding and packaging. The device side is preferably bonded to a heat sink package for better operation. To facilitate this bonding, metal is plated on the device side prior to bonding.

Although the process just described may produce satisfactory chips, a preferred process according to the invention omits the need for stopping the etch within the window in the n+ region and provides enhanced mechanical strength. Referring to FIG. 6A, the via holes 65' and 66' are formed first through the circuit side of the semi-insulating GaAs substrate 61' free of epilayers. The via holes 65' and 66' may be formed with wet chemical etching or using reactive ion etching (RIE). The mask 60 used to define each via hole, silicon nitride or silicon dioxide, is also an inhibitor of epitaxial growth. Thus, by leaving the dielectric mask 60 after etching, epitaxial n+ material 67' and 68' may then be grown in the via holes 65' and 66', respectively, by a selective epitaxial process. Because the epi is selective, the growth rate is greatly enhanced so that there is no problem filling the 8-12 mil thick via opening with epi in a reasonable time. It does not matter that the via opening is overfilled because this surface is lapped and polished for subsequent processing.

After the via side is polished, it is stained to delineate the via location so that the devices which are formed on the device side may be properly aligned. The wafer is now lapped and polished on the device side to approximately two mils greater than the final wafer thickness. Using the stained via openings as an alignment aid, the device side is now patterned for a "pocket etch." Referring to FIG. 6B, the pocket etch is similar to the via, but is much less deep. This approach helps to preserve lateral dimensional control. The pocket should be deep enough to penetrate the n+ filled via openings 65' and 66'. After the pocket is defined, n+ epi layer 62' is grown selectively in the pockets from the device side. The device side is now lapped and polished to the desired thickness, and the pocket is stained for an alignment aid.

The n+ vias are now complete, and the n- layer 63' is grown in the conventional manner over the entire device side surface. The circuit side of the wafer is protected from growth with a dielectric layer, such as silicon nitride or silicon dioxide. The n- layer is then patterned over the pockets with the n- material removed from between these n+ regions. The n- material should overlap the n+ material to prevent short circuits or premature breakdown. Alternately, when the pocket dimensions are very small, a dielectric layer may be placed over the exposed n+ area.

Ohmic metal 64' may then be deposited on the Gunn diode n material and on the n+ vias. The same ohmic metal may also be used for the circuit definition 74, 75 on the circuit side. After the ohmic metal is alloyed, the Schottky metal 71' is deposited to form varactor diode D2.

The final step prior to dicing, bonding and packaging is to plate a thick layer of gold 72 upon the device side to aid as a heat sink and bonding metal. The order of the described steps may be varied if desired.

The process may be modified further with fewer steps by forming the via pocket n+ region in one step by making a very deep hole with the RIE or similar etch technique. Although dimensional control of the n+ region on the device side may be difficult, suitable etch recipes for the RIE, other die process etch techniques, such as reactive ion beam etching or sputter etching, may be used, and laser drilling techniques may be used. An important aspect of the process involves providing a channel for n+ growth for conducting material to connect the circuit side of the wafer with the Gunn and varactor diodes on the device side of the wafer.

It is also possible to establish contact between top and bottom surfaces by etching a via opening and metalizing the substrate around the via.

It is also within the principles of the invention to fabricate two or more of chips 31, 32 and 33 on the same substrate.

There has been described novel apparatus and techniques for frequency controlling and methods of manufacture characteraized by numrous features and advantages. It is evident that those skilled in the art may now make numerous uses and modification of and departures from the specific embodiments described herein without departing from the inventive concepts. Consequently, the invention is to be construed as embracing each and every novel feature and every novel combination of features present in or possessed by the apparatus and techniques herein disclosed and limited solely by the spirit and scope of the appended claims.

Claims

1. A monolithic circuit comprising,

a semi-insulating substrate having a device side through which semiconductor devices may be diffused separated by said substrate from a circuit side carrying conductiong material forming circuits,

said substrate having at least a first via opening extending between said device side and said circuit side of said substrate,

said first via opening being filled with n+ material,

a first n- layer on said device side covering said first via opening,

a first ohmic contact on said n- layer coacting therewith to form a semiconductor device,

and a portion of said conducting material on the circuit side of said device in contact with said n+ material in said first opening for establishing contact with said first semiconductor device through said n+ material in said first via opening.

2. A monolithic circuit in accordance with claim 1 and further comprising,

at least a second via opening in said substrate,

said second via opening being filled with n+ material,

a second n- layer in contact with said n+ material in said second via opening covering said second via opening on said device side,

a second ohmic contact on said n- layer coacting therewith to form a second semiconductor device,

a thermally and electrically conducting layer on said device side interconnecting said first and second ohmic contacts,

and a second portion of said conducting material on said circuit side establishing contact with said second semiconductor device through the n+ material in said second via opening.