Patent Application
20150117565
1. Field of the Invention
The present invention relates generally to RF power transmission, modulation, and amplification. More particularly, the invention relates to methods and systems for vector combining power amplification.
2. Background Art
In power amplifiers, a complex tradeoff typically exists between linearity and power efficiency.
Linearity is determined by a power amplifier's operating range on a characteristic curve that relates its input to output variables—the more linear the operating range the more linear the power amplifier is said to be. Linearity is a desired characteristic of a power amplifier. In one aspect, for example, it is desired that a power amplifier uniformly amplifies signals of varying amplitude, and/or phase and/or frequency. Accordingly, linearity is an important determiner of the output signal quality of a power amplifier.
Power efficiency can be calculated using the relationship of the total power delivered to a load divided by the total power supplied to the amplifier. For an ideal amplifier, power efficiency is 100%. Typically, power amplifiers are divided into classes which determine the amplifier's maximum theoretical power efficiency. Power efficiency is clearly a desired characteristic of a power amplifier—particularly, in wireless communication systems where power consumption is significantly dominated by the power amplifier.
Unfortunately, the traditional tradeoff between linearity and efficiency in power amplifiers is such that the more linear a power amplifier is the less power efficient it is. For example, the most linear amplifier is biased for class A operation, which is the least efficient class of amplifiers. On the other hand, higher class amplifiers such as class B, C, D, E, etc, are more power efficient, but are considerably non-linear which can result in spectrally distorted output signals.
The tradeoff described above is further accentuated by typical wireless communication signals. Wireless communication signals, such as OFDM, CDMA, and W-CDMA for example, are generally characterized by their peak-to-average power ratios. The larger the signal's peak to average ratio the more non-linear distortion will be produced when non-linear amplifiers are employed.
Outphasing amplification techniques have been proposed for RF amplifier designs. In several aspects, however, existing outphasing techniques are deficient in satisfying complex signal amplification requirements, particularly as defined by wireless communication standards, for example.
In one aspect, existing outphasing techniques employ an isolating and/or a combining element when combining constant envelope constituents of a desired output signal. For example, it is commonly the case that a power combiner is used to combine the constituent signals. This combining approach, however, typically results in a degradation of output signal power due to insertion loss and limited bandwidth, and, correspondingly, a decrease in power efficiency.
In another aspect, the typically large size of combining elements precludes having them in monolithic amplifier designs.
What is needed therefore are power amplification methods and systems that solve the deficiencies of existing power amplifying techniques while maximizing power efficiency and minimizing non-linear distortion. Further, power amplification methods and systems that can be implemented without the limitations of traditional power combining circuitry and techniques are needed.
Embodiments for vector combining power amplification are disclosed herein.
In one embodiment, a plurality of substantially constant envelope signals are individually amplified, then combined to faun a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal.
In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of substantially constant envelope constituent signals. The constituent signals are amplified, and then re-combined to construct an amplified version of the original time-varying envelope signal.
Embodiments of the invention can be practiced with modulated carrier signals and with baseband information and clock signals. Embodiments of the invention also achieve frequency up-conversion. Accordingly, embodiments of the invention represent integrated solutions for frequency up-conversion, amplification, and modulation.
Embodiments of the invention can be implemented with analog and/or digital controls. The invention can be implemented with analog components or with a combination of analog components and digital components. In the latter embodiment, digital signal processing can be implemented in an existing baseband processor for added cost savings.
One or more of the embodiments provided herein includes one or more samplers. Such samplers can be implemented using any sampling device, including but not limited to those described in U.S. Pat. No. 6,061,551, which is incorporated herein by reference in its entirety.
Additional features and advantages of the invention will be set forth in the description that follows. Yet further features and advantages will be apparent to a person skilled in the art based on the description set forth herein or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure and methods particularly pointed out in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing summary and the following detailed description are exemplary and explanatory and are intended to provide further explanation of embodiments of the invention as claimed.
Embodiments of the present invention will be described with reference to the accompanying drawings, wherein generally like reference numbers indicate identical or functionally similar elements. Also, generally, the leftmost digit(s) of the reference numbers identify the drawings in which the associated elements are first introduced.
The present invention will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.
Methods, apparatuses and systems for vector combining power amplification are disclosed herein.
Vector combining power amplification is an approach for optimizing linearity and power efficiency simultaneously. Generally speaking, and referring to flowchart 502 in
Accordingly, vector combining power amplification allows for non-linear power amplifiers to be used to efficiently amplify complex signals whilst maintaining minimal non-linear distortion levels.
For purposes of convenience, and not limitation, methods and systems of the present invention are sometimes referred to herein as vector power amplification (VPA) methods and systems.
A high-level description of VPA methods and systems according to embodiments of the present invention is now provided. For the purpose of clarity, certain terms are first defined below. The definitions described in this section are provided for convenience purposes only, and are not limiting. The meaning of these temis will be apparent to persons skilled in the art(s) based on the entirety of the teachings provided herein. These terms may be discussed throughout the specification with additional detail.
The term signal envelope, when used herein, refers to an amplitude boundary within which a signal is contained as it fluctuates in the time domain. Quadrature-modulated signals can be described by r(t)=i(t)·cos(ωc·t)+q(t)·sin(ωc·t) where i(t) and q(t) represent in-phase and quadrature signals with the signal envelope e(t), being equal to e(t)=√{square root over (i(t)2+q(t)2)}{square root over (i(t)2+q(t)2)} and the phase angle associated with r(t) is related to arctan (q(t)/i(t).
The term constant envelope signal, when used herein, refers to in-phase and quadrature signals where e(t)=√{square root over (i(t)2+q(t)2)}{square root over (i(t)2+q(t)2)}, with e(t) having a relatively or substantially constant value.
The term time-varying envelope signal, when used herein, refers to a signal having a time-varying signal envelope. A time-varying envelope signal can be described in terms of in-phase and quadrature signals as e(t)=√{square root over (i(t)2+q(t)2)}{square root over (i(t)2+q(t)2)}, with e(t) having a time-varying value.
The term phase shifting, when used herein, refers to delaying or advancing the phase component of a time-varying or constant envelope signal relative to a reference phase.
Time-varying complex signals may also be generated as illustrated in
1.2) Example Generation of Time-Varying Complex Envelope Signals from Constant Envelope Signals
The description in this section generally relates to the operation of step 508 in
In example 1 of
In example 2 of
In example 3 of
In summary, the examples of
It is noted that signals in the examples of
A high-level overview of vector power amplification is now provided.
In the example of
In the example of
where output signal 178 is a power amplified version of input signal 172.
Linear (or substantially linear) power amplification of time-varying complex signals, as illustrated in
Referring to
Still referring to
In the example of
Still referring to
r(t)=I(t)·cos(ωt)+Q(t)·sin(ωt)=R(t)·cos(φ(t))·cos(ωt)+R(t)·sin(φ(t))·sin(φt) (1)
Note that, in the example of
It is further noted, from
In the example of
From
Any phasor of time-varying magnitude and phase can be obtained by the sum of two or more constant magnitude phasors having appropriately specified phase shifts relative to a reference phasor.
For the purpose of illustration, three views are provided in
The example of
Vector power amplification methods and systems according to embodiments of the present invention rely on the ability to decompose any time-varying envelope signal into two or more substantially constant envelope constituent signals or to receive or generate such constituent signals, amplify the constituent signals, and then sum the amplified signals to generate an amplified version of the time-varying complex envelope signal.
In sections 3.1-3.3, vector power amplification (VPA) embodiments of the present invention are provided, including 4-branch and 2-branch embodiments. In the description, each VPA embodiment is first presented conceptually using a mathematical derivation of underlying concepts of the embodiment. An embodiment of a method of operation of the VPA embodiment is then presented, followed by various system level embodiments of the VPA embodiment.
Section 3.4 presents various embodiments of control modules according to embodiments of the present invention. Control modules according to embodiments of the present invention may be used to enable certain VPA embodiments of the present invention. In some embodiments, the control modules are intermediary between an input stage of the VPA embodiment and a subsequent vector modulation stage of the VPA embodiment.
Section 3.5 describes VPA output stage embodiments according to embodiments of the present invention. Output stage embodiments are directed to generating the output signal of a VPA embodiment.
Section 3.6 is directed to harmonic control according to embodiments of the present invention. Harmonic control may be implemented in certain embodiments of the present invention to manipulate the real and imaginary power in the harmonics of the VPA embodiment, thus increasing the power present in the fundamental frequency at the output.
Section 3.7 is directed to power control according to embodiments of the present invention. Power control may be implemented in certain embodiments of the present invention in order to satisfy power level requirements of applications where VPA embodiments of the present invention may be employed.
According to one embodiment of the invention, herein called the Cartesian 4-Branch VPA embodiment for ease of illustration and not limitation, a time-varying complex envelope signal is decomposed into 4 substantially constant envelope constituent signals. The constituent signals are equally or substantially equally amplified individually, and then summed to construct an amplified version of the original time-varying complex envelope signal.
It is noted that 4 branches are employed in this embodiment for purposes of illustration, and not limitation. The scope of the invention covers use of other numbers of branches, and implementation of such variations will be apparent to persons skilled in the art based on the teachings contained herein.
In one embodiment, a time-varying complex envelope signal is first decomposed into its in-phase and quadrature vector components. In phasor representation, the in-phase and quadrature vector components correspond to the signal's real part and imaginary part phasors, respectively.
As described above, magnitudes of the in-phase and quadrature vector components of a signal vary proportionally to the signal's magnitude, and are thus not constant envelope when the signal is a time-varying envelope signal. Accordingly, the 4-Branch VPA embodiment further decomposes each of the in-phase and quadrature vector components of the signal into four substantially constant envelope components, two for the in-phase and two for the quadrature signal components. This concept is illustrated in
In the example of
Still referring to
The phase shifts of phasors {right arrow over (IU
As an example, it can be further verified that, for the case illustrated in
in
wherein I1 and I2 represent the normalized magnitudes of phasors {right arrow over (I1)} and {right arrow over (I2)}, respectively, and wherein the domains of I1 and I2 are restricted appropriately according to the domain over which equation (2) and (3) are valid. It is noted that equations (2) and (3) are one representation for relating the relative phase shifts to the normalized magnitudes. Other, solutions, equivalent representations, and/or simplified representations of equations (2) and (3) may also be employed. Look up tables relating relative phase shifts to normalized magnitudes may also be used.
The concept describe above can be similarly applied to the imaginary phasor or the quadrature component part of a signal r(t) as illustrated in
It follows from the above discussion that, in phasor representation, any phasor {right arrow over (R)} of variable magnitude and phase can be constructed by the sum of four substantially constant magnitude phasor components:
{right arrow over (R)}={right arrow over (IU)}+{right arrow over (IL)}+{right arrow over (QU)}+{right arrow over (QL)};
{right arrow over (IU)}+{right arrow over (IL)}={right arrow over (I)};
{right arrow over (QU)}+{right arrow over (QL)}={right arrow over (Q)};
I
U
=I
L=constant;
Q
U
=Q
L=constant; (4)
where IU, IL, QU, and QL represent the magnitudes of phasors {right arrow over (IU)}, {right arrow over (IL)}, {right arrow over (QU)}, and {right arrow over (QL)}, respectively.
Correspondingly, in the time domain, a time-varying complex envelope sinusoidal signal r(t)=R(t) cos(ωt+φ) is constructed by the sum of four constant envelope signals as follows:
where sgn({right arrow over (I)})=±1 depending on whether {right arrow over (I)} is in-phase or 180° degrees out-of-phase with the positive real axis. Similarly, sgn({right arrow over (Q)})=±1 depending on whether {right arrow over (Q)} is in-phase or 180° degrees out-of-phase with the imaginary axis.
corresponds to the phase shift of {right arrow over (IU)} and {right arrow over (IL)} relative to the real axis. Similarly,
corresponds to the phase shift of {right arrow over (QU)} and {right arrow over (QL)} relative to the imaginary axis.
can be calculated using the equations given in (2) and (3).
Equations (5) can be further simplified as:
It can be understood by a person skilled in the art that, whereas the time domain representations in equations (5) and (6) have been provided for the case of a sinusoidal waveform, equivalent representations can be developed for non-sinusoidal waveforms using appropriate basis functions. Further, as understood by a person skilled in the art based on the teachings herein, the above-describe two-dimensional decomposition into substantially constant envelope signals can be extended appropriately into a multi-dimensional decomposition.
In the example of
Referring to
Still referring to
The actual implementation of each of vector modulators 520, 530, 540, and 550 may vary. It will be understood by a person skilled in the art, for example, that various techniques exist for generating the constant envelope constituents according to the equations in (6).
In the example embodiment of
In each vector modulator 520, 530, 540, 550, the in-phase and quadrature components are multiplied with amplitude information. In
To generate the IU(t) constant envelope constituent signals 525 and 527 are summed using phase splitter 528 or alternate summing techniques. The resulting signal 529 corresponds to the IU(t) component of signal r(t).
In similar fashion as described above, vector modulators 530, 540, and 550, respectively, generate the IL(t), QU(t), and QL(t) components of signal r(t). IL(t), QU(t), and QL(t), respectively, correspond to signals 539, 549, and 559 in
Further, as described above, signals 529, 539, 549, and 559 are characterized by having substantially equal and constant magnitude envelopes. Accordingly, when signals 529, 539, 549, and 559 are input into corresponding power amplifiers (PA) 562, 564, 566, and 568, corresponding amplified signals 563, 565, 567, and 569 are substantially constant envelope signals.
Power amplifiers 562, 564, 566, and 568 amplify each of the signals 529, 539, 549, 559, respectively. In an embodiment, substantially equal power amplification is applied to each of the signals 529, 539, 549, and 559. In an embodiment, the power amplification level of PAs 562, 564, 566, and 568 is set according to the desired power level of output signal r(t).
Still referring to
Signals 573 and 575 are summed using summer 576, as shown in
It must be noted that, in the example of
Operation of the Cartesian 4-Branch VPA embodiment shall now be further described with reference to the process flowchart of
Step 620 includes receiving a clock signal set according to a desired output signal frequency of the desired output signal. In the example of
Step 630 includes processing the I component to generate first and second signals having the output signal frequency. The first and second signals have substantially constant and equal magnitude envelopes and a sum equal to the I component. The first and second signals correspond to the IU(t) and IL(t) constant envelope constituents described above. In the example of
Step 640 includes processing the Q component to generate third and fourth signals having the output signal frequency. The third and fourth signals have substantially constant and equal magnitude envelopes and a sum equal to the Q component. The third and fourth signals correspond to the QU(t) and QL(t) constant envelope constituents described above. In the example of
Step 650 includes individually amplifying each of the first, second, third, and fourth signals, and summing the amplified signals to generate the desired output signal. In an embodiment, the amplification of the first, second, third, and fourth signals is substantially equal and according to a desired power level of the desired output signal. In the example of
Vector power amplifier 700 includes an in-phase (I) branch 703 and a quadrature (Q) branch 705. Each of the I and Q branches further comprises a first branch and a second branch.
In-phase (I) information signal 702 is received by an I Data Transfer Function module 710. In an embodiment, I information signal 702 includes a digital baseband signal. In an embodiment, I Data Transfer Function module 710 samples I information signal 702 according to a sample clock 706. In another embodiment, I information signal 702 includes an analog baseband signal, which is converted to digital using an analog-to-digital converter (ADC) (not shown in
I Data Transfer Function module 710 processes I information signal 702, and determines in-phase and quadrature amplitude information of at least two constant envelope constituent signals of I information signal 702. As described above with reference to
I Data Transfer Function module 710 outputs information signals 722 and 724 used to control the in-phase and quadrature amplitude components of vector modulators 760 and 762. In an embodiment, signals 722 and 724 are digital signals. Accordingly, each of signals 722 and 724 is fed into a corresponding digital-to-analog converter (DAC) 730 and 732, respectively. The resolution and sample rate of DACs 730 and 732 is selected to achieve the desired I component of the output signal 782. DACs 730 and 732 are controlled by DAC clock signals 723 and 725, respectively. DAC clock signals 723 and 725 may be derived from a same clock signal or may be independent.
In another embodiment, signals 722 and 724 are analog signals, and DACs 730 and 732 are not required.
In the exemplary embodiment of
Vector modulators 760 and 762 multiply signals 740-742 with appropriately phased clock signals to generate constant envelope constituents of I information signal 702. The clock signals are derived from a channel clock signal 708 having a rate according to a desired output signal frequency. A plurality of phase splitters, such as 750 and 752, for example, and phasors associated with the vector modulator multipliers may be used to generate the appropriately phased clock signals.
In the embodiment of
In parallel and in similar fashion, the Q branch of vector power amplifier 700 generates at least two constant envelope constituent signals of quadrature (Q) information signal 704.
In the embodiment of
As described above with respect to
Circuitry 714 and 716 (herein referred to as “autobias circuitry” for ease of reference, and not limitation) and in this embodiment, control the bias of PAs 770, 772, 774, and 776 according to I and Q information signals 702 and 704. In the embodiment of
In an embodiment, PAs 770, 772, 774, and 776 apply substantially equal power amplification to respective substantially constant envelope signals 761, 763, 765, and 767. In other embodiments, PA drivers are additionally employed to provide additional power amplification. In the embodiment of
The outputs of PAs 770, 772, 774, and 776 are coupled together to generate output signal 782 of vector power amplifier 700. In an embodiment, the outputs of PAs 770, 772, 774, and 776 are directly coupled together using a wire. Direct coupling in this manner means that there is minimal or no resistive, inductive, or capacitive isolation between the outputs of PAs 770, 772, 774, and 776. In other words, outputs of PAs 770, 772, 774, and 776, are coupled together without intervening components. Alternatively, in an embodiment, the outputs of PAs 770, 772, 774, and 776 are coupled together indirectly through inductances and/or capacitances that result in low or minimal impedance connections, and/or connections that result in minimal isolation and minimal power loss. Alternatively, outputs of PAs 770, 772, 774, and 776 are coupled using well known combining techniques, such as Wilkinson, hybrid, transformers, or known active combiners. In an embodiment, the PAs 770, 772, 774, and 776 provide integrated amplification and power combining in a single operation. In an embodiment, one or more of the power amplifiers and/or drivers described herein are implemented using multiple input, single output power amplification techniques, examples of which are shown in
Output signal 782 includes the I and Q characteristics of I and Q information signals 702 and 704. Further, output signal 782 is of the same frequency as that of its constituents, and thus is of the desired up-converted output frequency. In embodiments of vector power amplifier 700, a pull-up impedance 780 is coupled between the output of vector amplifier 700 and a power supply. Output stage embodiments according to power amplification methods and systems of the present invention will be further described below in section 3.5.
In other embodiments of vector power amplifier 700, process detectors are employed to compensate for any process variations in circuitry of the amplifier. In the embodiment of
The embodiment illustrates a multiple-input single-output (MISO) implementation of the amplifier of
In the embodiment of
DAC 830 receives in-phase and quadrature information signals 810 and 820 from I Data Transfer Function module 710 and Q Data Transfer Function module 712, respectively, as described above. In an embodiment, a input selector 822 selects the order of signals 810 and 820 being input into DAC 830.
DAC 830 may output a single analog signal at a time. In an embodiment, a sample and hold architecture may be used to ensure proper signal timing to the four branches of the amplifier, as shown in
DAC 830 sequentially outputs analog signals 832, 834, 836, 838 to a first set of sample-and-hold circuits 842, 844, 846, and 848. In an embodiment, DAC 830 is clocked at a sufficient rate to emulate the operation of DACs 730, 732, 734, and 736 of the embodiment of
DAC 830's DAC clock signal 826, output selector signal 824, input selector 822, and sample-and-hold clocks 840A-D, and 850 are controlled by a control module that can be independent or integrated into transfer function modules 710 and/or 712.
In an embodiment, sample-and-hold circuits (S/H) 842, 844, 846, and 848 sample and hold the received analog values from DAC 830 according to a clock signals 840A-D. Sample-and-hold circuits 852, 854, 856, and 858 sample and hold the analog values from sample and hold circuits 842, 844, 846, and 848 respectively. In turn, sample-and-hold circuits 852, 854, 856, and 858 hold the received analog values, and simultaneously release the values to vector modulators 760, 762, 764, and 766 according to a common clock signal 850. In another embodiment, sample-and-hold circuits 852, 854, 856, and 858 release the values to optional interpolation filters 731, 733, 735, and 737 which are also anti-aliasing filters. In an embodiment, a common clock signal 850 is used in order to ensure that the outputs of S/H 852, 854, 856, and 858 are time-aligned.
Other aspects of vector power amplifier 800A substantially correspond to those described above with respect to vector power amplifier 700.
Embodiment 800B illustrates another single DAC implementation of the vector power amplifier. However, in contrast to the embodiment of
Other aspects of vector power amplifier 800B substantially correspond to those described above with respect to vector power amplifiers 700 and 800A.
Other aspects of vector power amplifier 800C substantially correspond to those described above with respect to vector power amplifiers 700 and 800A.
Other aspects of vector power amplifier 800D substantially correspond to those described above with respect to vector power amplifiers 700 and 800B.
A Cartesian-Polar-Cartesian-Polar (CPCP) 2-Branch VPA embodiment shall now be described (The name of this embodiment is provided for ease of reference, and is not limiting).
According to the Cartesian-Polar-Cartesian-Polar (CPCP) 2-Branch VPA method, a time-varying complex envelope signal is decomposed into 2 substantially constant envelope constituent signals. The constituent signals are individually amplified, and then summed to construct an amplified version of the original time-varying complex envelope signal. In addition, the phase angle of the time-varying complex envelope signal is determined and the resulting summation of the constituent signals are phase shifted by the appropriate angle.
In one embodiment of the CPCP 2-Branch VPA method, a magnitude and a phase angle of a time-varying complex envelope signal are calculated from in-phase and quadrature components of a signal. Given the magnitude information, two substantially constant envelope constituents are calculated from a normalized version of the desired time-varying envelope signal, wherein the normalization includes implementation specific manipulation of phase and/or amplitude. The two substantially constant envelope constituents are then phase shifted by an appropriate angle related to the phase shift of the desired time-varying envelope signal. The substantially constant envelope constituents are then individually amplified substantially equally, and summed to generate an amplified version of the original desired time-varying envelope signal.
Referring to
Still referring to
The phase shifts of phasors {right arrow over (U′)} and {right arrow over (L′)} relative to {right arrow over (R′)} are set according to the desired magnitude R of {right arrow over (R′)}. In the simplest case, when upper and lower phasors {right arrow over (U′)} and {right arrow over (L′)} are selected to have equal magnitude, upper and lower phasors {right arrow over (U′)} and {right arrow over (L′)} are substantially symmetrically shifted in phase relative to {right arrow over (R′)}. This is illustrated in the example of
It can be verified that, for the case illustrated in
in
where R represents a normalized magnitude of phasor {right arrow over (R′)}.
Equation (7) can further be reduced to
where R represents a normalized magnitude of phasor {right arrow over (R′)}.
Alternatively, any substantially equivalent mathematical equations or other substantially equivalent mathematical techniques such as look up tables can be used.
It follows from the above discussion that, in phasor representation, any phasor {right arrow over (R′)} of variable magnitude and phase can be constructed by the sum of two constant magnitude phasor components:
{right arrow over (R′)}={right arrow over (U′)}+{right arrow over (L′)}
|{right arrow over (U)}|=|{right arrow over (L)}|=A=constant (8)
Correspondingly, in the time domain, a time-varying envelope sinusoidal signal r′(t)=R(t)×cos(ωt) is constructed by the sum of two constant envelope signals as follows:
where A is a constant and
is as shown in equation (7).
From
r′(t)=U′(t)+L′(t);
U′(t)=C cos(ωt)+α sin(ωt);
L′(t)=C cos(ωt)−β sin(ωt); (10)
where C denotes the real part component of phasors {right arrow over (U′)} and {right arrow over (L′)} and is equal to
Note that C is a common component of {right arrow over (U′)} and {right arrow over (L′)}. α and β denote the imaginary part components of phasors {right arrow over (U′)} and {right arrow over (L′)}, respectively.
Accordingly, from equations (12),
As understood by a person skilled in the art based on the teachings herein, other equivalent and/or simplified representations of the above representations of the quantities A, B, and C may also be used, including look up tables, for example.
Note that {right arrow over (Rin)} is shifted by θ degrees relative to {right arrow over (R′)}.
Accordingly, using equations (8), it can be deduced that:
{right arrow over (Rin)}={right arrow over (R′)}ejθ=({right arrow over (U′)}+{right arrow over (L′)})ejθ={right arrow over (U′)}ejθ+{right arrow over (L′)}ejθ (11)
Equations (11) imply that a representation of {right arrow over (Rin)} can be obtained by summing phasors {right arrow over (U′)} and {right arrow over (L′)}, described above, shifted by θ degrees. Further, an amplified output version, {right arrow over (Rout)}, of {right arrow over (Rin)} can be obtained by separately amplifying substantially equally each of the θ degrees shifted versions of phasors {right arrow over (U′)} and {right arrow over (L′)}, and summing them.
Equivalently, in the time domain, it can be shown that:
r
out(t)=U(t)+L(t);
U(t)=K[C cos(ωt+θ)+α sin(ωt+θ)];
L(t)=K[C cos(ωt+θ)−β sin(ωt+θ)]. (12)
where rout(t) corresponds to the time domain signal represented by phasor {right arrow over (Rout)}, U(t) and L(t) correspond to the time domain signals represents by phasors {right arrow over (U)} and {right arrow over (L)}, and K is the power amplification factor.
A person skilled in the art will appreciate that, whereas the time domain representations in equations (9) and (10) have been provided for the case of a sinusoidal waveform, equivalent representations can be developed for non-sinusoidal waveforms using appropriate basis functions.
In the example of
Referring to
Still referring to
Still referring to
Output signals 1040 and 1042 of respective vector modulators 1060 and 1062 correspond, respectively, to the U(t) and L(t) constant envelope constituents of input signal r(t).
As described above, signals 1040 and 1042 are characterized by having substantially equal and constant magnitude envelopes. Accordingly, when signals 1040 and 1042 are input into corresponding power amplifiers (PA) 1044 and 1046, corresponding amplified signals 1048 and 1050 are substantially constant envelope signals.
Power amplifiers 1044 and 1046 apply substantially equal power amplification to signals 1040 and 1042, respectively. In an embodiment, the power amplification level of PAs 1044 and 1046 is set according to the desired power level of output signal r(t). Further, amplified signals 1048 and 1050 are in-phase relative to each other. Accordingly, when summed together, as shown in
In embodiment 1000A, constant envelope signals 1040 and 1042, output from vector modulators 1060 and 1062, are input into MISO PA 1054. MISO PA 1054 is a two-input single-output power amplifier. In an embodiment, MISO PA 1054 may include various elements, such as optional pre-drivers, drivers, power amplifiers, and process detectors (not shown in
Operation of the CPCP 2-Branch VPA embodiment is depicted in the process flowchart 1100 of
The process begins at step 1110, which includes receiving a baseband representation of the desired output signal. In an embodiment, this involves receiving in-phase (I) and quadrature (Q) components of the desired output signal. In another embodiment, this involves receiving magnitude and phase of the desired output signal.
Step 1120 includes receiving a clock signal set according to a desired output signal frequency of the desired output signal. In the example of
Step 1130 includes processing the clock signal to generate a normalized clock signal having a phase shift angle according to the received I and Q components. In an embodiment, the normalized clock signal is a constant envelope signal having a phase shift angle according to a ratio of the I and Q components. The phase shift angle of the normalized clock is relative to the original clock signal. In the example of
Step 1140 includes the processing of the I and Q components to generate the amplitude information required to produce first and second substantially constant envelope constituent signals.
Step 1150 includes processing the amplitude information of step 1140 and the normalized clock signal Rclk to generate the first and second constant envelope constituents of the desired output signal. In an embodiment, step 1150 involves phase shifting the first and second constant envelope constituents of the desired output signal by the phase shift angle of the normalized clock signal. In the example of
Step 1160 includes individually amplifying the first and second constant envelope constituents, and summing the amplified signals to generate the desired output signal. In an embodiment, the amplification of the first and second constant envelope constituents is substantially equal and according to a desired power level of the desired output signal. In the example of
Referring to
In an embodiment, I and Q Data Transfer Function module 1216 processes information signal 1210 to generate information signals 1220, 1222, 1224, and 1226. The operation of I and Q Data Transfer Function module 1216 is further described below in section 3.4.
Referring to
Still referring to
(12.1)
where θ represents the phase of the desired output signal, represented b phasor {right arrow over (Rout)}, in
In the exemplary embodiment of
In other embodiments, information signals 1220, 1222, 1224, and 1226 are generated in analog format and no DACs are required.
Referring to
Still referring to
Vector modulator 1238 combines the two modulated signals to generate Rclk signal 1250. Rclk signal 1250 is a substantially constant envelope signal having the desired output frequency and a phase shift angle according to the I and Q data included in signal 1210.
Still referring to
Vector modulator 1260 combines signal 1240, multiplied with a 90° shifted version of Rclk signal 1250, and signal 1248, multiplied with a 0° shifted version of Rclk signal 1250, to generate output signal 1264. In parallel, vector modulator 1262 combines signal 1242, multiplied with a 90° shifted version of Rclk signal 1250, and signal 1248. modulated with a 0° shifted version of Rclk signal 1250, to generate output signal 1266.
Output signals 1264 and 1266 represent substantially constant envelope signals. Further, phase shifts of output signals 1264 and 1266 relative to Rclk signal 1250 are determined by the angle relationships associated with the ratios α/C and β/C, respectively. In an embodiment, α=−β and therefore output signals 1264 and 1266 are symmetrically phased relative to Rclk signal 1250. With reference to
A sum of output signals 1264 and 1266 results in a channel-clock-modulated signal having the I and Q characteristics of baseband signal r(t). To achieve a desired power level at the output of vector power amplifier 1200, however, signals 1264 and 1266 are amplified to generate an amplified output signal. In the embodiment of
In an embodiment, PAs 1270 and 1272 apply substantially equal power amplification to respective constant envelope signals 1264-1266. In an embodiment, the power amplification is set according to the desired output power level. In other embodiments of vector power amplifier 1200, PA drivers and/or optional pre-drivers are additionally employed to provide additional power amplification capability to the amplifier. In the embodiment of
Respective output signals 1274 and 1276 of PAs 1270 and 1272 are substantially constant envelope signals. Further, when output signals 1274 and 1276 are summed, the resulting signal has minimal non-linear distortion. In the embodiment of
Output signal 1280 represents a signal having the I and Q characteristics of baseband signal r(t) and the desired output power level and frequency. In embodiments of vector power amplifier 1200, a pull-up impedance 1288 is coupled between the output of vector power amplifier 1200 and a power supply. In other embodiments, an impedance matching network 1290 is coupled at the output of vector power amplifier 1200. Output stage embodiments according to power amplification methods and systems of the present invention will be further described below in section 3.5.
In other embodiments of vector power amplifier 1200, process detectors are employed to compensate for any process variations in circuitry of the amplifier. In the exemplary embodiment of
Embodiment 1200A illustrates a multiple-input single-output (MISO) implementation of embodiment 1200. In embodiment 1200A, constant envelope signals 1261 and 1263, output from vector modulators 1260 and 1262, are input into MISO PA 1292. MISO PA 1292 is a two-input single-output power amplifier. In an embodiment, MISO PA 1292 includes elements 1270, 1272, 1282, 1284, and 1286 as shown in the embodiment of
Still referring to
In another implementation, shown in embodiment 1200B of
Other aspects of vector power amplifiers 1200A and 1200B substantially correspond to those described above with respect to vector power amplifier 1200.
In the exemplary embodiment of
DAC 1320 receives information signal 1310 from I and Q Data Transfer Function module 1216. Information signal 1310 includes identical information content to signals 1220, 1222, 1224 and 1226 in the embodiment of
DAC 1320 may output a single analog signal at a time. Accordingly, a sample-and-hold architecture may be used as shown in
DAC 1320 sequentially outputs analog signals 1332, 1334, 1336, 1336 to a first set of sample-and-hold circuits 1342, 1344, 1346, and 1348. In an embodiment, DAC 1230 is clocked at a sufficient rate to replace DACs 1230, 1232, 1234, and 1236 of the embodiment of
DAC 1320's DAC clock signal 1324, output selector signal 1322, and sample-and-hold clocks 1340A-D and 1350 are controlled by a control module that can be independent or integrated into transfer function module 1216.
In an embodiment, sample-and-hold circuits (S/H) 1342, 1344, 1346, and 1348 hold the received analog values and, according to a clock signal 1340A-D, release the values to a second set of sample-and-hold circuits 1352, 1354, 1356, and 1358. For example, S/H 1342 release its value to S/H 1352 according to a received clock signal 1340A. In turn, sample-and-hold circuits 1352, 1354, 1356, and 1358 hold the received analog values, and simultaneously release the values to interpolation filters 1231, 1233, 1235, and 1237 according to a common clock signal 1350. A common clock signal 1350 is used in order to ensure that the outputs of S/H 1352, 1354, 1356, and 1358 are time-aligned.
In another embodiment, a single layer of S/H circuitry that includes S/H 1342, 1344, 1346, and 1348 can be employed. Accordingly, S/H circuits 1342, 1344, 1346, and 1348 receive analog values from DAC 1320, and each releases its received value according to a clock independent of the others. For example, S/H 1342 is controlled by clock 1340A, which may not be synchronized with clock 1340B that controls S/H 1344. To ensure that outputs of S/H circuits 1342, 1344, 1346, and 1348 are time-aligned, delays between clocks 1340A-D are pre-compensated for in prior stages of the amplifier. For example, DAC 1320 outputs signal 1332, 1334, 1336, and 1338 with appropriately selected delays to S/H circuits 1342, 1344, 1346, and 1348 in order to compensate for the time differences between clocks 1340A-D.
Other aspects of vector power amplifier 1300 are substantially equivalent to those described above with respect to vector power amplifier 1200.
In the embodiment of
The embodiment of
Embodiment 1300A also illustrates optional bias control circuitry 1218 and associated bias control signal 1325, 1326, and 1327. Signals 1325, 1326, and 1327 may be used to bias different stages of MISO PA 1360 in certain embodiments.
Other aspects of vector power amplifier 1300A are equivalent to those described above with respect to vector power amplifiers 1200 and 1300.
A Direct Cartesian 2-Branch VPA embodiment shall now be described. This name is used herein for reference purposes, and is not functionally or structurally limiting.
According to the Direct Cartesian 2-Branch VPA embodiment, a time-varying envelope signal is decomposed into two constant envelope constituent signals. The constituent signals are individually amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal.
In one embodiment of the Direct Cartesian 2-Branch VPA embodiment, a magnitude and a phase angle of a time-varying envelope signal are calculated from in-phase and quadrature components of an input signal. Using the magnitude and phase information, in-phase and quadrature amplitude components are calculated for two constant envelope constituents of the time-varying envelope signal. The two constant envelope constituents are then generated, amplified equally or substantially equally, and summed to generate an amplified version of the original time-varying envelope signal Rin.
The concept of the Direct Cartesian 2-Branch VPA will now be described with reference to
As described and verified above with respect to
For the case illustrated in
in
where R represents the normalized magnitude of phasor {right arrow over (R′)}.
In the time domain, it was shown that a time-varying envelope signal, r′(t)=R(t) cos(ωt) for example, can be constructed by the sum of two constant envelope signals as follows:
r′(t)=U′(t)+L′(t);
U′(t)=C×cos(ωt)+α×sin(ωt);
L′(t)=C×cos(ωt)−β×sin(ωt). (14).
where C denotes the in-phase amplitude component of phasors {right arrow over (U′)} and {right arrow over (L′)} and is equal or substantially equal to
(A being a constant). β and β denote the quadrature amplitude components of phasors {right arrow over (U′)} and {right arrow over (L′)}, respectively.
Note that equations (14) can be modified for non-sinusoidal signals by changing the basis function from sinusoidal to the desired function.
{right arrow over (R)}={right arrow over (R′)}×e
jθ=({right arrow over (U′)}+{right arrow over (L′)})×ejθ={right arrow over (U)}+{right arrow over (L)};
{right arrow over (U)}={right arrow over (U′)}×e
jθ;
{right arrow over (L)}={right arrow over (L′)}×e
jθ. (15)
From equations (15), it can be further shown that:
{right arrow over (U)}={right arrow over (U′)}×e
jθ=(C+jα)×ejθ;
{right arrow over (U)}=(C+jα)(cos θ+j sin θ)=(C cos θ−α sin θ)+j(C sin θ+α cos θ). (16)
Similarly, it can be shown that:
{right arrow over (U)}={right arrow over (U′)}×e
jθ=(C+jβ)×ejθ;
{right arrow over (U)}=(C+jα)(cos θ+j sin θ)=(C cos θ−α sin θ)+j(C sin θ+α cos θ). (17)
Equations (16) and (17) can be re-written as:
{right arrow over (U)}=(C cos θ−α sin θ)+j(C sin θ+α cos θ)=Ux+jUy;
{right arrow over (L)}=(C cos θ−β sin θ)+j(C sin θ+β cos θ)=Lx+jLy. (18)
Equivalently, in the time domain:
U(t)=Uxφ1(t)+Uyφ2(t);
L(t)=Lxφ1(t)+Lyφ2(t); (19)
where φ1(t) and φ2(t) represent an appropriately selected orthogonal basis functions.
From equations (18) and (19), it is noted that it is sufficient to calculate the values of α, β, C and sin(Θ) and cos(Θ) in order to determine the two constant envelope constituents of a time-varying envelope signal r(t). Further, α, β and C can be entirely determined from magnitude and phase information, equivalently I and Q components, of signal r(t).
In the example of
Referring to
Still referring to
Accordingly, respective output signals 1540 and 1542 of vector modulators 1520 and 1530 correspond, respectively, to the U(t) and L(t) constant envelope constituents of signal r(t) as described above in equations (19). As described above, signals 1540 and 1542 are characterized by having equal and constant or substantially equal and constant magnitude envelopes.
Referring to
In an embodiment, power amplifiers 1550 and 1560 apply equal or substantially equal power amplification to signals 1540 and 1542, respectively. In an embodiment, the power amplification level of PAs 1550 and 1560 is set according to the desired power level of output signal r(t).
Amplified output signals 1562 and 1564 are substantially constant envelope signals. Accordingly, when summed together, as shown in
In embodiment 1500A, constant envelope signals 1540 and 1542, output from vector modulators 1520 and 1530, are input into MISO PA 1580. MISO PA 1580 is a two-input single-output power amplifier. In an embodiment, MISO PA 1580 may include various elements, such as optional pre-drivers, drivers, power amplifiers, and process detectors (not shown in
Operation of the Direct Cartesian 2-Branch VPA embodiment is depicted in the process flowchart 1600 of
Step 1620 includes receiving a clock signal set according to a desired output signal frequency of the desired output signal. In the example of
Step 1630 includes processing the I and Q components to generate in-phase and quadrature amplitude information of first and second constant envelope constituent signals of the desired output signal. In the example of
Step 1640 includes processing the amplitude information and the clock signal to generate the first and second constant envelope constituent signals of the desired output signal. In an embodiment, the first and second constant envelope constituent signals are modulated according to the desired output signal frequency. In the example of
Step 1650 includes amplifying the first and second constant envelope constituents, and summing the amplified signals to generate the desired output signal. In an embodiment, the amplification of the first and second constant envelope constituents is according to a desired power level of the desired output signal. In the example of
Referring to
In an embodiment, I and Q Data Transfer Function module 1716 processes information signal 1710 to generate information signals 1720, 1722, 1724, and 1726. The operation of I and Q Data Transfer Function module 1716 is further described below in section 3.4.
Referring to
Still referring to
In the exemplary embodiment of
In other embodiments, information signals 1720, 1722, 1724 and 1726 are generated in analog format and no DACs are required.
Referring to
Still referring to
Referring to
Output signals 1754 and 1756 represent constant envelope signals. A sum of output signals 1754 and 1756 results in a carrier signal having the I and Q characteristics of the original baseband signal. In embodiments, to generate a desired power level at the output of vector power amplifier 1700, signals 1754 and 1756 are amplified and then summed. In the embodiment of
In an embodiment, PAs 1760 and 1762 apply equal or substantially equal power amplification to respective constant envelope signals 1754 and 1756. In an embodiment, the power amplification is set according to the desired output power level. In other embodiments of vector power amplifier 1700, PA drivers are additionally employed to provide additional power amplification capability to the amplifier. In the embodiment of
Respective output signals 1764 and 1766 of PAs 1760 and 1762 are substantially constant envelope signals. In the embodiment of
Output signal 1770 represents a signal having the desired I and Q characteristics of the baseband signal and the desired output power level and frequency. In embodiments of vector power amplifier 1700, a pull-up impedance 1778 is coupled between the output of vector power amplifier 1700 and a power supply. In other embodiments, an impedance matching network 1780 is coupled at the output of vector power amplifier 1700. Output stage embodiments according to power amplification methods and systems of the present invention will be further described below in section 3.5.
In other embodiments of vector power amplifier 1700, process detectors are employed to compensate for any process and/or temperature variations in circuitry of the amplifier. In the exemplary embodiment of
In another embodiment of embodiment 1700, shown as embodiment 1700B of
In the exemplary embodiment of
DAC 1820 receives information signal 1810 from I and Q Data Transfer Function module 1716. Information signal 1810 includes identical information content to signals 1720, 1722, 1724, and 1726 in the embodiment of
DAC 1820 may output a single analog signal at a time. Accordingly, a sample-and-hold architecture may be used as shown in
In the embodiment of
DAC 1820's DAC clock signal 1814, output selector signal 1812, and sample-and-hold clocks 1830A-D, and 1840 are controlled by a control module that can be independent or integrated into transfer function module 1716.
In an embodiment, sample-and-hold circuits 1832, 1834, 1836, and 1838 sample and hold their respective values and, according to a clock signal 1830A-D, release the values to a second set of sample-and-hold circuits 1842, 1844, 1846, and 1848. For example, S/H 1832 release's its value to S/H 1842 according to a received clock signal 1830A. In turn, sample-and-hold circuits 1842, 1844, 1846, and 1848 hold the received analog values, and simultaneously release the values to interpolation filters 1852, 1854, 1856, and 1858 according to a common clock signal 1840.
In another embodiment, a single set of S/H circuitry that includes S/H 1832, 1834, 1836, and 1838 can be employed. Accordingly, S/H circuits 1832, 1834, 1836, and 1838 receive analog values from DAC 1820, and each samples and holds its received value according to independent clocks 1830A-D. For example, S/H 1832 is controlled by clock 1830A, which may not be synchronized with clock 1830B that controls S/H 1834. For example, DAC 1820 outputs signals 1822, 1824, 1826, and 1828 with appropriately selected analog values calculated by transfer function module 1716 to S/H circuits 1832, 1834, 1836, and 1838 in order to compensate for the time differences between clocks 1830A-D.
Other aspects of vector power amplifier 1800 correspond substantially to those described above with respect to vector power amplifier 1700.
In the embodiment of
The embodiment of
Other aspects of vector power amplifier 1800A are substantially equivalent to those described above with respect to vector power amplifiers 1700 and 1800.
In some of the above described embodiments, I and Q data transfer functions are provided to transform received I and Q data into amplitude information inputs for subsequent stages of vector modulation and amplification. For example, in the embodiment of
According to the present invention, I and Q Data Transfer Function modules may be implemented using digital circuitry, analog circuitry, software, firmware or any combination thereof.
Several factors affect the actual implementation of a transfer function according to the present invention, and vary from embodiment to embodiment. In one aspect, the selected VPA embodiment governs the amplitude information output of the transfer function and associated module. It is apparent, for example, that I and Q Data Transfer Function module 1216 of the CPCP 2-Branch VPA embodiment 1200 differs in output than I and Q Data Transfer Function module 1716 of the Direct Cartesian 2-Branch VPA embodiment 1700.
In another aspect, the complexity of the transfer function varies according to the desired modulation scheme(s) that need to be supported by the VPA implementation. For example, the sample clock, the DAC sample rate, and the DAC resolution are selected in accordance with the appropriate transfer function to construct the desired output waveform(s).
According to the present invention, transfer function embodiments may be designed to support one or more VPA embodiments with the ability to switch between the supported embodiments as desired. Further, transfer function embodiments and associated modules can be designed to accommodate a plurality of modulation schemes. A person skilled in the art will appreciate, for example, that embodiments of the present invention may be designed to support a plurality of modulation schemes (individually or in combination) including, but not limited to, BPSK, QPSK, OQPSK, DPSK, CDMA, WCDMA, W-CDMA, GSM, EDGE, MPSK, MQAM, MSK, CPSK, PM, FM, OFDM, and multi-tone signals. In an embodiment, the modulation scheme(s) may be configurable and/or programmable via the transfer function module.
Step 1920 includes calculating a phase shift angle between first and second substantially equal and constant envelope constituents of the I component. In parallel, step 1920 also includes calculating a phase shift angle between first and second substantially equal and constant envelope constituents of the Q component. As described above, the first and second constant envelope constituents of the I components are appropriately phased relative to the I component. Similarly, the first and second constant envelope constituents of the Q components are appropriately phased relative to the Q component. In the embodiment of
Step 1930 includes calculating in-phase and quadrature amplitude information associated with the first and second constant envelope constituents of the I component. In parallel, step 1930 includes calculating in-phase and quadrature amplitude information associated with the first and second constant envelope constituents of the Q component. In the embodiment of
Step 1940 includes outputting the calculated amplitude information to a subsequent vector modulation stage. In the embodiment of
Referring to
Components 2020 and 2022 output the measured I and Q magnitude information to components 2030 and 2032, respectively, of transfer function module 2000. In an embodiment, the measured I and Q magnitude information is in the form of digital signals. Based on the I magnitude information, component 2030 calculates a phase shift angle φ1 between first and second equal and constant or substantially equal and constant envelope constituents of the sampled I signal. Similarly, based on the Q magnitude information, component 2032 calculates phase shift angle φQ between a first and second equal and constant or substantially equal and constant envelope constituents of the sampled Q signal. This operation shall now be further described.
In the embodiment of
Referring to
Components 2040 and 2042 output the calculated amplitude information to subsequent stages of the vector power amplifier. In embodiments, each of the four calculated values is output separately to a digital-to-analog converter. As shown in the embodiment of
Step 2120 includes determining the magnitudes |I| and |Q| of the received I and Q data components.
Step 2130 includes calculating a magnitude |R| of the baseband signal based on the measured |I| and |Q| magnitudes. In an embodiment, |R| is such that |R|2=|I|2+|Q|2. In the embodiment of
Step 2140 includes normalizing the measured |I| and |Q| magnitudes. In an embodiment, |I| and |Q| are normalized to generate an Iclk_phase and Qclk_phase signals (as shown in
Step 2150 includes calculating in-phase and quadrature amplitude information associated with first and second constant envelope constituents. In the embodiment of
Step 2160 includes outputting the generated Iclk_phase and Qclk_phase (from step 2140) and the calculated amplitude information (from step 2150) to appropriate vector modulators. In the embodiment of
In an embodiment, transfer function module 2200 samples I and Q data signal 2210 according to a sampling clock 2212. Sampled I and Q data signals are received by component 2220 of transfer function module 2200. Component 2220 measures the magnitudes |{right arrow over (I)}| and |{right arrow over (Q)}| of the sampled I and Q data signals.
Based on the measured |{right arrow over (I)}| and |{right arrow over (Q)}| magnitudes, component 2230 calculates the magnitude |R| of the baseband signal. In an embodiment, |{right arrow over (R)}| is such that |{right arrow over (R)}|2=|{right arrow over (I)}|2+|{right arrow over (Q)}|2.
In parallel, component 2240 normalizes the measured |{right arrow over (I)}| and |{right arrow over (Q)}| magnitudes. In an embodiment, |{right arrow over (I)}| and |{right arrow over (Q)}| are normalized to generate Iclk_phase and Qclk_phase signals such that |Iclk_phase|2+|Qclk_phase|2=constant, where |Iclk_phase| and |Qclk_phase| represent normalized magnitudes of |{right arrow over (I)}| and |{right arrow over (Q)}|. Typically, given that the constant has a value A, the measured |{right arrow over (I)}| and |{right arrow over (I)}| magnitudes are both divided by the quantity
Component 2250 receives the calculated |{right arrow over (R)}| magnitude from component 2230, and based on it calculates a phase shift angle φ between first and second constant envelope constituents. Using the calculated phase shift angle φ, component 2050 then calculates in-phase and quadrature amplitude information associated with the first and second constant envelope constituents.
In the embodiment of
Referring to
Step 2320 includes determining the magnitudes |I| and |Q| of the received I and Q data components.
Step 2330 includes calculating a magnitude |R| of the baseband signal based on the measured |I| and |Q| magnitudes. In an embodiment, |R| is such that |R|2=|I|2+|Q|2. In the embodiment of
Step 2340 includes calculating a phase shift angle θ of the baseband signal based on the measured |I| and |Q| magnitudes. In an embodiment, θ is such that
and wherein the sign of I and Q determine the quadrant of θ. In the embodiment of
Step 2350 includes calculating in-phase and quadrature amplitude information associated with a first and second constant envelope constituents of the baseband signal. In the embodiment of
Step 2360 includes outputting the calculated amplitude information to DAC's for input into the appropriate vector modulators. In the embodiment of
In an embodiment, transfer function module 2400 samples I and Q data signal 2410 according to a sampling clock 2412. Sampled I and Q data signals are received by component 2420 of transfer function module 2200. Component 2420 measures the magnitudes |{right arrow over (I)}| and |{right arrow over (Q)}| of the sampled I and Q data signals.
Based on the measured |{right arrow over (I)}| and |{right arrow over (Q)}| magnitudes, component 2430 calculates the magnitude |{right arrow over (R)}|. In an embodiment, |{right arrow over (R)}| is such that |{right arrow over (R)}|2=|{right arrow over (I)}|2+|{right arrow over (Q)}|2.
In parallel, component 2240 calculates the phase shift angle θ of the baseband signal. In an embodiment, θ is such that
where the sign of I and Q determine the quadrant of θ.
Component 2450 receives the calculated |{right arrow over (R)}| magnitude from component 2430, and based on it calculates a phase shift angle φ between first and second constant envelope constituent signals. In the embodiment of
In parallel, component 2450 receives the calculated phase shift angle θ from component 2440. As functions of φ and θ, component 2450 then calculates in-phase and quadrature amplitude information for the vector modulator inputs that generate the first and second constant envelope constituents. In an embodiment, the in-phase and quadrature amplitude information supplied to the vector modulators are according to the equations provided in (18).
Component 2450 outputs the calculated amplitude information to subsequent stages of the vector power amplifier. In embodiments, the output values are separately output to digital-to-analog converters. As shown in the embodiment of
Embodiments of f(|I|), f(|Q|) of
According to the present invention, any periodic waveform that can be represented by a Fourier series and a Fourier transform can be decomposed into two or more constant envelope signals.
Below are provided two examples for sinusoidal and square waveforms.
Consider a time-varying complex envelope sinusoidal signal r(t). In the time domain, it can be represented as:
r(t)=R(t)sin(ωt+δ(t)) (20)
where R(t) represents the signal's envelope magnitude at time t, δ(t) represents the signal's phase shift angle at time t, and ω represents the signal's frequency in radians per second.
It can be verified that, at any time instant t, signal r(t) can be obtained by the sum of two appropriately phased equal and constant or substantially equal and constant envelope signals. In other words, it can be shown that:
R(t)sin(ωt+δ(t))=A sin(ωt)+A sin(ωt+φ(t)) (21)
for an appropriately chosen phase shift angle φ(t) between the two constant envelope signals. The phase shift angle φ(t) will be derived as a function of R(t) in the description below. This is equivalent to the magnitude to phase shift transform for sinusoidal signals.
Using a sine trigonometric identity, equation (21) can be re-written as:
R(t)sin(ωt+δ(t))=A sin(ωt)+A sin(ωt)cos φ(t)+A sin(φ(t))cos ωt;
R(t)sin(ωt+δ(t))=A sin(φ(t))cos ωt+A(1+cos φ(t))sin ωt. (22)
Note, from equation (22), that signal r(t) is written as a sum of an in-phase component and a quadrature component. Accordingly, the envelope magnitude R(t) can be written as:
R(t)=√{square root over ((A sin(φ(t)))2+(A(1+cos(φ(t))))2)}{square root over ((A sin(φ(t)))2+(A(1+cos(φ(t))))2)};
R(t)=√{square root over (2A(A+cos(φ(t))).)} (23)
Equation (23) relates the envelope magnitude R(t) of signal r(t) to the phase shift angle (t) between two constant envelope constituents of signal r(t). The constant envelope constituents have equal or substantially equal envelope magnitude A, which is typically normalized to 1.
Inversely, from equation (23), the phase shift angle φ(t) can be written as a function of R(t) as follows:
Equation (24) represents the magnitude to phase shift transform for the case of sinusoidal signals, and is illustrated in
Signal 2830 results from combining signals 2810 and 2820. According to embodiments of the present invention, signal 2830 will have a magnitude equal or substantially equal to a product of signals 2810 and 2820. In other words, signal 2830 will have a magnitude of zero whenever either of signals 2810 or 2820 has a magnitude of zero, and a non-zero magnitude when both signals 2810 and 2820 have non-zero magnitudes.
Further, signal 2830 represents a pulse-width-modulated signal. In other words, the envelope magnitude of signal 2830 is determined according to the pulse width of signal 2830 over one period of the signal. More specifically, the envelope magnitude of signal 2830 is equal or substantially to the area under the curve of signal 2830.
Referring to
radians.
Still referring to
R=A
1
×A
2×(γT−t′) (25)
Accordingly, it can be deduced that φ is related to R according to:
Note, from equation (26), that R is at a maximum of γA1A2 when φ=0. In other words, the envelope magnitude is at a maximum when the two constant envelope signals are in-phase with each other.
In typical implementations, signals 2810 and 2820 are normalized and have equal or substantially equal envelope magnitude of 1. Further, signals 2810 and 2820 typically have a duty cycle of 0.5. Accordingly, equation (26) reduces to:
Equation (27) illustrates the magnitude to phase shift transform for the case of normalized and equal or substantially equal envelope magnitude square wave signals. Equation (27) is illustrated in
In certain embodiments, magnitude to phase shift transforms may not be implemented exactly as theoretically or practically desired. In fact, several factors may exist that require adjustment or tuning of the derived magnitude to phase shift transform for optimal (or at least improved) operation. In practice, phase and amplitude errors may exist in the vector modulation circuitry, gain and phase imbalances can occur in the vector power amplifier branches, and distortion may exist in the MISO amplifier itself including but not limited to errors introduced by directly combining at a single circuit node transistor outputs within the MISO amplifier described herein. Each of these factors either singularly or in combination will contribute to output waveform distortions that result in deviations from the desired output signal r(t). When output waveform distortion exceeds system design requirements, waveform distortion compensation may be required.
According to embodiments of the present invention, waveform distortions can be measured, calculated, or estimated during the manufacture of the system and/or in real time or non-real time operation.
In other embodiments, the measured, calculated, or estimated waveform distortions are compensated for at the transfer function stage of the power amplifier. In this approach, the transfer function is designed to factor in and correct the measured, calculated, and/or estimated waveform distortions.
In some embodiments, in practice, amplitude and phase components of the phasor corresponding to R*sin({acute over (ω)}*t+δ) are compared to the desired phasor {right arrow over (R)} to generate system amplitude and phase error deviations. These amplitude and phase error deviations from the desired phasor {right arrow over (R)}, as shown in
Accordingly, given the fact that equations such as equation (28) can be used to calculate the resultant phasor at any instant in time based on the values of A1 and A2 and φe1(t) and φe2(t), transfer function modification(s) can be made to compensate for the system errors, and such transfer function modification(s) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Exemplary methods for generating error tables and/or mathematical functions to compensate for system errors are described in Section 4.1.2. It will be apparent to persons skilled in the relevant art(s) that these waveform distortion correction and compensation techniques can be implemented in either the digital or the analog domains, and implementation of such techniques will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.
An aspect of embodiments of the present invention lies in summing constituent signals at the output stage of a vector power amplifier (VPA). This is shown, for example, in
In the example of
In another aspect, output stage embodiments of the present invention can be implemented using multiple-input single-output (MISO) power amplifiers.
In another aspect, output stage embodiments of the present invention can be controlled to increase the power efficiency of the amplifier by controlling the output stage current according to the desired output power level.
In what follows, various output stage embodiments according to VPA embodiments of the present invention are provided in section 3.5.1. In section 3.5.2, embodiments of output stage current shaping functions, for increasing the power efficiency of certain VPA embodiments of the present invention, are presented. Section 3.5.3 describes embodiments of output stage protection techniques that may be utilized for certain output stage embodiments of the present invention.
PA branches 3005-{1, . . . , n} apply equal or substantially equal power amplification to respective signals 3010-{1, . . . , n}. In an embodiment, the power amplification level through PA branches 3005-{1, . . . , n} is set according to a power level requirement of the desired output signal.
In the embodiment of
To generate the desired output signal, outputs of PA branches 3005-{1, . . . , n} are coupled directly at summing node 3050. Summing node 3050 provides little or no isolation between the coupled outputs. Further, summing node 3050 represents a relatively lossless summing node. Accordingly, minimal power loss is incurred in summing the outputs of PAs 3040-{1, . . . , n}.
Output signal 3060 represents the desired output signal of output stage 3000. In the embodiment of
In the above-described embodiments of
According to embodiment 3600, PA's 3620-{1, . . . , n} include switching power amplifiers. In the example of
Embodiments are not limited to npn BJT implementations as described herein. A person skilled in the art will appreciate, for example, that embodiments of the present invention may be implemented using pnp BJTs, CMOS, NMOS, PMOS, or other type of transistors. Further, embodiments can be implemented using GaAs and/or SiGe transistors with the desired transistor switching speed being a factor to consider.
Referring back to
Referring to
Still referring to
It is noted that, in the embodiment of
In another aspect, output stage embodiments can be implemented using multiple-input single-output (MISO) power amplifiers.
It is noted that MISO implementations, similar to the one shown in
Referring to
Still referring to
Embodiment 5110D represents an npn implementation of the two-input single output PA building block. Embodiment 5110D includes two npn transistors coupled together using a common collector node, which provides the output of the PA. A pull-up impedance (not shown) can be coupled between the common collector node and a supply node (not shown).
Embodiment 5130D represents a pnp equivalent of embodiment 5110D. Embodiment 5130D includes two pnp transistors coupled at a common collector node, which provides the output of the PA. A pull-down impedance (not shown) can be coupled between the common collector node and a ground node (not shown).
Embodiment 5140D represents a complementary npn/pnp implementation of the two-input single output PA building block. Embodiment 5140D includes an npn transistor and a pnp transistor coupled at a common collector node, which provides the output of the PA.
Still referring to
Embodiment 5160D represents an PMOS equivalent of embodiment 5120D. Embodiment 5120D includes two PMOS transistors coupled at a common drain node, which provides the output of the PA.
Embodiment 5150D represents a complementary MOS implementation of the two-input single-output PA building block. Embodiment 5150D includes a PMOS transistor and an NMOS transistor coupled at common drain node, which provides the output of the PA.
Two-input single-output embodiments of
Embodiment 5150E represents an npn implementation of a multiple-input single-output PA. Embodiment 5150E includes a plurality of npn transistors coupled together using a common collector node, which provides the output of the PA. A pull-up impedance (not shown) can be coupled between the common collector node and a supply voltage (not shown). Note that an n-input single-output PA according to embodiment 5150E can be obtained by coupling additional npn transistors to the two-input single-output PA building block embodiment 5110D.
Embodiment 5170E represents a pnp equivalent of embodiment 5150E. Embodiment 5170E includes a plurality of pnp transistors coupled together using a common collector node, which provides the output of the PA. A pull-down impedance (not shown) may be coupled between the common collector node and a ground node (not shown). Note than an n-input single-output PA according to embodiment 5170E can be obtained by coupling additional pnp transistors to the two-input single-output PA building block embodiment 5130D.
Embodiments 5110E and 5130E represent complementary npn/pnp implementations of a multiple-input single-output PA. Embodiments 5110E and 5130E may include a plurality of npn and/or pnp transistors coupled together using a common collector node, which provides the output of the PA. Note that an n-input single-output PA according to embodiment 5110E can be obtained by coupling additional npn and/or pnp transistors to the two-input single-output PA building block embodiment 5140D. Similarly, an n-input single-output PA according to embodiment 5130E can be obtained by coupling additional npn and/or pnp transistors to the two-input single-output PA building block embodiment 5130D.
Embodiment 5180E represents an PMOS implementation of a multiple-input single-output PA. Embodiment 5180E includes a plurality of PMOS transistors coupled together using a common drain node, which provides the output of the PA. Note that an n-input single-output PA according to embodiment 5180E can be obtained by coupling additional NMOS transistors to the two-input single-output PA building block embodiment 5160D.
Embodiment 5160E represents a NMOS implementation of multiple-input single-output PA. Embodiment 5160E includes a plurality of NMOS transistors coupled together using a common drain node, which provides the output of the PA. Note that an n-input single-output PA according to embodiment 5160E can be obtained by coupling additional PMOS transistors to the two-input single-output PA building block embodiment 5120D.
Embodiments 5120E and 5140E complementary MOS implementations of a multiple-input single-output PA. Embodiments 5120E and 5140E include a plurality of npn and pnp transistors coupled together using a common drain node, which provides the output of the PA. Note that a n-input single-output PA according to embodiment 5120E can be obtained by coupling additional NMOS and/or PMOS transistors to the two-input single-output PA building block 5150D. Similarly, an n-input single-output PA according to embodiment 5140E can be obtained by coupling additional NMOS and/or PMOS transistors to the two-input single-output PA building block 5160D.
It must be noted that the multiple-input single-output embodiments described above may each correspond to a single or multiple branches of a PA. For example, referring to
It is further noted that the transistors shown in the embodiments of
Still referring to
Embodiments of the output stage and optional pre-driver and driver stage bias and current control techniques according to embodiments of the present invention are described below. In certain embodiments, output stage current control functions are employed to increase the output stage efficiency of a vector power amplifier (VPA) embodiment In other embodiments, output stage current control is used to provide output stage protection from excessive voltages and currents which is further describe in section 3.5.3. In embodiments, output stage current control functions are performed using the Autobias module described above with reference to
According to embodiments of the present invention, power efficiency of the output stage of a VPA can be increased by controlling the output stage current of the VPA as a function of the output power and the envelope of the output waveform.
Note that Iout signal 4020 varies as a function of envelope signal 3920. Accordingly, Iout signal 4020 is at the maximum when a maximum output power is required, but decreases as the required output power goes down. Particularly, Iout signal 4020 approaches zero as the associated output power goes to zero. Accordingly, a person skilled in the art will appreciate that output stage current control, according to embodiments of the present invention, results in significant power savings and increases the power efficiency of the power amplifier.
According to embodiments of the present invention, output stage current control may be implemented according to a variety of functions. In an embodiment, the output stage current can be shaped to correspond to the desired output power of the amplifier. In such an embodiment, the output stage current is a function that is derived from the envelope of the desired output signal, and the power efficiency will increase.
In implementation, several approaches exist for performing output stage current control. In some embodiments, output stage current shaping is performed using the Autobias module. The Autobias module is illustrated as autobias circuitry 714 and 716 in the embodiments of
Output stage current control using Autobias is depicted in process flowchart 4800 of the embodiment of
Step 4820 includes calculating a signal according to the output power and output envelope signal information. In embodiments, an Autobias signal is calculated as a function of some measure of the desired output power. For example, the Autobias signal may be calculated as a function of the envelope magnitude of the desired output signal. Referring to the embodiments of
Step 4830 includes applying the calculated signal at an output stage of the VPA, thereby controlling a current of the output stage according to the output power of the desired output signal. In embodiments, step 4830 includes coupling the Autobias signal at the PA stage input of the VPA. This is illustrated, for example, in the embodiments of
In other embodiments, step 4830 includes coupling the Autobias signal using pull-up impedances at the PA stage input and optionally the inputs of the driver and optional pre-driver stages of the VPA.
Embodiments for implementing the Autobias circuitry described above will now be provided.
In embodiment 2700A, Autobias circuitry 2700A includes an Autobias Transfer Function module 2712, a DAC 2714, and an optional interpolation filter 2718. Autobias circuitry 2700A receives an I and Q Data signal 2710. Autobias Transfer Function module 2712 processes the received I and Q Data signal 2710 to generate an appropriate bias signal 2713. Autobias Transfer Function module 2712 outputs bias signal 2713 to DAC 2714. DAC 2714 is controlled by a DAC clock 2716 which may be generated in Autobias transfer module 2712. DAC 2714 converts bias signal 2713 into an analog signal, and outputs the analog signal to interpolation filter 2718. Interpolation filter 2718, which also serves as an anti-aliasing filter, shapes the DAC's output to generate Autobias signal 2720, illustrated as Bias A in embodiment 5112G. Autobias signal 2720 may be used to bias the PA stage and/or the driver stage, and/or the optional pre-driver stage of the amplifier. In an embodiment, Autobias signal 2720 may have several other Autobias signals derived therefrom to bias different stages within the PA stage. This can be done using additional circuitry not included in embodiment 2700A.
In contrast, embodiment 2700B illustrates an Autobias circuitry embodiment in which multiple Autobias signals are derived within the Autobias circuitry. As shown in embodiment 2700B, circuit networks 2722, 2726, and 2730, illustrated as circuit networks A, B, and C in embodiment 2700B, are used to derive Autobias signals 2724 and 2728 from Autobias signal 2720. Autobias signals 2720, 2724, and 2728 are used to bias different amplification stages.
Embodiment 2700C illustrates another Autobias circuitry embodiment in which multiple Autobias signals are generated independently within the Autobias Transfer Function module 2712. In embodiment 2700C, Autobias Transfer Function module 2712 generates multiple bias signals according to the received I and Q Data signal 2710. The bias signals may or may not be related. Autobias Transfer Function module 2712 outputs the generated bias signals to subsequent DACs 2732, 2734, and 2736. DACs 2732, 2734, and 2736 are controlled by DAC clock signals 2733, 2735, and 2737, respectively. DACs 2732, 2734, and 2736 convert the received bias signals into analog signals, and output the analog signals to optional interpolation filters 2742, 2744, and 2746. Interpolation filters 2742, 2744, and 2746, which also serve as anti-aliasing filters, shape the DACs outputs to generate Autobias signals 2720, 2724, and 2728. Similar to embodiment 2700B, Autobias signals 2720, 2724, and 2728 are used to bias different amplification stages such as the optional pre-driver, driver, and PA.
As noted above, Autobias circuitry embodiments according to the present invention are not limited to the ones described in embodiments 2700A, 2700B, and 2700C. A person skilled in the art will appreciate, for example, that Autobias circuitry can be extended to generate any number of bias control signals as required to control the bias of various stages of amplification, and not just three as shown in embodiments 5200B and 5200C, for example.
As described above, output stage embodiments according to embodiments of the present invention are highly power efficient as a result of being able to directly couple outputs at the PA stage using no combining or isolating elements. Certain output stage embodiments in certain circumstances and/or applications, however, may require additional special output stage protection measures in order to withstand such direct coupling approach. This may be the case for example for output stage embodiments such as 5110D, 5120D, 5130D, 5160D, 5150E, 5160E, 5170E, and 5180E illustrated in
In one aspect, transistors of distinct branches of a PA stage should generally not simultaneously be in opposite states of operation for extended periods of time. Following a restart or power on with no inputs being supplied to the final PA stages, transients within the PA branches may cause this mode to occur resulting in the PA stage transistors potentially damaging one another or circuit elements connected to the output. Accordingly, embodiments of the present invention further constrain the Autobias module to limit the output current in the PA stage.
In another aspect, it may be desired to ensure that the Autobias module limits the output voltages below the breakdown voltage specification of the PA stage transistors. Accordingly, in embodiments of the present invention, such as the one illustrated in
A person skilled in the art will appreciate that other output stage protection techniques may also be implemented. Furthermore, output stage protection techniques may be implementation specific. For example, depending on the type of PA stage transistors (npn, pnp, NMOS, PMOS, npn/pnp, NMOS/PMOS), different protection functions may be required.
According to embodiments of the present invention, an underlying principle for each branch PA is to maximize the transfer of power to a fundamental harmonic of the output spectrum. Typically, each branch PA may be multi-stage giving rise to a harmonically rich output spectrum. In one aspect, transfer of real power is maximized for the fundamental harmonic. In another aspect, for non-fundamental harmonics, real power transfer is minimized while imaginary power transfer may be tolerated. Harmonic control, according to embodiments of the present invention, may be performed in a variety of ways.
In one embodiment, real power transfer onto the fundamental harmonic is maximized by means of wave-shaping of the PA stage input signals. In practice, several factors play a role in determining the optimal wave shape that results in a maximum real power transfer onto the fundamental harmonic. Embodiment 3400 of the present invention, described above, represents one embodiment that employs waveshaping of PA stage input signals. In embodiment 3400, a plurality of harmonic control circuitry (HCC) networks 3410-{1, . . . , n} are coupled at the PA stage input of each PA branch {1, . . . , n}. HCC networks 3410-{1, . . . , n} have the effect of waveshaping the PA stage inputs, and are typically selected so as to maximize real power transfer to the fundamental harmonic of the summed output spectrum. According to embodiments of the present invention, waveshaping can be used to generate variations of harmonically diverse waveforms. In other embodiments, as can be apparent to a person skilled in the art, waveshaping can be performed at the optional pre-driver and/or the driver stage.
In another embodiment, harmonic control is achieved by means of waveshaping of the PA stage output.
Harmonic control using staggered bias is depicted in process flowchart 4900 of the embodiment of
Step 4920 includes coupling a plurality of impedances between the first ports of the plurality of transistors and a bias signal. In the example embodiment of
According to embodiments of the present invention, a variety of multi-stage staggered bias approaches may be designed. Bias impedance values may be fixed or variable. Furthermore, bias impedance values may be equal or substantially equal, distinct, or set according to a variety of permutations. For example, referring to the example of
Vector power amplification embodiments of the present invention intrinsically provide a mechanism for performing output power control.
Phasors {right arrow over (U2)} and {right arrow over (L2)} represent upper and lower constituents of a second phasor {right arrow over (R2)}. {right arrow over (U2)} and {right arrow over (L2)} are constant magnitude and are symmetrically shifted in phase relative to {right arrow over (R2)} by a phase shift angle
It is noted, from
According to the above observation, output power control can be performed by imposing constraints on the phase shift angle of the constituent signals of a desired output signal. Referring to
can take, magnitude constraints can be imposed on phasor {right arrow over (R1)}.
According to embodiments of the present invention, a maximum output power level can be achieved by imposing a minimum phase shift angle condition. For example, referring to
the magnitude of phasor {right arrow over (R1)} is constrained not to exceed a certain maximum level. Similarly, a maximum phase shift angle condition imposes a minimum magnitude level requirement.
In another aspect of power control, output power resolution is defined in terms of a minimum power increment or decrement step size. According to an embodiment of the present invention, output power resolution may be implemented by defining a minimum phase shift angle step size. Accordingly, phase shift angle values are set according to a discrete value range having a pre-determined step size.
is set according to a pre-determined value range having a minimum step φstep.
A person skilled in the art will appreciate that a variety of power control schemes may be implemented in a fashion similar to the techniques described above. In other words, various power control algorithms can be designed, according to the present invention, by setting corresponding constraints on phase shift angle values. It is also apparent, based on the description above of data transfer functions, that power control schemes can be naturally incorporated into a transfer function implementation.
Referring to
Further illustrated in
Exemplary VPA implementations according to embodiments of the present invention will be provided in this section. Advantages of these VPA implementations will be appreciated by persons skilled in the art based on the teachings herein. We briefly describe below some of these advantages before presenting in more detail the exemplary VPA implementations.
The exemplary VPA implementations enable several layers of functionality for performing power control and/or for controlling power efficiency using circuitry within the VPA.
4.1.2) Error Compensation and/or Correction
The exemplary VPA implementations provide different approaches for monitoring and/or compensating for errors in the VPA. These errors may be due, among other factors, to process and/or temperature variations in the VPA, phase and amplitude errors in the vector modulation circuitry, gain and phase imbalances in branches of the VPA, and distortion in the MISO amplifier (see, for example, Section 3.4.5 above). In previously described VPA embodiments, part of this functionality was embodied in the process detector circuitry (e.g., process detector 792 in
In an embodiment, the receiver is integrated with the VPA, or is provided by an external calibration and/or testing device. Alternatively, the receiver is the receiver module in the device employing the VPA (e.g., the receiver in a cellular phone). In this alternative embodiment, the VPA error table and/or feedback information can be generated by this receiver module in the device.
The calculated Ierror and Qerror values are used to generate an error table or function representative of expected I and Q errors for various I and Q input values. In embodiments, the calculated Ierror and Qerror values are further interpolated to generate error values for an augmented range of I and Q input values, based on which the error table or function is generated.
In contrast to feedforward techniques, feedback techniques do not pre-compensate for errors but perform. real-time measurements inside or at the output of the VPA to detect any errors or deviations due to process or temperature variations, for example.
Hybrid feedforward/feedback techniques include both feedforward and feedback error pre-compensation and/or correction components. For example, a hybrid feedforward/feedback technique may pre-compensate for errors but may also use low rate periodical feedback mechanisms to supplement feedforward pre-compensation.
The exemplary VPA implementations provide several VPA architectures for concurrently supporting multiple frequency bands (e.g., quad band) and/or multiple technology modes (e.g., tri mode) for data transmission. Advantages of these VPA architectures will be appreciated by a person skilled in the art based on the teachings to be provided herein. In embodiments, the VPA architectures allow for using a single PA branch for supporting both TDD (Time Division Duplex) and FDD (Frequency Division Duplex) based standards. In other embodiments, the VPA architectures allow for the elimination of costly and power inefficient components at the output stage (e.g., isolators), typically required for FDD based standards. For the purpose of illustration and not limitation, frequency band allocation on lower and upper spectrum bands for various communication standards is provided in
As will be appreciated by persons skilled in the art based on the teachings herein, advantages enabled by the exemplary VPA implementations exist in various aspects in addition to those described above. In the following, a more detailed description of the exemplary VPA implementations will be provided. This includes a description of different implementations of the digital control circuitry of the VPA followed by a description of different implementations of the analog core of the VPA. Embodiments of the present invention are not limited to the specific implementations described herein. As will be understood by persons skilled in the art based on the teachings herein, several other VPA implementations may be obtained by combining features provided in the exemplary VPA implementations. Accordingly, the exemplary VPA implementations described below do not represent an exhaustive listing of VPA implementations according to embodiments of the present invention, and other implementations based on teachings contained herein are also within the scope of the present invention. For example, certain digital control circuitry could be integrated or combined with a baseband processor. In addition, certain analog control circuitry such as quadrature generators and vector modulators can be implemented using digital control circuitry. In an embodiment, the VPA system can be implemented in its entirety using digital circuitry and can be integrated completely with a baseband processor.
The digital control module of the VPA includes digital circuitry that is used, among other functions, for signal generation, performance monitoring, and VPA operation control. In Section 3, the signal generation functions of the digital control module (i.e., generating constant envelope signals) were described in detail with reference to the transfer function module (state machine) of the digital control module, in embodiments 700, 1200, and 1700, for example. The performance monitoring functions of the digital control module include functions for monitoring and correcting for errors in the operation of the VPA and/or functions for controlling the bias of different stages of the VPA. The VPA operation control functions of the digital control module include a variety of control functions related to the operation of the VPA (e.g., powering up or programming VPA modules). In certain embodiments, these control functions may be optional. In other embodiments, these control functions are accessible through the digital control module to external processors connected to the VPA. In other embodiments, these functions are integrated with baseband processors or other digital circuitry. Other functions are also performed by the digital control module in addition to those described above. Digital control module functions and implementations will now be provided in further detail.
According to an embodiment of the present invention, the digital control module can be implemented in any CMOS process, including, for example, 180, 130, 90, 65, 45, 32, 22, 16, and/or 11 nanometer CMOS technology.
Input interface 5602 provides a plurality of buses and/or ports for inputting signals into digital control module 5600. These buses and/or ports include, for example, buses and/or ports for inputting I and Q data signals, control signals provided by an external processor, and/or clock signals. In an embodiment, input interface 5602 includes an I/O bus. In another embodiment, input interface 5602 includes a data bus for receiving feedback signals from the analog core of the VPA. In another embodiment, input interface 5602 includes ports for reading values out of digital control module 5600. In an embodiment, values are read out of digital control module 5600 by an external processor (e.g., a baseband processor) connected to digital control module 5600.
Output interface 5604 provides a plurality of output buses and/or ports for outputting signals from digital control module 5600. These output buses and/or ports include, for example, buses and/or ports for outputting amplitude information signals (used to generate constant envelope signals), bias control signals (Autobias signals), voltage control signals (power supply signals), and output select signals.
State machine 5606 performs various functions related to the signal generation and/or performance monitoring functions of digital control module 5600. In an embodiment, state machine 5606 includes a transfer function module, as described in Section 3, for performing signal generation functions. In another embodiment, state machine 5606 includes modules for generating, among other types of signals, bias control signals, power control signals, gain control signals, and phase control signals. In another embodiment, state machine 5606 includes modules for performing error pre-compensation in a feedforward error correction system.
In an embodiment, state machine 5606 includes a vector synthesis engine (VSE). The VSE can be implemented using a fixed calculating engine and/or a Digital Signal Processor (DSP). In another embodiment, the VSE is implemented using a fixed calculating engine only, which based on I and Q data, for example, calculates appropriate control signals as described above (e.g., bias control signals, power control signals, etc.).
RAM 5608 and/or NVRAM 5610 are optional components of digital control module 5600. In embodiments, RAM 5608 and NVRAM 5610 reside externally of digital control module 5600 and may be accessible to digital control module 5600 through data buses connected to digital control module 5600 via input interface 5602, for example. RAM 5608 and/or NVRAM 5610 may or may not be needed depending on the specific VPA implementation. For example, a VPA implementation employing feedforward techniques for error pre-compensation may require RAM 5608 or NVRAM 5610 to store error tables or functions and/or calibration data. On the other hand, a feedback technique for error correction may solely rely on digital logic modules in the state machine and may not require RAM 5608 or NVRAM 5610 storage. Similarly, the amount of RAM 5608 and NVRAM 5610 storage may depend on the specific VPA implementation. Typically, when used, NVRAM 5610 is used for storing data that is not generated in real time (e.g., calibration data to compensate for temperature and/or process variations, for example) and/or that must be retained when power is turned off. This includes, for example, error tables and/or error values such as scalar values and angular values generated in the testing and characterization phase of the VPA system and/or look up tables used by transfer functions modules.
The input interface 5602 of exemplary digital control module 5700 includes an A/D IN bus 5702, a digital I/O bus 5704, and a plurality of control signals 5706-5730. In other digital control module implementations, the input interface 5602 may include more or less data buses, programming buses, and/or control signals.
A/D IN bus 5702 carries feedback information from the analog core of the VPA to the digital control module 5700. Feedback information can be used, among other functions, to monitor the output power of the VPA and/or for amplitude and/or phase variations in branches of the VPA. As illustrated in
Digital I/O bus 5704 carries data and control signals into and out of the digital control module 5700 from and to one or more processors or controllers that may be connected to the VPA. In an embodiment, some of control signals 5706-5730 are used to inform the digital control module 5700 of the type of information to expect on (or that is present on) digital I/O bus 5704. For example, PC/(I/Q)n signal 5724 indicates to the digital control module 5700 whether power control information or I/Q data is being sent over digital I/O bus 5704. Similarly, I/Qn signal 5720 indicates to the digital control module 5700 whether I or Q data is being sent over digital I/O bus 5704.
Other control signals of the input interface 5602 of the VPA digital control module 5700 include Digital Enable/Disablen 5706, PRGM/RUNn 5708, READ/WRITEn 5710, CLK OUT 5712, CLK_IN ×2 Enable/Disablen 5714, CLK_IN ×4 Enable/Disablen 5716, CLK_IN 5718, TX/RXn 5726, SYNTH PRGM/SYNTH RUNn 5728, and OUTPUT SEL/LATCHn 5730.
Digital Enable/Disablen signal 5706 controls the power-up, reset, and shut down of the VPA. Signals to power-up, reset, or shut down the VPA typically come from a processor connected to the VPA. For example, when used in a cellular phone, a baseband processor or controller of the cellular phone may shut down the VPA in receive mode and enable it in transmit mode.
PRGM/RUNn signal 5708 indicates to the digital control module 5700 whether it is in programming or in run mode. In programming mode, the digital control module 5700 can be programmed to enable the desired operation of the VPA. For example, memory (RAM 5608, NVRAM 5610) bits of the digital control module 5700 can be programmed to indicate the standard to be used (e.g., WCDMA, EDGE, GSM, etc.) for communication. Programming of digital control module 5700 is done using digital I/O bus 5704.
In an embodiment, the VPA is programmed and/or re-programmed (partially or completely) after it is installed in (or integrated with) the final product or device employing the VPA. For example, when used in a cellular phone, the VPA can be programmed, wirelessly, in a wired manner, or via the cellular phone keypad, after the cellular phone is manufactured to provide the cellular phone with new, additional, modified or different features, including but not limited to, features related to (1) supported waveforms, (2) power control, (3) enhanced efficiency; (4) characterization and calibration information; and/or (5) network control profiles. The VPA can also be programmed to remove waveforms or other features as desired by the network provider.
Programming of the VPA may be payment based. For example, the VPA may be programmed to include features and enhancements selected and purchased by the end-user.
In an embodiment, the VPA is programmed after the device is manufactured using any well known method or technique, including but not limited to: (1) programming the VPA using the programming interface of the device employing the VPA; (2) programming the VPA by storing programming data on a memory card readable by the device (a SIM card, for example, in the case of a cellular phone); and/or (3) programming the VPA by transferring programming data to the VPA wirelessly by the network provider or other source.
READ/WRITEn signal 5710 indicates to the digital control module 5700 whether data is to be read from or written to the digital control module storage (RAM 5608 or NVRAM 5610) via digital I/O bus 5704. When data is being read out of the digital control module 5700, CLK OUT signal 5712 indicates timing information for reading from digital I/O bus 5704.
CLK_IN signal 5718 provides a reference clock signal to the digital control module 5700. Typically, the reference clock signal is selected according to the communication standards supported by the VPA. For example, in a dual-mode WCDMA/GSM system, it is desirable that the reference clock signal be a multiple of the WCDMA chip rate (3.84 MHz) and the GSM channel raster (200 KHz), with 19.2 MHz being a popular rate as the least common multiple of both. Further, CLK_IN signal 5718 can be made a multiple of the reference clock signal. In an embodiment, CLK_IN ×2 Enable/Disablen 5714, CLK_IN ×4 Enable/Disablen 5716 can be used to indicate to the VPA digital control module 5700 that a multiple of the reference clock is being provided.
TX/RXn signal 5726 indicates to the digital control module 5700 when the system (e.g., cellular phone) employing the VPA is going into transmit or receive mode. In an embodiment, the digital control module 5700 is notified a short amount of time prior to the system going into transmit mode in order for it to power up the VPA. In another embodiment, the digital control module 5700 is notified when the system is going into receive mode in order for it to enter a sleep mode or to shutdown the VPA.
SYNTH PRGM/SYNTH RUNn signal 5728 is used to program the synthesizer that provides the reference frequency to the VPA (such as synthesizers 5918 and 5920 shown in
OUTPUT SEL/LATCHn signal 5730 is used to select the VPA output to be used for transmission. This may or may not be needed depending on the number of outputs of the VPA. When OUTPUT SEL 5730 goes high, the digital control module 5700 expects to receive data for selecting the output on digital I/O bus 5704. When LATCH 5730 goes high, the digital control module 5700 ensures that the VPA output used for transmission is held (cannot be changed) for the duration of the current transmit sequence.
The output interface 5604 of exemplary digital control module 5700 includes a plurality of data buses (5748, 5750, 5752, 5754, 5756, 5758, 5760, 5762, 5764, and 5766), a programming bus 5799, and a plurality of control signals (5768, 5770, 5772, 5744, 5776, 5778, 5780, 5782, 5784, 5786, 5788, 5790, 5792, 5794, 5796, and 5798). In other embodiments of digital control module 5700, the output interface 5604 may have more or less data buses, programming buses, and/or control signals.
Data buses 5752, 5754, 5756, and 5758 carry digital information from the digital control module 5700 that is used to generate the substantially constant envelope signals in the analog core of the VPA. Note that exemplary digital control module 5700 may be used in a 4-Branch VPA embodiment (see Section 3.1) or a 2-Branch VPA embodiment (see Section 3.3). For example, digital information carried by data buses 5752, 5754, 5756, and 5758 correspond to signals 722, 724, 726, and 728 in the embodiment of
Data buses 5760 and 5762 carry digital information from the digital control module 5700 that is used to generate bias voltage signals for the PA amplification stage and the driver amplification stage of the VPA (see
Data buses 5764 and 5766 carry digital information from the digital control module 5700 that is used to generate voltage control signals for the output stage and the driver stage of the VPA. Digital information carried by data bus 5764 is converted from digital to analog using DAC—07 to generate output stage voltage control signal 5765. Similarly, digital information carried by data bus 5766 is converted from digital to analog using DAC—08 to generate driver stage voltage control signal 5767. Output stage voltage control signal 5765 and driver stage voltage control 5767 are used to generate supply voltages for the output stage and the driver stage, providing a further method for controlling the voltage of the output stage and driver stage of the VPA. In an embodiment, DACs 07 and 08 are controlled and synchronized using a Voltage Control DAC CLK signal 5774, and are provided, in an embodiment, the same central reference voltage VREF_F signal 5747.
Data buses 5748 and 5750 carry digital information from the digital control module 5700 that is used to generate gain and phase balance control signals. In an embodiment, the gain and phase balance control signals are generated in response to feedback gain and phase information received from the analog core of the VPA on A/D IN bus 5702. Digital information carried by data bus 5748 is converted from digital to analog using DAC—09 to generate analog gain balance control signal 5749. Similarly, digital information carried by data bus 5750 is converted from digital to analog using DAC—10 to generate analog phase balance control 5751. Gain and phase balance control signals 5749 and 5751 provide one mechanism for regulating gain and phase in the analog core of the VPA. In an embodiment, DACs 09 and 10 are controlled and synchronized using a Balance DAC CLK signal 5768, and are provided the same central reference voltage VREF_B 5739.
Programming bus 5799 carries digital instructions from the digital control module 5700 that are used to program frequency synthesizer or synthesizers in the analog core of the VPA. In an embodiment, digital instructions carried by programming bus 5799 are generated according to data received on digital I/O bus 5704, when SYNTH PRGM signal 5728 is high. Digital instructions for programming the frequency synthesizers include instructions for setting the appropriate synthesizer (HI Band or Low Band) to generate a frequency according to the selected communication standard. In an embodiment, programming bus 5799 is a 3-wire programming bus. In an embodiment, programming bus 5799 is an SPI bus.
In addition to the data and programming buses described above, the output interface 5604 includes a plurality of control signals.
In conjunction with programming bus 5799, used for programming the frequency synthesizers of the analog VPA core, HI Band Enable/Disablen and Low Band Enable/Disablen control signals 5796 and 5798 are generated to control which of a high band frequency synthesizer and a low band frequency synthesizer of the analog VPA core is enabled/disabled.
Control signals 5738, 5740, 5742, 5744, and 5746 control an input selector for multiplexing feedback signals from the analog core of the VPA onto A/D N input signal 5736 of A/D converter 5732. In an embodiment, control signals 5738, 5740, 5744, and 5746 control the multiplexing of a power output feedback signal, a differential branch amplitude feedback signal, and a differential branch phase feedback signal on A/D IN signal 5736. Other feedback signals may be available in other embodiments. In an embodiment, the feedback signals are multiplexed according to a pre-determined multiplexing cycle. In another embodiment, certain feedback signals are periodically carried by A/D N signal 5736, while others are requested on-demand by the digital control module.
Output select control signals 5776, 5778, 5780, 5782, and 5784 are generated by the digital control module 5700 in order to select a VPA output, when the particular VPA implementation supports a plurality of outputs for different frequency bands and/or technology modes. In an embodiment, output select control signals 5776, 5778, 5780, 5782, and 5782 are generated according to digital control module input signal 5730. In the example implementation of
Vector MOD HI Band(s)/Vector MOD Low Band(s)n control signal 5786 is generated by the digital control module 5700 to indicate whether a high band frequency modulation set or a low band frequency modulation set of vector modulators is to be used in the analog core of the VPA. In an embodiment, the high band and the low band vector modulators have different characteristics, allowing each set to be more suitable for a range of modulation frequencies. Control signal 5786 is generated according to the selected output of the VPA. In an embodiment, control signal 5786 controls circuitry within the analog core of the VPA in order to ensure that the selected set of vector modulators is powered up and that the other set(s) of vector modulators are powered off. In another embodiment, control signal 5786 controls circuitry within the analog core of the VPA in order to couple a set of interpolation filters to the selected set of vector modulators.
3G HI Band/Normaln control signal 5788 is an optional control signal which may be used, if necessary, to enable the VPA to support the wide range High frequency band. In an embodiment, control signal 5788 may force more current through the output stage circuitry of the analog core and/or modify the output impedance characteristics of the VPA.
Filter Response 1/Filter Response 2n control signal 5790 is an optional control signal which may be used to dynamically change the response of interpolation filters in the VPA system. This may be needed as the interpolation filters have different optimal responses for different communication standards. For example, the optimal filter response has a 3 dB corner frequency around 5 MHz for WCDMA or EDGE, while this frequency is around 400 KHz for GSM. Accordingly, control signal 5790 allows for optimizing the interpolation filters according to the used communication standard. In another embodiment, control signal 5790 is used to dynamically change the response of the interpolation filters based on output power requirements and/or variable VSE clock rates.
Attenuator control signals 5792 and 5794 are optional control signals which may be used, if necessary, to provide additional output power control features and functions. For example, attenuator control signals 5792 and 5794 could be configured to enable/disable RF attenuators on the output of the VPA. These attenuators may be required based on the specific VPA implementation, which could be fabricated using Silicon, GaAs, or CMOS processes.
Exemplary implementation 5800 includes different input select control signals 5808, 5810, and 5812 compared to exemplary implementation 5700. Input select control signals 5810 and 5812 control whether feedback information is to be received from the high band or the low band analog circuitry of the VPA, depending on which band is in use. Input select control signal I/Qn 5808 controls the multiplexing of I and Q feedback data from the analog core of the VPA. In an embodiment, control signal 5812 allows sequential switching between I data and Q data on A/D IN signal 5736.
In further distinction to exemplary embodiment 5700, exemplary embodiment 5800 include an additional data bus 5802, which carries digital information from the digital control module 5800 used to generate an automatic gain control signal 5806. Automatic gain control signal 5806 is used to control the gain of an amplifier circuit used in the feedback mechanism in the analog core of the VPA. Further description of this component of the feedback mechanism will be provided below. In an embodiment, digital information carried by data bus 5802 is converted from digital to analog by DAC—11 to generate analog signal 5806. DAC—11 is controlled by a clock signal 5804 provided by the digital control module, and is provided VREF_B signal 5739 as a central reference voltage.
In particular, the output interface of digital control module 7900 includes similar data buses as data buses 5748, 5750, 5752, 5752, 5754, 5756, 5758, 5760, 5764, and 5766 of digital control module embodiment 5700, with the only potential difference being in the bit widths associated with the data buses (embodiment 7900 provides a general configuration of the data bus widths).
The output interface of digital control module 7900 further includes a data bus similar to data bus 5802 of digital control module embodiment 5800. As described above, data bus 5802 can be used to forward automatic gain control information. The automatic gain control information is used to enable a receiver-based feedback mechanism in the analog core of the VPA, as will be further described below in Section 4.3.3.
Further, the output interface of digital control module 7900 includes similar control signals as control signals 5738, 5740, 5742, 5744, and 5746 of embodiment 5700. As described above, control signals 5738, 5740, 5742, 5744, and 5746 can be used to multiplex back to the digital control module feedback information from the analog core of the VPA, including feedback information regarding the power output, the differential branch phase, and the differential branch amplitude, to enable a differential feedback mechanism.
Accordingly, digital control module embodiment 7900 can be used with an analog core implementing a receiver-based feedback approach, a differential feedback approach, or both.
In a variation from embodiments 5700 and 5800, digital control module 7900 includes a plurality of frequency control signals 7902, instead of output select signals 5776, 5778, 5780, 5782, and 5784. Frequency control signals 7902 allow digital control module 7900 to specify up to 16 different output frequency values. Depending on which output frequency value is selected by control signals 7902, appropriate circuitry within the analog core of the VPA is activated. For example, this includes activating an appropriate path (including interpolation filters, vector modulators, PAs, etc.) and/or output of the VPA and associated power and control circuitry based on the selected output frequency value.
In a further variation from embodiments 5700 and 5800, digital control module 7900 outputs control signals 7904 and 7906, which are used to enable/disable frequency divider circuits 7910 and 7912, respectively. In an embodiment, frequency divider circuits 7910 and 7912 are part of the analog core of the VPA. In an embodiment, frequency divider circuits 7910 and 7912 allow local oscillator (LO) signal 7908 to be passed through unchanged, divided by 2, or divided by 4, to generate LO signal 7914. LO signal 7914 is provided to a synthesizer (e.g., synthesizer 5918 or 5920 in
Digital control module 7900 further outputs a gain control signal, which is converted to analog by DAC 11 to generate gain control signal 7916. Gain control signal 7916 can be used to control the gain levels of the branches of the active VPA. In an embodiment, this is done by controlling one or more automatic gain controllers (AGCs) located in the VPA branches. This is illustrated in exemplary embodiment 8700 in
In operation, the phase shifter circuitry associated with the upper and the lower branches of the VPA operate identically. Particularly, for example, phase shifter compare and control circuitry 8102 receives a desired upper branch phase signal from the digital control module via DAC—01. Phase shifter compare and control circuitry further receives a feedback signal from phase detector 8112 via buffer amplifier 8116. Phase detector 8112 measures the phase of the upper branch signal at the output of upper branch phase shifter circuitry 8106. Phase shifter compare and control circuitry 8102 compares the desired phase signal and the feedback signal to determine whether the output phase signal is equal to the desired phase signal. If equal, phase shifter compare and control circuitry 8102 instructs phase shifter 8106 to hold or lock onto the current phase value. Alternatively, phase shifter compare and control circuitry 8102 may instruct phase shifter 8106 to either advance, retard, or invert the output phase signal in order to reach the desired upper branch phase.
It is noted that exemplary digital control modules 5700, 5800, 7900, 8000, and 8100 illustrate some of the typical input and output digital control module signals that may be used in a digital control module implementation. More or less input and output signals may also be used, as will be appreciated by a person skilled in the art based on the teachings herein, depending on the system in which the VPA is being used and/or the specific VPA analog core to be used with the digital control module. In an embodiment, exemplary digital control module implementations 5700, 5800, 7900, 8000, and 8100 may be used in conjunction with a VPA analog core using feedback only, feedforward only, or both feedback and feedforward error correction. When used in a feedforward only approach, feedback elements and/or signals (e.g., A/D IN 5702, control signals 5738, 5740, 5742, 5744, 5746, gain and phase balance control signals 5749 and 5751) may be disabled or eliminated. Accordingly, variations of exemplary digital control module implementations 5700, 5800, 7900, 8000, and 8100 are within the scope of embodiments of the present invention.
In this section, various exemplary implementations of the VPA analog core will be provided. As will be described below, the various exemplary implementations share a large number of components, circuits, and/or signals, with the main differences relating to the output stage architecture, the adopted error correction feedback mechanism, and/or the actual semiconductor material used in chip fabrication. As will be understood by a person skilled in the art based on the teachings herein, other VPA analog core implementations are also conceivable by interchanging, adding, and/or removing features among the various exemplary implementations described below. Accordingly, embodiments of the present invention are not to be limited to the exemplary implementations described herein.
Analog core implementation 5900 is a 2-Branch VPA embodiment. This implementation 5900, however, can be readily modified to a 4-Branch or a CPCP VPA embodiment, as will be apparent to persons skilled in the art based on the teachings herein.
At a high level, analog core 5900 includes an input stage for receiving data signals from the digital control module 5700, a vector modulation stage for generating substantially constant envelope signals, and an amplification output stage for amplifying and outputting the desired VPA output signal. Additionally, analog core 5900 includes power supply circuitry for controlling and delivering power to the different stages of the analog core, optional output stage protection circuitry, and optional circuitry for generating and providing feedback information to the digital control module of the VPA.
The input stage of VPA analog core 5900 includes an optional interpolation filter bank (5910, 5912, 5914, and 5916) and a plurality of switches 5964, 5966, 5968, and 5970. Interpolation filters 5910, 5912, 5914, and 5916, which may also serve as anti-aliasing filters, shape the analog outputs 5753, 5755, 5757, and 5759 of DACs 01-04 to generate the desired output waveform. In an embodiment, the response of interpolation filters 5910, 5912, 5914, and 5916 is dynamically changed using control signal 5790 from the digital control module 5700. Digital control module signal 5790 may, for example, control switches within interpolation filters 5910, 5912, 5914, and 5916 to cause a change in active circuitry (enable/disable RC circuitry) within filters 5910, 5912, 5914, and 5916. This may be needed as interpolation filters 5910, 5912, 5914, and 5916 have different optimal responses for different communication standards and/or output power levels. It should be noted that interpolation filters 5910, 5912, 5914, and 5916 can be implemented using digital circuitry such as FIR filters or programmable FIR filters. When implemented digitally, these filters can be included within the VPA system or integrated with a baseband processor.
Subsequently, the outputs of interpolation filters 5910, 5912, 5914, and 5916 are switched using switches 5964, 5966, 5968, and 5970 to connect to either an upper band path 5964 or a lower band path 5966 of the VPA analog core 5900. This determination between the upper and lower band paths is usually made by the digital control module 5700 based on the selected frequency range for transmission by the VPA. For example, the lower band path 5966 is used for GSM-900, while the upper band path 5964 is used for WCDMA. In an embodiment, switches 5964, 5966, 5968, and 5970 are controlled by Vector MOD HI Band(s)/Vector MOD Low Band(s)n signal 5786, provided by the digital control module 5700. Signal 5786 controls the coupling of each of switches 5964, 5966, 5968, and 5970 to respective first or second inputs, thereby controlling the coupling of the outputs of interpolation filters 5910, 5912, 5914, and 5916 to the either the upper path 5964 or lower path 5966 of the VPA analog core 5900.
The vector modulation stage of VPA analog core 5900 includes a plurality of vector modulators 5922, 5924, 5926, and 5928, divided between the upper band path 5964 and the lower band path 5966 of the analog core 5900. Based on the selected band of operation, either the upper band path vector modulators (5922, 5924) or the lower band path vector modulators (5926, 5928) are active.
In an embodiment, the operation of vector modulators 5922, 5924 or 5926, 5928 is similar to the operation of vector modulators 1750 and 1752 in the embodiment of
Vector modulators 5922 and 5924 (or 5926 and 5928) modulate input signals 5919, 5921, 5923, and 5925 (5927, 5929, 5931, and 5933) with HI BAND RF_CLK signal 5935 (LOW BAND RF_CLK signal 5937). In an embodiment, vector modulators 5922 and 5924 (or 5926 and 5928) modulate the input signals with appropriately derived and/or phase shifted versions of HI BAND RF_CLK signal 5935 (LOW BAND RF_CLK signal 5937), and combine the generated modulated signals to generate substantially constant envelope signals 5939 and 5941 (5943 and 5945).
In another embodiment, vector modulators 5922 and 5924 (or 5926 and 5928) further receive a phase balance control signal 5751 from the VPA digital control module. Phase balance control signal 5751 controls vector modulators 5922 and 5924 (or 5926 and 5928) to cause a change in phase in constant envelope signals 5939 and 5941 (or 5943 and 5945), in response to phase feedback information from the analog core. The amplitude and phase feedback mechanism is further discussed below. Optionally, upper band path vector modulators 5922 and 5924 also receive a 3G HI Band/Normaln signal 5788 from the digital control module. Signal 5788 can be used, if necessary, to further support driving the vector modulators at the highest frequencies of the upper band.
The output stage of VPA analog core 5900 includes a plurality of MISO amplifiers 5930 and 5932, divided between the upper band path 5964 and the lower band path 5966 of the analog core 5900. Based on the selected band of operation, either the upper band path MISO amplifier 5930 or the lower band path MISO amplifier 5932 is active.
In an embodiment, MISO amplifier 5930 (or 5932) receives substantially constant envelope signals 5939 and 5941 (or 5943 and 5945) from vector modulators 5922 and 5924 (or 5926 and 5928). MISO amplifier 5930 (or 5932) individually amplifies signals 5939 and 5941 (or 5943 and 5945) to generate amplified signals, and combines the amplified signals to generate output signal 5947 (or 5949). In an embodiment, MISO amplifier 5930 (or 5932) combines the amplified signals via direct coupling, as described herein. Other modes of combining the amplified signals according to embodiments of the present invention have been described above in Section 3.
The output stage of VPA analog core 5900 is capable of supporting multi-band multi-mode VPA operation. As shown in
In analog core 5900, the output 5947 of MISO amplifier 5930 can be coupled to one of three output paths 5954, 5956, and 5958, with each output path 5954, 5956, 5958 being the one that is coupled to an antenna (not shown) or connector (not shown) for a particular mode of transmission. Similarly, the output 5949 of MISO amplifier 5932 can be coupled to one of two output paths 5960 and 5962. In an embodiment, output select signals 5776, 5778, 5780, 5782, and 5784, provided by the digital control module, control switches 5942 and 5944 to couple the output of the active MISO amplifier to the appropriate output path, based on the selected transmission mode. It is noted that more or less output paths 5954, 5956, 5958, 5960, and 5962 may be used.
Accordingly, with only two MISO amplifiers 5930 and 5932, analog core 5900 supports multiple different transmission modes. In an embodiment, analog core 5900 allows for using a single MISO amplifier to support GSM, EDGE, WCDMA, and CDMA2000. It is clear therefore that one of the advantages of this exemplary VPA analog core according to implementation 5900 is in the reduction in the number of PAs per supported output paths This directly corresponds to a reduction in required chip area for the VPA analog core 5900.
In an embodiment, the output stage of analog core 5900 receives optional output stage autobias signal 5761, driver stage autobias signal 5763, and gain balance control signal 5749 from the digital control module. Output stage autobias signal 5761 and driver stage autobias signal 5763 may or may not be needed according to the particular type of transistors used in the actual MISO implementation. In an embodiment, output stage autobias signal 5761 and driver stage autobias signal 5763 control the bias of MISO amplification stages to cause a change in the power output and/or the power efficiency of the VPA. Similarly, gain balance control signal 5749 may cause a change in the gain levels of different MISO amplification stages, in response to power output feedback information received by the digital control module from the analog core. Further discussion of these optional output stage input signals will be provided below.
In an embodiment, the output stage of analog core 5900 provides optional feedback signals to the digital control module 5700 of the VPA. Typically, these feedback signals are used by the digital control module 5700 to correct for amplitude and phase variations in branches of the VPA and/or for controlling the output power of the VPA. In the specific implementation of analog core 5900, a differential feedback approach is employed to monitor for amplitude and phase variations, using a differential branch amplitude signal 5950 and a differential branch phase signal 5948 provided by the output stage. Further, output power monitoring is provided using signals PWR Detect A 5938 and PWR Detect B 5940, which measure the output power of MISO amplifiers 5930 and 5932, respectively. Since only one of MISO amplifiers 5930 and 5932 can be active at any time, in an embodiment, PWR Detect A 5938 and PWR Detect 5940 are summed together using summer 5942, to generate a signal that corresponds to the output power of the VPA.
In an embodiment, the feedback signals from the output stage are multiplexed using an input selector 5946 controlled by the digital control module 5700. In another embodiment, the digital control module 5700 uses A/D Input Selector signals 5738, 5740, 5742, 5744, and 5746 to control input selector 5946 and select the feedback signal to be received. It is noted that monitoring of feedback signals may not need to occur in real-time rate and may only need to be performed periodically at a low rate. For example, for the purpose of branch amplitude and phase error correction, the rate at which feedback monitoring is performed depends on several factors such as the degree of feedforward correction being performed in the digital control module, process variations due to temperature, or operation changes such as changing battery or supply voltages.
Above, the tradeoffs between feedforward and feedback error compensation and/or correction techniques have been described. Accordingly, parameters governing the rates at which feedback monitoring is performed are design choices typically selected by the actual designer of the VPA. As a result, analog core implementation 5900 can be programmed to operate as a pure feedback implementation by disabling any feedforward correction in the digital control module, a pure feedforward implementation by disabling the monitoring of feedback signals, or as a hybrid feedforward/feedback implementation with variable feedforward/feedback utilization.
In an embodiment, the output stage of analog core 5900 includes optional output stage protection circuitry. In
As described above, analog core 5900 includes power supply circuitry for controlling and delivering power to the different stages of the analog core 5900. In one aspect, the power supply circuitry provides means for powering up active portions of the VPA analog core 5900. In another aspect, the power supply circuitry provides means for controlling the power efficiency and/or the output power of the VPA.
In analog core implementation 5900, the power supply circuitry includes MA Power Supply 5902, Driver Stage Power Supply 5904, Output Stage Power Supply 5906, and Vector Mods Power Supply 5908. In an embodiment, the power supply circuitry is controlled by output select signals 5776, 5778, 5780, 5782, and 5784, provided by the digital control module 5700. Optionally, one or more of these power supply circuitry (i.e., MA Power Supply 5902, Driver Stage Power Supply 5904, Output Stage Power Supply 5906, and Vector Mods Power Supply 5908) can be controlled by a digital control bus such as an SPI bus. This eliminates the DACs that correspond to said one or more power supply circuitry, which couple said power supply circuitry to digital control module 5700.
MA Power Supply 5902 includes circuitry for controlling the powering up of active portions of the VPA analog core 5900. In analog core 5900, MA Power Supply 5902 has two outputs MA1 VSUPPLY 5903 and MA2 VSUPPLY 5905. At any time, only one of MA1 VSUPPLY 5903 or MA2 VSUPPLY 5905 is active, ensuring that only the upper band 5964 or the lower band 5966 portion of the VPA analog core 5900 is powered up. In an embodiment, the active output of MA Power Supply 5902 is coupled to all active circuitry of the VPA analog core 5900, with the exception of circuitry having unique power supply signals as described below. MA Power Supply 5902 receives output select signals from the digital control module, which enable one or the other of output signals MA1 VSUPPLY 5903 or MA2 VSUPPLY 5905, based on the selected output of the VPA.
Driver Stage Power Supply 5904 includes circuitry for providing power to the driver stage circuitry of the MISO amplifiers 5930, 5932. Similar to MA Power Supply 5902, Driver Stage Power Supply 5904 has two outputs MA1 Driver VSUPPLY 5907 and MA2 Driver VSUPPLY 5909, with only one of the two outputs being active at any time. Driver Stage Power Supply 5904 is also controlled by output select signals 5776, 5778, 5780, 5782, and 5784 according to the selected output of the VPA. In addition, Driver Stage Power Supply 5904 receives a Driver Stage Voltage Control signal 5767 from the digital control module 5700. In an embodiment, the outputs MA1 Driver VSUPPLY 5907 and MA2 Driver VSUPPLY 5909 are generated according to the received Driver Stage Voltage Control signal 5767. In another embodiment, Driver Stage Voltage Control signal 5767 causes Driver Stage Power Supply 5904 to increase or decrease MA1 Driver VSUPPLY 5907 or MA2 Driver VSUPPLY 5909 to control the driver stage power amplification level. In another embodiment, Driver Stage Voltage Control signal 5767 is used by the digital control module 5700 to affect a change, using Driver Stage Power Supply 5904, in the power supply voltage of the driver stage of the active MISO amplifier 5930 or 5932, thereby controlling the power efficiency of the VPA.
Output Stage Power Supply 5906 includes circuitry for providing power to the PA stage circuitry of the MISO amplifiers 5930, 5932. Similar to MA Power Supply 5902, Output Stage Power Supply 5906 has two outputs MA1 Output Stage VSUPPLY 5911 and MA2 Output Stage VSUPPLY 5913, with only one of the two outputs being active at any time. Output Stage Power Supply 5906 is also controlled by output select signals 5776, 5778, 5780, 5782, and 5784 according to the selected output of the VPA. In addition, Output Stage Power Supply 5906 receives an Output Stage Voltage Control signal 5765 from the digital control module 5700. In an embodiment, the outputs MA1 Output Stage VSUPPLY 5911 and MA2 Output Stage VSUPPLY 5913 are generated according to the received Output Stage Voltage Control signal 5765. In another embodiment, Output Stage Voltage Control signal 5765 causes Output Stage Power Supply 5906 to increase or decrease MA1 Output Stage VSUPPLY 5911 or MA2 Output Stage VSUPPLY 5913 to control the PA stage power amplification level. In another embodiment, Output Stage Voltage Control signal 5765 is used by the digital control module 5700 to affect a change, using Output Stage Power Supply 5906, in the power supply voltage of the PA stage of the active MISO amplifier 5930 or 5932, thereby controlling the power efficiency of the VPA.
Vector Mods Power Supply 5908 includes circuitry for providing power to the vector modulators 5922, 5924, 5926, and 5928 of the analog core 5900. In analog core 5900, Vector Mods Power Supply 5908 has two outputs 5915 and 5917 for powering up the upper band vector modulators 5922 and 5924 and the lower band vector modulators 5926 and 5928, respectively. At any time, only one of outputs 5915 or 5917 is active, ensuring that only the upper band or the lower vector modulators of the analog core 5900 are powered up. Vector Mods Power Supply 5908 receives a vector mod select signal 5786 from the digital control module 5700, which controls which of its two outputs 5915 and 5917 is active, according to the selected transmission frequency requirements.
In addition to the above described power supply circuitry, analog core 5900 may optionally include voltage reference generator circuitry. The voltage reference generator circuitry may reside externally or within the VPA analog core 5900. The voltage reference generator circuitry generates reference voltages for different circuits within the VPA. In an embodiment, as illustrated in
In an embodiment, MISO amplifier stage 6058 corresponds to MISO amplifier 5930 in analog core 5900. Accordingly, MA VSUPPLY signal 6006, MA Driver VSUPPLY signal 6004, and MA Output Stage VSUPPLY signal 6002 correspond respectively to signals 5903, 5907, and 5911 in
MISO amplifier stage 6058 in embodiment 6000 includes an optional pre-driver amplification stage, embodied by Pre-Drivers 6012 and 6014, a driver amplification stage, embodied by Drivers 6018 and 6020, and a PA amplification stage, embodied by output stage PAs 6030 and 6032. In an embodiment, substantially constant envelope input signals MA IN1 6008 and MA IN2 6010 are amplified at each stage of MISO amplifier 6058, before being summed at the outputs of the PA stage.
In an embodiment, MISO amplifier stage 6058 is powered by power supply signals provided by voltage controlled power supply circuits. As described with reference to
In an embodiment, MISO amplifier stage 6058 includes bias control circuitry. The bias control circuitry may be optional according to the particular MISO amplifier implementation. In an embodiment, the bias control circuitry provides a mechanism for controlling efficiency and/or power at each amplification stage of MISO amplifier 6058. This mechanism is independent of the mechanism described above with reference to the power supply signals. Further, this mechanism provides for independently and individually controlling each amplification stage. In
In an embodiment, Gain Balance Control Circuitry 6016 is coupled to the inputs of either the pre-driver amplification stage or the driver amplification stage as illustrated in
In an embodiment, the digital control module 5700 independently controls the bias of the optional pre-driver stage, the driver stage, and the PA stage of MISO amplifier 6058 using Gain Balance Control signal 5749, Driver Stage Autobias signal 5763, and Output Stage Autobias signal 5761, respectively. In another embodiment, the digital control module 5700 may affect a change in the bias of the optional pre-driver stage, the driver stage, and/or the PA stage of MISO amplifier 6058 only using Gain Balance Control signal 5749. As illustrated in
In an embodiment, MISO amplifier stage 6058 includes circuits for enabling an error correction and/or compensation feedback mechanism. In output stage embodiment 6000, a differential feedback mechanism is adopted, whereby Differential Branch Amplitude Measurement Circuitry 6024 and Differential Branch Phase Measurement Circuitry 6026 respectively measure differences in amplitude and phase between branches of MISO amplifier 6058. In an embodiment, Differential Branch Amplitude Measurement Circuitry 6024 and Differential Branch Phase Measurement Circuitry 6026 are coupled at the inputs of the PA stage (PAs 6030 and 6032) of MISO amplifier 6058. In other embodiments, circuitry 6024 and 6026 may be coupled at the inputs of prior stages of MISO amplifier 6058. In an embodiment, Differential Branch Amplitude Measurement Circuitry 6024 and Differential Branch Phase Measurement Circuitry 6026 respectively output Differential Branch Amplitude signal 5950 and Differential Branch Phase signal 5948, which are fed back to digital control module 5700 (through A/D converters). Since digital control module 5700 knows at any particular time the correct differences in amplitude and/or phase between the branches of MISO amplifier 6058, it may determine any errors in amplitude and/or phase based on Differential Branch Amplitude signal 5950 and Differential Branch Phase signal 5948.
Output stage embodiment 6000 includes optional output stage protection circuitry. The output stage protection circuitry may or may not be needed according to the particular MISO amplifier implementation. In
Output stage embodiment 6000 includes optional power detection circuitry. In an embodiment, the power detection circuitry serves as a means for providing power level feedback to the digital control module. In
The optional output switching stage of output stage embodiment 6000 is embodied by a switch 6044 in
Accordingly, pull-up impedance coupling at the output of the VPA can be done in various ways. In an embodiment, as shown in
According to the particular MISO amplifier implementation, output stage embodiment 6000 may include more or less circuitry than to what is illustrated in
According to embodiments of the present invention, output stage embodiment 6000 including MISO amplifier stage 6058, the optional output switching stage (switch 6044), and the optional output protection and power detection circuitry may be fabricated using a SiGe (Silicon-Germanium) material. In another embodiment, MISO amplifier stage 6058 is fabricated using SiGe, and the output switching stage is fabricated using GaAs. In another embodiment, the PA stage (PAs 6030 and 6032) and the output switching stage are fabricated using GaAs, while other circuitry of MISO amplifier stage 6058 and optional circuitry of the output stage are fabricated using SiGe. In another embodiment, the PA stage, the driver stage, and the output switching stage are fabricated using GaAs, while other circuitry of MISO amplifier stage 6058 and optional circuitry of the output stage are fabricated using SiGe. In another embodiment, the PA stage, the driver stage, the optional pre-driver stage, and the output switching stage are fabricated using GaAs. In another embodiment, the VPA system may be implemented using CMOS for all circuitry except for the output stage (6030 or 6032) which could be implemented in SiGe or GaAs material. In another embodiment, the VPA system may be implemented in its entirety in CMOS. Other variations and/or combinations of fabrication material(s) used for circuitry of the output stage are also possible, as can be understood by a person skilled in the art, and are therefore also within the scope of embodiments of the present invention.
Accordingly, as different semiconductor materials have different costs and performance, embodiments of the present invention provide a variety of VPA designs encompassing a wide range of cost and performance options.
Analog core implementation 6100 is corresponds to a 2-Branch VPA embodiment. This implementation, however, can be readily modified to a 4-Branch or a CPCP VPA embodiment, as will be apparent to persons skilled in the art based on the teachings herein.
Analog core implementation 6100 has the same input stage and vector modulation stage as analog core implementation 5900, described above. Accordingly, similar to analog core implementation 5900, analog core 6100 includes an upper band path 5964 and a lower band path 5966 for upper band and lower band operation of the VPA, respectively.
One of the differences between analog core 5900 and analog core 6100 lies in the output stage of the VPA. In contrast to the output stage of analog core 5900, which includes two MISO amplifiers 5930 and 5932, the output stage of analog core 6100 includes five MISO amplifiers 6126, 6128, 6130, 6132, and 6134, divided between the upper band path 5964 and the lower band path 5966 of the analog core. In an embodiment, the output stage includes a combination of SiGe and GaAs MISO amplifiers. In an embodiment, the upper band path 5964 includes three MISO amplifiers 6126, 6128, and 6130, and the lower band path 5966 includes two MISO amplifiers 6132 and 6134. Based on the selected band of operation, a single MISO amplifier, either in the upper band path 5964 or the lower band path 5966, is active. In an embodiment, each of MISO amplifiers 6126, 6128, 6130, 6132, and 6134 can be dedicated to a single transmission mode (e.g., WCDMA, GSM, EDGE, etc.) of the VPA. This is in contrast to analog core 5900, where each of MISO amplifiers 5930 and 5932 supports more than one transmission modes. Advantages and disadvantages of each architecture will be further discussed below.
As a result of having more than one MISO amplifiers per path, a switching stage is needed to couple the vector modulation stage to the MISO amplifiers in analog core 6100. In
In an embodiment, MISO amplifier 6126 (or 6128, 6130, 6132, 6134) receives constant envelope signals 6119 and 6121 (or 6123 and 6125, 6127 and 6129, 6131 and 6133, 6135 and 61137). MISO amplifier 6126 (or 6128, 6130, 6132, 6134) individually amplifies signals 6119 and 6121 (or 6123 and 6125, 6127 and 6129, 6131 and 6133, 6135 and 6137) to generate amplified signals, and combines the amplified signals to generate output signal 6141 (6144, 6146, 6148, 6150). In an embodiment, MISO amplifier 6126 (or 6128, 6130, 6132, 6134) combines the amplified signals via direct coupling, as described herein. Other modes of combining the amplified signals according to embodiments of the present invention have been described above in Section 3.
The output stage of VPA analog core 6100 is capable of supporting multi-band multi-mode VPA operation. Further, since the output stage of analog core 6100 can dedicate one MISO amplifier for each supported transmission mode, the output switching stage (embodied in analog core 5900 by switches 5942 and 5944) can be eliminated. This results in a more efficient output stage (no power loss due switching stage), but at the expense of a larger chip area. This summarizes the main tradeoff between the architecture of analog core 5900 and that of analog core 6100.
In an embodiment, the output stage of analog core 6100 receives optional bias control signals from digital control module 5700. These are output stage autobias signal 5761, driver stage autobias signal 5763, and gain balance control signal 5749, which have been described above with reference to analog core 5900.
In an embodiment, the output stage of analog core 6100 provides optional feedback signals to digital control module 5700 of the VPA. These feedback signals include Differential Branch Amplitude signal 5950 and Differential Branch Phase signal 5948, described above with reference to analog core 5900, to enable a differential feedback approach to monitor for amplitude and phase variations in branches of the VPA. Also, similar to analog core 5900, output power monitoring is provided using PWR Detect signals 6152, 6154, 6156, 6158, and 6160, each of which measuring one of outputs 6142, 6144, 6146, 6148, and 6150 of the VPA. Since only one of the VPA outputs can be active at any time, PWR Detect signals 6152, 6154, 6156, 6158, and 6160 are summed together, in an embodiment, using summer 5952, to generate a signal that corresponds to the current output power of the VPA.
Similar to analog core 5900, the feedback signals from the output stage are multiplexed using an input selector 5946 controlled by the digital control module. Other aspects of the multiplexing of the feedback signals are described above with reference to analog core 5900.
Similar to analog core 5900, analog core 6100 can be designed to operate as a pure feedback implementation by disabling any feedforward correction in the digital control module, a pure feedforward implementation by disabling the monitoring of feedback signals, or as a hybrid feedforward/feedback implementation with variable feedforward/feedback utilization.
In an embodiment, the output stage of analog core 6100 includes optional output stage protection circuitry. In
Analog core 6100 includes power supply circuitry for controlling and delivering power to the different stages of the analog core. In one aspect, the power supply circuitry provides means for powering up active portions of the VPA analog core. In another aspect, the power supply circuitry provides means for controlling the power efficiency and/or the output power of the VPA.
The power supply circuitry of analog core 6100 is substantially similar to the power supply circuitry of analog core 5900, with the difference being that analog core 6100 includes five MISO amplifiers as opposed to two in analog core 5900. In
It is noted that in analog core implementation 8200, the vector modulation stage or phase circuitry outputs (i.e., signals RF OUT1 and RF OUT 2) are coupled directly to the inputs of the MISO amplifiers (i.e., MA1, . . . , MA5), without any switching circuitry therebetween. This is done by ensuring that only one of MISO amplifiers MA1, . . . , MA5 is active at any given time, therefore resulting in signals RF OUT 1 and RF OUT 2 being coupled to the active MISO. As described above, ensuring that only one MISO amplifier is active at any given time is achieved using power supply signals MA1 VSupply, . . . , MA5 V Supply.
In an embodiment, the output stage of analog core 8200 provides optional feedback signals to the digital control module of the VPA. These feedback signals include a Differential Branch Amplitude signal 5950 and a Differential Branch Phase signal 5948, as described above with reference to analog core 5900, to enable a differential feedback approach to monitor for amplitude and phase variations in branches of the VPA. Also, similar to analog core 6100, output power monitoring is provided using PWR Detect signals 6152, 6154, 6156, 6158, and 6160, each of which measuring the power at one of the outputs of VPA. Since only one of the VPA outputs can be active at any time, the PWR Detect signals are summed together, in an embodiment, using a summer 5952, to generate a signal that corresponds to the current output power of the VPA.
Also, similar to analog core 5900, the feedback signals from the output stage are multiplexed using an input selector 5946 controlled by the digital control module. Other aspects of the multiplexing of the feedback signals are described above with reference to analog core 5900.
As described above with respect to analog core 5900, analog core 8200 can be similarly designed to operate as a pure feedback implementation, a pure feedforward implementation, or as a hybrid feedforward/feedback implementation with variable feedforward/feedback utilization.
One difference between analog core 6100 and analog core 8300 relates to the implementation of the vector modulators between the interpolation filter banks and the inputs of the MISO amplifiers. For example, analog core 6100 employs an upper band(s) vector modulator bank (5922, 5924) and a lower band(s) vector modulator bank (5926, 5928). Depending on the desired mode of operation of the VPA, either the upper band(s) or the lower band(s) vector modulator bank is active and couples interpolation filter bank (5910, 5912, 5914, and 5916) to the active MISO in the VPA. On the other hand, analog core 8300 employs a single vector modulator bank comprised of vector modulators 8302 and 8304, which replaces the upper band(s) and the lower band(s) vector modulator banks in analog core 6100. A quadrature generator 8306 provides the required phase signals to vector modulator bank (8302, 8304) based on LO1 signal 7914. In an embodiment, quadrature generator 8306 generates a θ degrees phase signal, a 90 degrees phased signal, a 180 degrees phased signal, and a 270 degrees phased signal relative to LO1 signal 7914.
Further, to ensure proper vector modulation for all supported signal frequencies, a mixing stage and a mixer image-rejection stage can be optionally coupled at the outputs of the vector modulator bank. For example, as shown in
In an embodiment, depending on the desired output frequency of the VPA, mixing stage (8308, 8310) and mixer image-rejection stage (8312, 8314) can be appropriately configured. In an embodiment, this is done using LO2 signal 8012, which controls the frequency conversion performed by mixing stage (8308, 8310), and frequency control signals 7902, which can be used to configure in real time the frequency responses of mixer image-rejection filters 8312 and 8314. In another embodiment, mixing stage (8308, 8310) and mixer image-rejection stage (8312, 8314) are used when the desired output frequency is within the upper band frequency range supported by the VPA (as described above with respect to
As in analog core 6100, as a result of having more than one MISO amplifiers per path, a switching stage is needed to couple the vector modulation stage to the MISO amplifiers in analog core 8300. In
One difference between analog core 8300 and analog core 8400 is that analog core 8400 eliminates mixing stage (8308, 8310) and mixer image-rejection stage (8312, 8314) and directly couples the outputs 8318 and 8320 of vector modulator bank (8302, 8304) to MISO Input Switch 8316. In an embodiment, this is enabled by designing vector modulator bank (8302, 8304) to support a wider range of frequencies, including frequencies in the lower and upper frequency ranges supported by the VPA, such that mixing stage (8308, 8310) and mixer image-rejection stage (8312, 8314) can be eliminated.
Buffer amplifiers 8502, 8504, 8506, and 8508 allow for multiple VPA analog cores to be connected to and controlled by a single digital control module (via DACs). As shown in
MISO amplifiers 6126, 6128, 6130, 6132 and/or 6134 shown in
Output stage embodiment 6200 is substantially similar to output stage embodiment 6000 illustrated in
Similar to embodiment 6000, MISO amplifier stage 6220 in embodiment 6200 includes an optional pre-driver amplification stage, embodied by Pre-Drivers 6206 and 6208, a driver amplification stage, embodied by Drivers 6210 and 6212, and a PA amplification stage, embodied by output stage PAs 6214 and 6216. In an embodiment, substantially constant envelope input signals MA IN1 6202 and MA IN 6204 are amplified at each stage of MISO amplifier 6220, before being summed at the outputs of the PA stage. Input signals MA IN1 6202 and MA IN 6204 correspond to signals 6123 and 6125 in
In an embodiment, MISO amplifier stage 6220 of output stage embodiment 6200 is powered by power supply signals provided by voltage controlled power supply circuits. In another embodiment, MISO amplifier stage 6220 includes optional bias control circuitry controllable by the digital control module. In another embodiment, MISO amplifier stage 6220 includes circuits for enabling an error correction and/or compensation feedback mechanism. In another embodiment, output stage embodiment 6000 includes optional output stage protection circuitry and power detection circuitry. These aspects (power supply, bias control, error correction, output protection, and power detection) of output stage embodiment 6200 are substantially similar to what have been described above with respect to output stage embodiment 6000.
According to embodiments of the present invention, output stage embodiment 6200 may be fabricated using a SiGe (Silicon-Germanium) material including MISO amplifier stage 6220 and the optional output protection and power detection circuitry. In another embodiment, MISO amplifier stage 6220 is fabricated using SiGe in its entirety. In another embodiment, the PA stage (PAs 6214 and 6216) of MISO amplifier stage 6220 is fabricated using GaAs and/or GaN, while other circuitry of MISO amplifier stage 6220 and optional circuitry of the output stage are fabricated using SiGe. In another embodiment, the PA stage and the driver stage (Drivers 6210 and 6212) of MISO amplifier stage 6220 are fabricated using GaAs and/or GaN, while other circuitry of MISO amplifier stage 6220 and optional circuitry of the output stage are fabricated using SiGe. In another embodiment, the PA stage, the driver stage, and the optional pre-driver stage (Pre-Drivers 6206 and 6208) are fabricated using GaAs and/or GaN. In another embodiment, the VPA system may be implemented using CMOS for all circuitry except for the output stage (6030 or 6032) which could be implemented in SiGe, GaAs, or GaN material. In another embodiment, the VPA system may be implemented in its entirety in CMOS. Other variations and/or combinations of fabrication material(s) used for circuitry of the output stage are also possible, as can be understood by a person skilled in the art, and are therefore also within the scope of embodiments of the present invention. Further, output stages within the same VPA may be fabricated using different material, as illustrated in
Analog core implementation 6300 corresponds to a 2-Branch VPA embodiment. This implementation, however, can be readily modified to a 4-Branch or a CPCP VPA embodiment, as will be apparent to a person skilled in the art based on the teachings herein.
Analog core implementation 6300 includes similar input stage, vector modulation stage, and amplification output stage as analog core 5900 of
Similar to analog core 5900, analog core 6300 includes a feedback error correction and/or compensation mechanism. In contrast to analog core 5900, however, analog core 6300 employs a receiver-based feedback mechanism, as opposed to a differential feedback mechanism in analog core 5900. A receiver-based feedback mechanism is one that is based on having a receiver that receives the active output of the VPA, generates I data and Q data from the received output, and feeds back the generated I and Q data to the digital control module. By estimating the delay between the input and the output of the VPA, the feedback I and Q signals can be properly aligned with their corresponding input I and Q signals. In another embodiment, the receiver feedback includes the complex output signal (magnitude and phase polar information) instead of Cartesian I and Q data signals.
In an embodiment, this is done by coupling a receiver (not shown) at the active output of the VPA (5947 or 5949). In
In an embodiment, the AGC circuitry is used to allow the receiver to feedback useful I and Q information over a wide dynamic range of VPA output power. For example, output signals 5954, 5956, 5958, 5960, and 5962 can vary from +35 dBm to −60 dBm in certain cell phone applications. For I and Q data to contain accurate feedback information, the I and Q output of the receiver needs to be scaled to utilize the majority of the input voltage range of the A/Din signal 5736, independently of the output signal power. Digital Control module 5800 is designed to control the VPA to the required output power, which allows digital control module 5800 to determine an appropriate receiver gain to achieve the proper A/D input voltage which is digitized through A/D 5732.
A VPA analog core with a receiver-based feedback mechanism can be implemented as a pure feedback, feedforward, or hybrid feedback/feedforward system. As described above, a pure feedback implementation requires a minimal amount of or no memory (RAM 5608, NVRAM 5610) in the digital control module. This may represent one advantage of an analog core implementation according to analog core 6300, in addition to the elimination of differential feedback measurement circuitry from the analog core. Nonetheless, analog core 6300 can be programmed to operate as a pure feedback implementation by disabling any feedforward correction in digital control module 5800, a pure feedforward implementation by disabling the monitoring of feedback signals, or as a hybrid feedforward/feedback implementation with variable feedforward/feedback utilization.
In an embodiment, the output stage of analog core 6300 includes optional output stage protection circuitry. This is not shown in
Output stage embodiment 6400 is substantially similar to output stage embodiment 6000 illustrated in
Similar to embodiment 6000, MISO amplifier stage 6434 in embodiment 6400 includes an optional pre-driver amplification stage, embodied by Pre-Drivers 6406 and 6408, a driver amplification stage, embodied by Drivers 6410 and 6412, and a PA amplification stage, embodied by output stage PAs 6414 and 6416. In an embodiment, constant envelope input signals MA IN1 6402 and MA IN 6404 are amplified at each stage of MISO amplifier stage 6434, before being summed at the outputs of the PA stage of MISO amplifier stage 6434.
In an embodiment, MISO amplifier stage 6434 of output stage embodiment 6400 is powered by power supply signals provided by voltage controlled power supply circuits. In another embodiment, MISO amplifier stage 6434 includes optional bias control circuitry controllable by the digital control module. In another embodiment, output stage embodiment 6400 includes optional output stage protection circuitry (not shown in
According to embodiments of the present invention, output stage embodiment 6400 may be fabricated using a SiGe (Silicon-Germanium) material including the MISO amplifier stage 6434, the output switching stage 6420, and the optional output protection circuitry. In another embodiment, MISO amplifier stage 6434 is fabricated using SiGe, and the output switching stage 6420 is fabricated using GaAs and/or GaN. In another embodiment, the PA stage (PAs 6414 and 6416) of MISO amplifier stage 6434 and the output switching stage 6420 are fabricated using GaAs and/or GaN, while other circuitry of MISO amplifier stage 6434 and optional circuitry of the output stage are fabricated using SiGe. In another embodiment, the PA stage, the driver stage (Drivers 6410 and 6412), and the output switching stage 6420 are fabricated using GaAs and/or GaN, while other circuitry of MISO amplifier stage 6434 and optional circuitry of the output stage are fabricated using SiGe. In another embodiment, the PA stage, the driver stage, the optional pre-driver stage (Pre-drivers 6406 and 6408), and the output switching stage 6420 are fabricated using GaAs and/or GaN. In another embodiment, the VPA system may be implemented using CMOS for all circuitry except for the output stage (6030 or 6032) which could be implemented in SiGe, GaAs, or GaN material. In another embodiment, the VPA system may be implemented in its entirety in CMOS. Other variations and/or combinations of fabrication material(s) used for circuitry of the output stage are also possible, as can be understood by a person skilled in the art, and are therefore also within the scope of embodiments of the present invention. Further, output stages within the same the VPA may be fabricated using different material, as illustrated in
According to embodiments of the present invention, a VPA output stage can be controlled to vary its amplifier class of operation according to changes in its output waveform trajectory. This concept is illustrated in
It is noted that the VPA output stage amplifier class traverses from non-linear to substantially linear operation as a function of the desired waveform real time trajectory. In this embodiment, the amplifier output changes from a class S amplifier output to a class A amplifier output as the output waveform envelope decreases from its maximum value towards zero. Near the zero crossing, the VPA output stage is operating as a substantially linear amplifier at very low power output. At the zero crossing, the VPA output stage is turned off. This class transiting mode of operation greatly reduces the vector modulator or phase generation circuitry phase accuracy requirements. With regard to the example shown in
Embodiments according to the present invention solve the phase accuracy control problem by transiting multiple classes of operation based on waveform trajectory so as to maintain the best balance of efficiency versus practical vector modulator or phase generator circuitry phase control accuracy for all waveforms. In embodiments, the output power dynamic range of the VPA output stage exceeds 90 dB.
In an embodiment, at higher instantaneous signal power levels, the amplifier class in operation (class S) is highly efficient and phase accuracy is easily achieved using phase control. At lower instantaneous signal power levels, however, phase control accuracy may not be sufficient to achieve the required waveform linearity. This is illustrated in
Accordingly, to support high resolution power control at lower power levels, other mechanisms of control are needed in addition to phase control.
As can be understood by persons skilled in the art, the control regions illustrated in
In embodiments, the power control mechanisms defined by the different control regions enable the transition of the VPA output stage between different class amplifiers. This is shown in
The VPA embodiment of
According to embodiments of the present invention, the MISO amplifier output stage can be caused to transition in real time between different amplifier classes of operation according to changes in output waveform trajectory. In an embodiment, combinations of control mechanisms (outphasing, input bias and/or input amplitude) are used to enable the MISO amplifier stage to transition between different amplifier classes of operation.
Based on the determined instantaneous power level, step 120 of process flowchart 100 includes determining a desired amplifier class of operation, wherein said amplifier class of operation optimizes the power efficiency and linearity of the power amplifier. In an embodiment, determining the amplifier class of operation depends on the specific type of desired output waveform (e.g., CDMA, GSM, EDGE).
Step 130 includes controlling the power amplifier to operate according to the determined amplifier class of operation. In an embodiment, the power amplifier is controlled using phase control (outphasing), bias control, and/or amplitude control methods, as described herein.
According to process flowchart 100, the power amplifier is controlled such that it transitions between different amplifier classes of operation according to the instantaneous power level of the desired output waveform. In other embodiments, the power amplifier is controlled such that it transitions between different amplifier classes of operation according the average output power of the desired output waveform. In further embodiments, the power amplifier is controlled such that it transitions between different amplifier classes of operation according to both the instantaneous power level and the average output power of the desired output waveform.
According to embodiments of the present invention, the power amplifier can be controlled to transition from a class A amplifier to a class S amplifier, while passing through intermediary amplifier classes (AB, B, C, and D).
Embodiments of the invention control transitioning of the power amplifier(s) to different amplifier classes as follows:
To achieve a class A amplifier, the drive level and bias of the power amplifier are controlled so that the output current conduction angle is equal to 360 degrees. The conduction angle is defined as the angular portion of a drive cycle in which output current is flowing through the amplifier.
To achieve a class AB amplifier, the drive level and bias of the power amplifier are controlled so that the output current conduction angle is greater than 180 degrees and less than 360 degrees.
To achieve a class B amplifier, the drive level and bias of the power amplifier are controlled so that the output current conduction angle is approximately equal to 180 degrees.
To achieve a class C amplifier, the drive level and bias of the power amplifier are controlled so that the output current conduction angle is less than 180 degrees.
To achieve a class D amplifier, the drive level and bias of the power amplifier are controlled so that the amplifier is operated in switch mode (on/off).
To achieve a class S amplifier, the amplifier is controlled to generate a Pulse Width Modulated (PWM) output signal.
In an embodiment, the above described real-time amplifier class control of the VPA output stage is accompanied by a dynamic change in the transfer function being implemented in the digital control module of the VPA. This is further described below with respect to
When the VPA output stage operates as a class S amplifier, it effectuates Pulse Width Modulation (PWM) on the received substantially constant envelope signals IN1 and IN2. A theoretical equivalent circuit of the VPA output stage in this amplifier class of operation is illustrated in
A plot of this function, described previously as the magnitude to phase shift transform, is illustrated in
On the other hand, when the VPA output stage operates as a class A amplifier, it emulates a perfect summing node. A theoretical equivalent circuit of the VPA output stage in this amplifier class of operation is illustrated in
According to an embodiment of the present invention, amplifier classes of operation A and S represent two extremes of the amplifier operating range of the VPA output stage. However, as described above, the VPA output stage may transition a plurality of other amplifier classes of operation including, for example, classes AB, B, C, and D. Accordingly, the transfer function implemented by the digital control module of the VPA varies within a spectrum of magnitude to phase shift transform functions, with the transform functions illustrated in
Mathematical basis for a new concept related to processing signals to provide power amplification and up-conversion is provided herein. These new concepts permit arbitrary waveforms to be constructed from sums of waveforms which are substantially constant envelope in nature. Desired output signals and waveforms may be constructed from substantially constant envelope constituent signals which can be created from the knowledge of the complex envelope of the desired output signal. Constituent signals are summed using new, unique, and novel techniques not available commercially, not taught or found in literature or related art. Furthermore, the blend of various techniques and circuits provided in the disclosure provide unique aspects of the invention which permits superior linearity, power added efficiency, monolithic implementation and low cost when compared to current offerings. In addition, embodiments of the invention are inherently less sensitive to process and temperature variations. Certain embodiments include the use of multiple input single output amplifiers described herein.
Embodiments of the invention can be implemented by a blend of hardware, software and firmware. Both digital and analog techniques can be used with or without microprocessors and DSP's.
Embodiments of the invention can be implemented for communications systems and electronics in general. In addition, and without limitation, mechanics, electro mechanics, electro optics, and fluid mechanics can make use of the same principles for efficiently amplifying and transducing signals.
The present invention has been described above with the aid of functional building blocks illustrating the performance of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Any such alternate boundaries are thus within the scope and spirit of the claimed invention. One skilled in the art will recognize that these functional building blocks can be implemented by discrete components, application specific integrated circuits, processors executing appropriate software and the like and combinations thereof.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
The present application is a continuation of U.S. patent application Ser. No. 13/972,147, filed Aug. 21, 2013, now allowed, which is a continuation of U.S. patent application Ser. No. 13/444,012, filed Apr. 11, 2012, now U.S. Pat. No. 8,548,093, which is a continuation of U.S. patent application Ser. No. 12/123,186, filed May 19, 2008, now U.S. Pat. No. 8,315,336, which claims priority to U.S. Provisional Patent Application No. 60/924,519, filed May 18, 2007 (Attorney Docket No. 1744.2160001), and U.S. Provisional Patent Application No. 60/924,622, filed May 23, 2007 (Attorney Docket No. 1744.216000H), all both of which are herein incorporated by reference in their entireties. The present application is related to U.S. patent application Ser. No. 11/509,031, filed Aug. 24, 2006 (Attorney Docket No. 1744.2160002), and U.S. patent application Ser. No. 11/512,360, filed Aug. 30, 2006 (Attorney Docket No. 1744.1900008), both of which are herein incorporated by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| 60924519 | May 2007 | US | |
| 60924622 | May 2007 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 13972147 | Aug 2013 | US |
| Child | 14522679 | US | |
| Parent | 13444012 | Apr 2012 | US |
| Child | 13972147 | US | |
| Parent | 12123186 | May 2008 | US |
| Child | 13444012 | US |
