CONVERTER DEVICE AND CORRESPONDING METHOD

Abstract

A converter circuit to produce a dc output signal from a stabilized input voltage may include a flyback inductor and a drive arrangement to drive said flyback inductor. A control unit is provided sensitive to the demagnetisation of said flyback inductor, said control unit configured to act on a first, a second and a third switch to effect in a cyclical manner the sequence including: a) producing a ramp-like increase of a magnetising current in said flyback inductor following activation of said first switch and said second switch; b) de-activating said first and second switch when the magnetising current in said flyback inductor reaches a predetermined peak value, c) activating said third switch thus producing energy transfer in said flyback inductor, and d) activating said first switch and de-activating said third switch when the voltage on said first electronic switch has reached zero.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Italian Patent Application Serial No. TO2009A000267, which was filed Apr. 7, 2009, and is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to techniques of d.c./d.c. conversion.

The disclosure has been developed with particular attention paid to its possible use in units for driving LEDs used as light sources. A possible application of the present disclosure is driving of medium-power LEDs with insulation barrier with a d.c. input and an output at constant voltage or current.

BACKGROUND

FIG. 1 illustrates an electrical scheme in which a line voltage LV (for example the normal grid voltage at 50 Hz) is converted into an output current/voltage OS that can be used for driving a load, constituted, for example, by a light source such as an LED module.

In the example illustrated here by way of reference, after traversing a rectifier R, the line voltage LV passes through two stages 10 and 20 so that a stabilized output signal OS is supplied at output from the stage 20 itself.

The stage 10 has basically a function of active power-factor control (PFC) and produces at its output a stabilized voltage Vs of the order of 400 Vdc with a ripple at 100 Hz superimposed thereon (i.e., at a frequency that is twice the grid frequency), whilst absorbing a sinusoidal current in phase with the grid voltage.

In the example of FIG. 1, the stage 10 includes an inductor 12 with a diode 14 cascaded thereto. An electronic switch such as a MOSFET 16 is set between the inductor 12 and the diode 14 according to a general T configuration.

This structure is here recalled purely by way of illustration: persons skilled in the art know in fact that the same signal (i.e., the voltage Vs) can be obtained with different techniques.

With reference now to the stage 20, in the example illustrated said stage 20 is basically configured as a d.c.-d.c. stage of a fly-back type, which generates, starting from the voltage Vs, the stabilized output signal OS, i.e., the voltage Vout and/or the current Iout.

In the example represented here, the stage 20 includes a transformer (i.e., a mutual inductor) 22, the secondary winding 24 of which supplies, through a diode 26, the charge of an output capacitor 28 across which the stabilized output voltage Vout is present. The primary winding 30 of the transformer 22 is driven via an electronic switch Q2 (typically constituted by a MOSFET) according to the scheme known as quasi-resonant (QR) mode.

In the scheme of FIG. 1, the reference number 32 designates an input capacitor of the stage 20, across which the voltage Vs is present. Then connected through the primary winding 30 of the transformer 22 is an RCD snubber, i.e., a diode 34, the anode of which comes under the switch Q2 and the cathode of which is connected to an RC group constituted by the parallel of a resistor 37 and a capacitor 39.

The topology represented in FIG. 1 is to be deemed in itself known to the art.

Likewise known is the corresponding operating principle: basically, the switch Q2 is on (i.e., rendered conductive) for voltages lower than the voltage Vs (referred to also as “bus” voltage) reducing the switching-on leakages accordingly. The quasi-resonant (QR) driving strategy gives rise to a variable-frequency system that reduces emission of electromagnetic interference (EMI). The RMS values of the currents in the circuit are lower than those that arise in the case where the driving strategy known as “discontinuous conduction mode” (DCM) is adopted.

The scheme illustrated in FIG. 1 is as a whole very versatile in so far as it enables “coverage” of rather wide voltage and current ranges both at input and at output.

The inventors have noted that the scheme of FIG. 1 suffers from certain intrinsic limitations.

In the first place, the switch Q2 is exposed to a very high voltage, substantially given by the sum of the value of the bus voltage Vs plus n times the output voltage, where n is the transformation ratio (turns ratio) of the mutual inductor or transformer 22.

To obtain a good switching when this operating mode is adopted, the aforesaid ratio, i.e., the number n, is chosen in such a way that the product n·Vout is as close as possible to the value of the bus voltage Vs. Consequently, considering the value of approximately 400 Vdc indicated previously, the voltage across the switch Q2 can reach values of the order of 800 V. This imposes use of a component capable of withstanding a voltage of 900-1000 V, i.e., a rather costly component.

The system is likewise somewhat sensitive to possible overvoltages present on the bus voltage.

Moreover, the reduction of the electromagnetic interference (EMI) cannot be contained beyond a certain limit since there is not an effective zero-voltage switching (ZVS).

Again, there is in any case a power leakage on the mutual inductor due to the presence of the RCD dissipative snubber constituted by the elements 34, 36 and 38 introduced previously.

The inventors have likewise noted that the limitations outlined above can be overcome by resorting to the scheme of the stage 20 represented in FIG. 2, where parts, elements, and components identical or equivalent to the ones already described with reference to FIG. 1 have been designated by the same reference numbers.

In the scheme of FIG. 2, the primary winding 30 of the mutual inductor 22 is driven via a sort of bridge configuration that includes two branches both of which come under (according to a general connection in parallel) the bus line Vs, i.e.:

• • a branch including the diode 34, connected with its cathode directly to the bus line Vs (in practice with the elimination of the RC components 37 and 39 of the snubber of the circuit of FIG. 1) and with the switch Q2 connected in series to the diode 34; and
  • a second branch including a second electronic switch Q1, which is substantially similar to the switch Q2 (for example, once again a MOSFET) and is connected to the line Vs, and a diode 35, which is set between the switch Q1 and ground.

The two terminals of the primary winding 30 of the mutual inductor 22 are in fact connected, respectively, to the intermediate point A between the switch Q1 and the cathode of the diode 36 and, respectively, the intermediate point B between the anode of the diode 34 and the switch Q2.

This scheme is basically a fly-back converter with two switches (constituted by Q2 and Q3), wherein the voltage across Q2 and Q3 is always less than or equal to the bus voltage Vs.

It is possible to choose the turns ratio of the mutual inductor 22 in such a way as to obtain a switching to the on condition at a very low voltage.

In addition, the energy stored in the dispersed inductance of the inductor 22 is recovered in the bus through the diodes 34 and 36.

The inventors have noted that this solution is not free from drawbacks either.

For example, the switch Q1 is floating and, in particular in the embodiment as MOSFET, it also requires a floating supply in order to be able to drive the gate electrode.

For generating said floating voltage it is not possible to resort to a bootstrap technique in so far as the source of the switch Q1 does not necessarily go to zero during the switching period.

Once again it is not possible to achieve an effective condition of zero-voltage switching (ZVS).

SUMMARY

A converter circuit to produce a dc output signal from a stabilized input voltage may include a flyback inductor and a drive arrangement to drive said flyback inductor. A control unit is provided sensitive to the demagnetisation of said flyback inductor, said control unit configured to act on a first, a second and a third switch to effect in a cyclical manner the sequence including: a) producing a ramp-like increase of a magnetising current in said flyback inductor following activation of said first switch and said second switch; b) de-activating said first and second switch when the magnetising current in said flyback inductor reaches a predetermined peak value, c) activating said third switch thus producing energy transfer in said flyback inductor, and d) activating said first switch and de-activating said third switch when the voltage on said first electronic switch has reached zero.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:

FIGS. 1 and 2 have already been described previously;

FIG. 3 is a circuit diagram of a converter as described herein; and

FIG. 4 reproduces various diagrams representing the plots of some signals in a converter as described herein.

DESCRIPTION

The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. In the ensuing description, various specific details are illustrated aimed at providing an in-depth understanding of the embodiments. The embodiments can be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so as not to render various aspects of the embodiments obscure.

Reference to “an embodiment” or “one embodiment” in the framework of this description is aimed at indicating that a particular configuration, structure, or characteristic described in relation to the embodiment is included in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in different points of this description do not necessarily refer to one and the same embodiment. Furthermore, particular conformations, structures, or characteristics can be combined in any adequate way in one or more embodiments.

The references used herein are only adopted for reasons of convenience and hence do not define the scope of protection or the scope of the embodiments.

Various embodiments provide a solution capable of overcoming some or all of the drawbacks of the solutions illustrated previously.

Once again, in the scheme of FIG. 3, component parts or elements that are identical or equivalent to parts, elements, or components already described with reference to FIG. 1 or FIG. 2 are designated by the same reference numbers and will not be described again here for simplicity of illustration.

Basically, as compared with the scheme of FIG. 2, the solution of FIG. 3 envisages replacing with a further switch Q3 the diode 36 connected in series to the switch Q1. In addition, for reasons that will emerge more clearly from what follows, in the scheme of FIG. 3 also two capacitances C1 and C2 associated to the two switches Q2 and Q3 have been illustrated.

The capacitances C1 and C2 can be constituted (at least in part) by the parasitic capacitances of the two switches Q2 and Q3, or else be capacitances added to the circuit. In one embodiment, in order to facilitate zero-voltage switchings (ZVS), C1>C2 and for satisfying this condition the use of an external capacitance C1 may be required.

The scheme of FIG. 3 uses the further switch Q3 for generating a floating supply for the switch Q1, likewise enabling use of a zero-voltage switching (ZVS) for all three switches Q1, Q2, and Q3.

The solution represented in FIG. 3 enables use as switch Q3 of a MOSFET of smaller dimensions than the two MOSFETs that constitute the two first switches (main switches) Q1 and Q2. The switch Q3 has in fact the main function of recirculating the leakage energy and a reduced amount of reverse magnetizing current so as to enable zero-voltage switching.

The reference numbers 100, 200 and 300 designate the lines for driving, respectively, the switch Q1, the switch Q2, and the switch Q3. Said lines come under a control or command circuit or unit (for example a microcontroller) 1000.

In the embodiment illustrated, the unit 1000 is rendered likewise sensitive to:

• • the voltage across the mutual inductor or transformer 22, detected for example via an auxiliary winding present on the secondary of the transformer 22 in order to determine the instant of demagnetization of the inductor 22 itself; and
  • the current in the switch Q2, detected, for example, via an amperometric resistor 38 connected between the source of Q2 and ground.

To simplify illustration of the criteria of operation of the circuit represented in FIG. 3, it is here assumed that:

• • the line 200 is directly connected to the control unit 1000 so as to receive directly the driving pulses issued by said unit;
  • present in the line 100, between the unit 1000 and the gate of the switch Q1, is a system for generation of a delay in switching-on for Q1; in the example of FIG. 3, said delay has been obtained by means of an AND gate 102 with two inputs and a delay block 104 (which introduces, for example, a delay of 1 μs, and is connected to one of the two inputs of the AND gate in such a way that the signal introduced on the line 100 reaches the two inputs directly and with the delay set by the element 104, the overall result being that the driving pulses (positive) issued by the unit 1000 will be applied to the gate of the switch Q1 with a corresponding delay with respect to the pulses for driving the gate of the switch Q2: it will be noted that the delay is thus generated only on the rising edge and not on the falling edge); and
  • present in the line 300 that performs the function of driving of the gate of the switch Q3 is a logic inverter 202 (which is such as to cause the “high” logic level generated by the unit 1000 to become a “low” logic level, and vice versa), as well as a layout substantially similar to the one seen previously, including an AND gate 204 and a delay element 206, i.e., with a switching-on delay of the switch Q3 (also here the delay is only when switching on and not when switching off); said delay can have, for example, a value of 0.5 μs, hence less than, and preferentially equal to half, the delay value set by the line 106.

Persons skilled in the art will, on the other hand, appreciate that the driving scheme represented here corresponds to a solution that can be illustrated easily: operating criteria altogether similar to the ones that can be achieved with said circuit configuration can be achieved with altogether different circuit solutions.

In general, the solutions for driving the switches Q1, Q2 and Q3 may be obtained either applying an analog approach (using normal PWM driving circuits) or applying a digital approach (using microprocessors or else DSP circuits).

For example, the function for driving the gate of the switch Q2 can be performed via a PWM current-mode-controller circuit NCP 1207 manufactured by ON Semiconductor.

Such a circuit is also capable of performing the functions of detection of the state of demagnetization of the mutual inductor 22 (via the auxiliary winding) and of the current on the switch Q2 described previously. In particular, this can occur via the PIN 1 (ZV sense) connected to the resistor 36 and the PIN 3 (Current sense) connected to the resistor 38.

The signal for driving the switch Q2 thus generated by the circuit NCP 1207 (through the pin 5—gate driver) can be brought to the input IN (pin 1) of a circuit such as, for example, the integrated circuit L6384 manufactured by STMicroelectronics to obtain then on the respective outputs HVG (pin 7) and LVG (pin 5) the signals for driving the switch Q1 and the switch Q3.

In the case of the example illustrated in FIG. 3, the driving sequence of the circuit set via the unit 1000 is the one illustrated in the three diagrams of FIG. 4 designated respectively by Q2, Q3, and Q1. Said diagrams refer to a common time scale; in each diagram the “high” level (ON) indicates that the switch is on or active, i.e., conductive; the “low” level (OFF) indicates, instead, that the switch is off or inactive, i.e., non-conductive.

At time t1 the switch Q2 is rendered conductive, i.e., turned on, at zero voltage (ZVS), and the switch Q3 is turned off, i.e., rendered non-conductive. On account of the presence of the inverter 202, the “high” pulse that sends the switch Q2 into conduction assumes, in fact, a low level at output from the inverter 202, which propagates immediately through the AND gate, thus turning off the switch Q3.

The effect of turning-on of the switch Q2 and turning-off of the switch Q3 causes the magnetizing current of the mutual inductor 22 to charge the capacitance C2 across the switch Q3 at the bus voltage Vs.

The output pulse of the unit 1000 that has produced activation of the switch Q2 and turning-off of the switch Q3 propagates, with a delay DT1 established by the delay element 104, at output from the AND gate 102 and reaches the switch Q1, thus switching it on (at zero voltage).

The magnetizing current on the flyback mutual inductor hence starts to increase according to a ramp.

When (in the example considered, thanks to the signal supplied by the resistor 38) the unit 1000 detects that the current of the transformer 22 has reached a pre-determined peak value, the unit 1000 itself governs—at the instant t2 of FIG. 4—turning-off (i.e., passage into conditions of not-conduction) both of the switch Q1 and of the switch Q2.

Once again, it will be appreciated that the turning-off command (“low” logic level) propagates without delays at output from the AND logic gate 102 and hence as far as the switch Q1.

In these conditions, the leakage energy of the transformer is recovered at the bus during a pre-set time interval DTleak (which for simplicity of illustration may be assumed equal to the interval DT2 of FIG. 3: in actual fact, the relation DT2=Dtleak usually applies).

The zero level or “low” level of the output signal of the unit 1000 that determines turning-off of the switches Q1 and Q2 becomes, at output from the logic inverter 202, a signal of “high” logic level, which propagates, with a delay DT2 set by the delay line 206, at output from the AND logic gate 204, determining switching-on (also here at zero voltage) of the switch Q3.

The magnetization energy is consequently transferred to the load on the secondary of the mutual inductor 22.

At a subsequent instant t3, the flyback inductor is found to be demagnetized, and the magnetization inductance of the flyback inductor resonates with the capacitances C1 and C2 (it will be recalled once again that C1 and C2 are not necessarily parasitic capacitances but can be capacitances added to the circuit), causing the voltage across the switch Q2 to go to zero with an oscillation, with the magnetizing current that changes sign.

At the next instant t4, the unit detects—via the auxiliary winding of the inductor 22—that the voltage across Q2 has dropped to zero.

At this point, the sequence repeats as described previously starting from instant t1, i.e., with the switch Q2 that is again switched on at zero voltage, whilst the switch Q3 is simultaneously de-activated.

Without prejudice to the principle of the invention, the details of construction and the embodiments may vary, even significantly, with respect to what has been illustrated purely by way of non-limiting example herein, without thereby departing from the scope of the invention, as defined by the annexed claims. For example, the mode of connection of the intermediate points A and B of the bridge structure that includes the electronic switches Q2, Q1 and Q3 can be reversed with respect to the one illustrated herein. Likewise, the switch in question, here provided in the form of n-channel MOSFET could be provided with electronic switches of different nature, for example, with p-channel MOSFETs, adapting accordingly the polarities of the driving signals of the components involved.

Moreover, the foregoing description regards for simplicity of illustration an example of embodiment in which the switches Q1 and Q2 are de-activated simultaneously (at the instant t2 of the diagram of FIG. 4) so that the energy for obtaining zero-voltage switching (ZVS) of the switch Q3 is the leakage energy alone. In various embodiments, it is possible to envisage that turning-off of Q1 will precede, at least slightly, that of Q2 (i.e., that turning-off of Q2 follows turning-off of Q1) so that the magnetizing current recirculates through the bulk diode of Q3 and through Q2 (kept conductive) facilitating, that is, zero-voltage switching of Q3, even in conditions of reduced load.

Similar considerations apply as regards turning-on of the switch Q2 and turning-off of the switch Q3 (instants t1 and t4 of the diagram of FIG. 4). Whereas the foregoing description refers for simplicity of illustration to an example of embodiment in which said events intervene simultaneously, in various embodiments it is possible to activate the switch Q2 and de-activate the switch Q3 when the voltage on the switch Q2 has reached zero, by causing the de-activation of the switch Q3 to follow the activation of the switch Q2 (with the operating sequence that proceeds according to the same modalities considered above). This operating mode enables possible reduction of the operating frequency of the converter, without this jeopardizing the characteristics of zero-voltage switching.

The above embodiments, which are such as to lead to temporal offset between turning-off of Q2 and turning-off of Q1 or else temporal offset between de-activation of the switch Q3 and activation of the switch Q2 can be used both individually and in combination for optimizing efficiency of conversion and regulating the operating frequency without adversely affecting operation of the converter and zero-voltage (ZV) transitions.

While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

1. A converter circuit to produce a dc output signal from a stabilized input voltage, comprising: a flyback inductor; anda drive arrangement to drive said flyback inductor comprising a bridge structure with a first branch and a second branch fed from a bus line to receive said input voltage and having respective intermediate points to drive the terminals of said flyback inductor, wherein:said first branch comprises a diode interposed between said bus line and the intermediate point of said first branch as well as a first electronic switch acting between the intermediate point of said first branch and ground,said second branch comprises a second electronic switch acting between said bus line and the intermediate point of said second branch,said second branch includes a third electronic switch acting between the intermediate point of said second branch and ground, anda control unit is provided sensitive to the demagnetisation of said flyback inductor, said control unit configured to act on said first, second and third switches to effect in a cyclical manner the sequence including: a) producing a ramp-like increase of a magnetising current in said flyback inductor following activation of said first switch and said second switch;b) de-activating said first and second switch when the magnetising current in said flyback inductor reaches a predetermined peak value, andc) activating said third switch thus producing energy transfer in said flyback inductor, andd) activating said first switch and de-activating said third switch when the voltage on said first electronic switch has reached zero.

2. The converter of claim 1, wherein said control unit is configured to activate said second switch with a given delay with respect to activation of said first switch.

3. The converter of claim 1, wherein said control unit is configured to activate said third switch with a respective given delay with respect to the de-activation of said first and said second switch.

4. The converter of claim 1, wherein said first and third switches have associated capacitances and wherein said control unit is configured to permit the magnetising inductance of said flyback inductor to resonate with said capacitances, between the activation and the de-activation of said third switch, whereby the voltage on said first switch swings back to zero, while said magnetising current in said flyback inductor changes sign.

5. The converter of claim 4, wherein the capacitance associated with said first switch is larger than the capacitance associated with said third switch.

6. The converter of claim 1, comprising at least one of: a first sensor coupled to said flyback inductor to detect demagnetization of said flyback inductor, anda second sensor coupled to said first electronic switch to detect the current on said first electronic switch.

7. The converter of claim 1, coupled with a light source, fed with said dc output signal.

8. The converter of claim 7, wherein the light source comprises a LED module.

9. The converter of claim 1, wherein said control unit is configured to de-activate said first and second switch when the magnetising current in said flyback inductor reaches a predetermined peak value, by simultaneous de-activation or with de-activation of said first switch following de-activation of said second switch.

10. The converter of claim 1, wherein said control unit is configured to activate said first switch and de-activate said third switch when the voltage on said first electronic switch has reached zero by simultaneous activation/deactivation or with de-activation of said third switch following activation of said first switch.

11. A method of producing a dc output signal from a stabilized input voltage via a flyback inductor driven by a bridge structure with a first branch and a second branch fed with said input voltage and having respective intermediate points to drive the terminals of said fly back inductor, wherein: said first branch comprises a diode interposed between said input voltage and the intermediate point of said first branch as well as a first electronic switch acting between the intermediate point of said first branch and ground,said second branch comprises a second electronic switch acting between said input voltage and the intermediate point of said second branch,the method comprising:providing a third electronic switch acting between the intermediate point of said second branch and ground, andeffecting in a cyclical manner the sequence comprising: a) producing a ramp-like increase of a magnetising current in said flyback inductor following activation of said first switch and second switch;b) de-activating said first and second switch when the magnetising current in said flyback inductor reaches a predetermined peak value,c) activating said third switch thus producing energy transfer in said flyback inductor, andd) activating said first switch and de-activating said third switch when the voltage on said first electronic switch has reached zero.