The present disclosure relates to a converter arrangement for an AC system. The converter arrangement comprises a common DC bus and an inter-phase transformer (IPT) interface for connection to an AC phase line.
Multilevel converters are found in many high power applications in which medium to high voltage levels are present in the system. By virtue of their design, multilevel converters share the system voltage (line-to-line or phase voltages) eliminating the need of series connection of devices. These converters may be connected in Delta or Wye in a variety of well-known topologies. These topologies (and variants thereof) can be used for high-voltage direct current (HVDC) and flexible alternating current transmission system (FACTS) applications.
Modular multilevel converters (also called chain-link converters) are often used because of their high efficiencies, their modularity and scalability, as well as for their ability to produce voltage waveforms with low harmonic content which effectively reduce the need for large alternating current (AC) filters. Several modular multilevel converter topologies exist, e.g. M2LC (also called MMLC and MMC), in particular in flexible alternating current transmission system (FACTS) applications, high voltage direct current (HVDC) applications but also in motor drives etc.
Two of the main parameters in the selection among the various alternatives of converters are the cost and the losses. Both parameters are related to the total silicon area used in the converter which is affected by the voltage and current ratings. In addition to steady-state balanced operation of the converter, the designer must take into account the unbalance in the three-phase system. This unbalance results in negative sequence currents and voltages that need to be compensated by the converter. The net effect is that the current rating of the valves (or the total number of cells) will increase due to the zero sequence current or voltage that needs to be injected to compensate for the unbalanced condition. The consequence of this higher number of cells is a higher cost and higher losses.
The problems of higher cost and higher losses associated with negative sequence conditions can be mitigated by including degrees of parallelization into multi-level converter configurations for FACTS applications. Parallel connected sub-converters provide common storage elements which facilitate energy exchange between phases in the converter. This reduces the total stored energy in the converter and avoids overrating due to zero sequence to voltage or current.
The Institute of Electrical and Electronics Engineers (IEEE) article “A large power, low-switching frequency Voltage Source Converter for FACTS applications” by Javier Chivite-Zabalza et al. discloses a converter with parallel 3-level (3-L) neutral point clamped (NPC) inverters. The converter combines four three-phase 3-L NPC inverters that share a common direct current (DC) bus. The twelve resulting converter poles are combined in parallel pairs by means of inter-phase transformers (IPTs, also sometimes called inter-cell transformers, ICT) to obtain two sets of three-phase systems. A problem with this topology is that an intermediate transformer is needed to obtain the required voltage and the intermediate transformer adds significant cost to the converter arrangement, particularly in industrial applications where connection voltages are typically low enough to avoid transformer connection. Another disadvantage with the topology is that it requires a series connection of cascaded intermediate transformers to further increase the output voltage.
It is an objective of the present invention to provide an improved converter topology at a reduced cost.
According to an aspect of the present invention, there is provided a converter arrangement for an AC system. The converter arrangement comprises at least one phase leg comprising a first sub-converter (2a), a second sub-converter, an IPT interface configured for connecting the first and second sub-converters with a phase line of the AC system, and at least one DC bus connected to the first and second sub-converters. The first sub-converter is connected in parallel with the second sub-converter between the at least one DC bus and the IPT interface. Each of the first and second sub-converters comprises a chain-link converter connected to the IPT interface and comprising a plurality of converter cells connected in series with each other, and a common DC link multilevel converter connected to the at least one DC bus and in series with the chain-link converter.
By using a plurality of parallel sub-converters, each of which comprising a plurality of modular converter cells, the output voltage to the IPT can be increased, e.g. compared with using NPC inverters only, while the current through the cell switches can be kept down. Further, connecting the sub-converters via an IPT interface, allows for current sharing between phase-legs which have a common DC-link, and allows for superimposing the voltage waveform of each sub-converter and thus combining the harmonic performance of each sub-converter to achieve a higher effective switching frequency.
Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to “a/an/the element, apparatus, component, means, step, etc.” are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated. The use of “first”, “second” etc. for different features/components of the present disclosure are only intended to distinguish the features/components from other similar features/components and not to impart any order or hierarchy to the features/components.
Embodiments will be described, by way of example, with reference to the accompanying drawings, in which:
Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments are shown. However, other embodiments in many different forms are possible within the scope of the present disclosure. Rather, the following embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout the description.
In accordance with the present invention, IPTs are used while obviating the need for intermediate transformers (or reducing the number of cascaded intermediate transformers). Instead, various other multi-level converters may be used for the input of the IPTs.
Another embodiment of a three-phase converter arrangement 1 of the present invention is schematically illustrated in
There are several variants of the topology of the present invention, which could also be considered for e.g. FACTS applications, present and future. It may be possible to utilise any converter topology as the sub-converter 2 building block. Typical series cascade transformer arrangements could also be used to further increase the total output voltage of the converter. Any of these variants would still utilise advantages of the present invention e.g. the use of IPTs 3 to reduce switching losses, and a common DC bus 5 within the converter arrangement 1.
The creation of extra voltage levels with use of IPTs may make it feasible to utilise higher voltage valves/cells. A problem with utilising higher voltage cells in other topologies is that the lower number of voltage levels may result in unacceptable harmonic performance. However, the use of the IPT interface 3 provides double the number of voltage levels and hence a two times increase in the harmonic performance. The invention gives flexibility for the compensation of negative sequence currents. It maintains the cascaded multi-level structure to deal with high voltages and reduces the need to de-rate or dimension the semiconductors for higher voltage or current for zero-sequence injection.
The IPT 3 may effectively be a single primary, single secondary transformer, where the two windings are connected in series. The series connection point may be taken as the output and the remaining two terminals as the inputs. The two closely coupled windings may be arranged so that the flux created by equal currents entering the input terminals is cancelled out, leaving in the core the flux created by the voltage difference between the two input terminals. This results in the voltage-ampere (VA) rating of the IPTs being a small fraction of the total VA rating for the converter arrangement 1, and also ensures equal current sharing between the two input poles.
The resultant minimal flux in the IPTs may mean they require a physically small core and relatively large windings. This means however that the modulation strategy should be tailored to control the time integral of voltage difference at the inputs of each IPT. This may limit the maximum flux in the core of each IPT and reduce the resultant cost of the IPTs.
Typically, if converter poles are parallel so that the output of each pole is connected together, then each pole must be switched to create the same output voltage at every instant. The IPTs, however, support any instantaneous voltage difference between the two poles, and the output voltage may then be the average of the voltage at the two inputs.
There are various modulation methods that may be be utilised in this new converter arrangement 1. Harmonic elimination techniques may be used to mitigate the harmonics occurring at multiples of the fundamental frequency and hence improve the harmonic performance.
Other strategies, such as carrier based techniques and space vector modulation may also/alternatively be employed with the present invention.
Utilising a common DC bus 5 for the entire converter arrangement 1 may mean that a fault in one valve/cell 8 renders the whole converter arrangement non-operational. This may not meet FACTS typical reliability requirements. One way to increase the redundancy is to use an IPT interface 3 with a higher number of IPT legs as in
The present disclosure has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the present disclosure, as defined by the appended claims.
Filing Document | Filing Date | Country | Kind |
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PCT/EP2014/053069 | 2/18/2014 | WO | 00 |