Patent Application
20060265443
An embodiment of the invention relates generally to microprocessor (or simply, processor) systems, and more particularly, to the capability of such systems for converting a number from a first base representation to a second base representation.
In processor systems, there is frequently a need to convert a number from one base to another base representation. For example, while human users are accustomed to dealing with numbers in their decimal representation, computers typically perform their arithmetic in binary or hexadecimal representation. Thus, when a result has been computed in a processor system as a binary 1101, this will need to be converted to its corresponding “13” for display to a human user.
To efficiently convert between binary and decimal numbers across a wide range (e.g., integers 0 to 1018) in a processor system, a method has been developed that applies division and remainder operations to the original binary number sequentially. If c is a binary integer to be converted into its decimal format, then c may be represented in decimal as
c=d0·10P+d1·10p−1+d2·10p−2+. . . +dp−1·101+dp (1)
where the general form above allows for a total of p+1 digits of precision in the decimal representation. The division and remainder method computes each decimal digit recursively, that is the determination of a particular digit depends on a previously calculated adjacent digit. In particular, the following sequence is typically taken:
dp=c % 10 c1=(c−dp)/10 (2)
dp−1=c1 % 10 c2=(c1−dp−1)/10
. . .
d1=cp−1 % 10 cp=(cp−1−d1)/10
d0=cp % 10
The percentage sign in Equation (2) above refers to the remainder of the division of the two operands. First, dp is computed, by taking the remainder of c (the number to be converted, in binary format) divided by 10. Next, c1 is computed as shown, followed by dp−1 which uses c1. The sequence thus continues until d0, the last digit of the decimal representation, has been computed. This algorithm thus calculates, in sequence, for the case of an 18 digit decimal representation, d17, c1, d16, c2, . . . d1, c17, and d0.
In most modem processor systems, the arithmetic operations in Equation (2) above would actually be computed in binary format using, for example, division units that may be part of the arithmetic and logic unit (ALU) of a processor. An example of a processor instruction that converts a binary integer into a decimal integer is the FBSTP-Store BCD Integer and Pop instruction for the IA-32 Intel® Architecture (see IA-32 Intel® Architecture Software Developer's Manual, Volume 2A, page 3-217 (Order Number 253666, 2004)). Note that BCD refers to binary coded decimal, where each digit of the decimal representation is represented by a binary code.
Since the conversion between binary and decimal occurs quite frequently during operation of a processor system, faster conversion methodologies can greatly benefit the overall performance of the system.
The embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” embodiment of the invention in this disclosure are not necessarily to the same embodiment, and they mean at least one.
A machine-implemented method for converting a number from a first base to a second, different base is described that exposes more instruction-level parallelism, to achieve faster conversions. The method may in general be applied to convert from a base b, where b is greater than or equal to 2, to a different base B, where B is also greater than or equal to 2. The underlying arithmetic operations in the conversion may be implemented in base b. For most modem processor systems, b=2 (binary format), and B=10 (decimal format). The methodology described here, however, can alternatively be applied to other base conversions, as well as being implemented in processor systems whose arithmetic operations are not necessarily performed in binary arithmetic.
In embodiments illustrated here, a positive, binary integer is converted into its decimal format. However, negative numbers can also be converted using such methodologies, by treating the sign of the number separately. The methodologies are also applicable to conversions from binary to decimal floating-point formats, if the decimal floating-point data types have integer decimal coefficients.
Referring to
In some conventional processor systems, a multiplication instruction is issued to the processor at the rate of one per processor clock cycle, in each floating-point unit that is available for executing the instruction. Accordingly, reducing the number of such multiplications directly impacts the number of clock cycles required for the conversion. To help reduce the number of multiplications, and also because of special encoding that has been proposed for a revision of the floating-point formats by the Institute of Electrical and Electronics Engineers, IEEE Standard 754-1985 for Binary Floating-Point Arithmetic (“revised IEEE Standard 754”), only powers of ten with an exponent that is a multiple of three should be used.
Next, the method proceeds with operation 108 in which a second set of machine-operations are performed using results of the first operation 104, to obtain further results which include at least t1, t2, . . . t4. As in the first operations, there may also be results t0 and t5 which are at the boundary and accordingly may be given special treatment, e.g. t0=a0. Advantageously, this methodology allows a0-a4 to be computed in parallel, and also allows t1-t5 to be computed in parallel, thereby helping accelerate the overall conversion process.
The next operation in
Additional details of the methodology illustrated in
a0=floor (c·k15)//by Property 1, a0=d0·102+d1·10+d2 (3)
a1=floor (c·k12)//by Property 1, a1=d0·105+d1·104+ . . . +d4·101+d5
a2=floor (c·k9)//by Property 1, a2=d0·108+d1·107+ . . . +d7·101+d8
a3=floor (c·k6)//by Property 1, a3=d0·1011+d1·1010+ . . . +d10·101+d11
a4=floor (c·k3)//by Property 1, a4=d0·1014+d1·1013+ . . . +d13·101+d14
//a5=c=d0·1017+d1·1016+ . . . +d16·101+d17
//a0=t0=d0·102+d1·10+d2
t1=a1−1000·a0//t1=d3·102+d4·10+d5 (4)
t2=a2−1000·a1//t2=d6·102+d7·10+d8
t3=a3−1000·a2//t3=d9·102+d10·10·+d11
t4=a4−1000·a3//t4=d12·102+d13·10+d14
t5=a5−1000·a4//t5=d15·102+d16·10+d17
As seen in the above detail, each of the partial results a0, a1, . . . is given by the product of c and a respective constant, truncated to the largest integer which is not greater than its real argument (the floor function). Note that the constants k3, k6, . . . may be previously calculated or otherwise obtained and stored, prior to invoking the method for conversion.
In Equations (4) above, a second set of quantities t1, t2, . . . t5 are computed, where for each quantity, a linear combination of a respective set of two of the first quantities a0, . . . a5 is computed. In particular, a multiply-add operation may be performed for each ti, as shown. In this example, each computed ti will be a value that lies between 0 and 999 (decimal). Thus, referring back to
The quantity ti may be used as an index into a table of entries each of which contains the encoding of a respective, three-digit decimal value that may be numerically equal to the index. In other words, the table is a previously computed look-up table with, in this example, 1000 entries, where each entry contains the decimal format of a binary number in the range 0-999. In the example here where the precision of the decimal representation is 18 digits, each entry of this look-up table refers to three decimal digits that are encoded in BCD format, where each table entry may contain 12 bits (4 bits for each digit). If, however, the three decimal digits are encoded as specified in the proposed, revised IEEE Standard 754, then each table entry need contain no more than 10 bits (this is also referred to as densely packed decimal encoding, or DPD in short).
As was explained above in the Background section, a conventional technique for converting from a first base to a second base calculates the digits of the second base representation in a sequence of division and remainder operations. The methodology described above, in accordance with an embodiment of the invention, advantageously avoids a large number of division or remainder operations, in favor of typically faster multiplications. In addition, these multiplications may be performed in parallel in at least two different levels (ai and ti), thereby further accelerating the conversion process. As an example, a purely software implementation of the conversion methodology described above, for converting a positive binary integer into decimal format, has been implemented on an ITANIUM 2 processor platform of Intel Corp., Santa Clara, California, measuring thirty-one (31) processor clock cycles. Compare this with the several hundred clock cycles typically needed by the FBSTP instruction.
A breakdown of the thirty-one cycles may be as follows: six (6) are taken for loading the constants ki (using, e.g., LDF instructions), 4+7 (11) for calculating a ai (e.g., using FMPY and FCVT.FX.TRUNC instructions), four (4) for calculating ti with, e.g. XMA instructions, seven (7) for calculating the index to the look-up table (e.g., using GETF.SIG, SHL, and ADD), and finally one (1) instruction for loading a group of three decimal digits from the table (e.g., using LD2). There may also be two additional clock cycles needed for the delayed issue of instructions that cannot be issued in the same clock cycle. Note that the instructions for calculating the ai and those for calculating ti can each be executed in parallel, thus further reducing the latency of the conversion.
The following property has been defined so as to ensure that the conversion method described above works correctly, for all integer numbers c that do not exceed the maximum output value that can be represented, in this example from 0 to 999999999999999999. The property referred to here as Property 1 is stated here for b=2 and B=10, however, it is true for any b greater than or equal to 2 and B greater than or equal to 2. To clarify some of the nomenclature used below: the floor( ) function returns the largest integer not greater than its real argument; the ceil( ) function returns the smallest integer not less than its real argument; the frac( ) function returns the fractional part, and is frac(x)=x−floor(x), 0≦frac(x)<1.
Property 1
Let c ∈ N be a number in base b=2, and d0·10P+d1·10p−1+d2·10P−2+ . . . +dp−1·101+dp its representation in base B=10, with d0, d1, . . . dp ∈{0, 1, . . . , 9}. Let x ∈{1, 2, 3, . . . , p} and ρ=ln 10/ln 2.
If y ∈ N, y≧ceil (frac(ρ·x)+ρ·(p+1)) and kx is the value of 10−x rounded up (toward positive infinity) to y bits,
kx=(10−x)Rp,y (5)
then
floor (c·k)=d0·10p−x+d1·10p−x−1+d2·10p−x−2+ . . . +dp−x−1·101+dp−x (6)
(Note that rounding for example to nearest or to fewer bits than the minimum y may not yield the correct product for all integer numbers c that do not exceed the maximum output value that can be represented, in this example from 0 to 999999999999999999.
Proof:
10−x=2−ρ·x=2−ρ·x −floor(−ρ·x)·2floor(−ρ·x)=2frac(−ρ·x)·2floor(−ρ·x)
As 1≦2frac(−ρ·x)<2 and rounding is to y bits:
ulp(kx)=2floor(−ρ·x)−y+1
Let
H=d0·10p−x+d1·10p−x−1+d2·10p−x−2+ . . . +dp−x−1·101+dp−x
where H≦10p−x+1−1. It is necessary to show that:
H≦c·kx<H+1 <=>
H≦(d0·10p+d1·10p−1+d2·10p−x−2+ . . . +dp−x·10x++dp−x+1·10x−1+ . . . +dp) (10−x+ex)<H+1
where kx=10−x+ex, with ex the rounding error and 0≦ex<1 ulp(kx). The inequalities to prove are:
H≦(10x·H+dp−x+1·10x−1 +. . . +dp) (10−x+ex)<H +1
The first inequality is clearly satisfied as 10x·H·10−x=H. For the second, notice that:
dp−x+1·10x−1+ . . . +dp≦10x−1
It is thus sufficient to prove that:
(10x·H+10x−1)·(10−x+ulp(kx))≦H+1<=>
[10x·(H+1)−1]·(10−x+2floor(−ρ·x)−y+1)≦H+1<=>
10x·(H+1)2floor(−ρx)−y+1−10−x2floor(−ρ·x)−y+1)≦0 <=>
[10x·(H+1)−1]·2−floor(ρ·x)−y≦10−x
(we used the fact that for a non-integer z, floor(z)+floor(−z)=−1)
As H+1≦10p−x+1, it is sufficient to show that:
(10p+1−1)·2−floor(ρ·x)−y≦10−x
It is sufficient then to prove that:
10p+1·2−floor(ρ·x)−y≦10−x<=>
10p+x+1≦2floor(ρ·x)+y<=>
2ρ·(p+x+1)≦2floor(ρ·x)+y<=>
ρ·(p+x+1)≦floor(ρ·x)+y
It is sufficient to prove that:
ρ·(p+x+1)≦floor(ρ·x)+ymin <=>
ρ·(p+x+1)≦floor(ρ·x)+ceil (frac(ρ·x)+ρ·(p+1)) <=>
ρ·(p+x+1)≦ceil (floor(ρ·x)+frac(ρ·x)+ρ·(p+1)) <=>
ρ·(p+x+1)≦ceil (ρ·x+ρ·(p+1)) <=>
ρ·(p+x+1)≦ceil (ρ·(p+x+1))
This is true, and concludes the proof.
The values of ymin for p=17 and three other precisions defined by the revised IEEE Standard 754 are shown in the following table giving the precision of the multiplicative constants as a function of the decimal data type precision. The constants ki that may be pre-calculated are also listed.
Thus, if the approximations to the negative powers of 10 are calculated to a predetermined and sufficient precision, the methodology for converting binary integers to decimal as described above is correct for all integer numbers c that do not exceed the maximum output value that can be represented, in this example form 0 to 999999999999999999. Note that although in the above examples, there are fewer constants k being used whenever the precision p is substantially smaller, this need not be true in all cases. For example, for both p=15 and p=17, there are five constants.
The methodology described above may be used to significantly improve the latency of processor instructions that perform base conversions, such as the FBSTP instruction on the IA-32 architecture. The methodology replaces many division and remainder operations by relatively simple multiplications, with constants being used that are approximations to negative powers of the second base (where these constants may be pre-calculated). In addition, the methodology replaces the sequential nature of conventional algorithms with a method that exposes more instruction-level parallelism, which can be used better on processors that have pipelined functional units, multiple functional units, or multi-core processors.
As an alternative to a purely software implementation,
A delay unit 212 has its input coupled to a result output of the truncation unit (which delivers the integer ai). The delay unit 212 serves to hold a previous result a−1, until a subsequent result ai becomes available at the truncation unit output. See for example, Equation (4) above where, for example, t3 is computed to be a linear combination of a2 and a3. This linear combination may be a multiply-add operation, performed by a multiply-add unit 216 (back to
For even better performance, a pre-calculated table of constants 220 may be added that has an input coupled to a result output of the multiply-add unit 216, so that the ti acts as an index into the table. An output of the table 220 provides one or more digits of the number in the decimal representation, where in this case three contiguous digits are provided by each entry of the table. For example, if the index is t, (see Equation (4)), then the output digits are d3 d4 d5. Other mappings are, of course, possible between the index and the output of the table.
An embodiment of the invention may be a machine readable medium having stored thereon instructions which program a processor to perform some of the operations described above, e.g. multiply-add instructions; truncate instructions. In other embodiments, some of these operations might be performed by specific hardware components that contain hardwired logic (see the circuit hardware units of
A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), not limited to Compact Disc Read-Only Memory (CD-ROMs), Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), and a transmission over the Internet.
Further, a circuit hardware design may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners. First, as is useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process. Furthermore, most designs, at some stage, reach a level of data representing the physical placement of various devices in the hardware model. In the case where conventional microelectronic fabrication techniques are used, data representing a hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In any representation of the design, the data may be stored in any form of a machine-readable medium.
The invention is not limited to the specific embodiments described above. For example, the binary to decimal conversion described above uses previously calculated approximations to only powers of ten whose exponents are a multiple of three. However, in general, other sets of powers of the second base may be selected for use in the conversion methodology, depending upon, for example, the format and precision of the representation in the second base. Accordingly, other embodiments are within the scope of the claims.
