The present disclosure relates generally to semiconductor memory devices, methods, and systems, and more particularly, to methods, devices, memory controllers, and systems for copyback operations.
Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its information and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent information by retaining stored information when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.
Memory devices can be combined together to form a solid state drive (SSD). A solid state drive can include non-volatile memory (e.g., NAND flash memory and NOR flash memory), and/or can include volatile memory (e.g., DRAM and SRAM), among various other types of non-volatile and volatile memory. An SSD can be used to replace hard disk drives as the main storage device for a computer, as the solid state drive can have advantages over hard drives in terms of performance, size, weight, ruggedness, operating temperature range, and power consumption. For example, SSDs can have superior performance when compared to magnetic disk drives due to their lack of moving parts, which may avoid seek time, latency, and other electro-mechanical delays associated with magnetic disk drives. SSD manufacturers can use non-volatile flash memory to create flash SSDs that may not use an internal battery supply, thus allowing the drive to be more versatile and compact.
An SSD can include one or more discrete memory packages, and one or more of the memory packages can be multi-chip packages (MCPs). A MCP can include a number of memory dies or chips thereon, which can be referred to as logical units (LUNs). As used herein, “a number of” something can refer to one or more of such things. As an example, the memory chips and/or dies associated with a MCP can include a number of memory arrays along with peripheral circuitry. The memory arrays can include memory cells organized into a number of physical blocks, with each of the physical blocks capable of storing multiple pages of data.
Various memory systems include a system controller to perform operations such as erase operations, program operations, and read operations, for example. In addition, some memory systems support “copyback” operations. A copyback operation can involve moving data of a first page (e.g., a source page) to a second page (e.g., a target page, which may sometimes be referred to as a destination page). Performing a copyback operation can include a copyback read operation, a copyback program operation, and a copyback program verify operation. A copyback read operation can include reading data stored in a source page and storing it in a page buffer. A copyback program operation can include reprogramming the data stored in the page buffer to the target page. In some instances, the data stored in the page buffer can be moved (e.g., transferred) directly to the target page without reading the data out of the page buffer. The copyback program verify operation can then be used to confirm whether the data is correctly programmed to the target page.
Memory systems supporting copyback operations can include signal processing (e.g., error correction code and/or other data recovery algorithms) components such as error correction code (ECC) circuitry. The complexity of ECC circuitry (e.g., the number of logic gates required to implement adequate error correction) increases with advancing manufacturing technology, for example. Increased ECC circuit complexity can lead to drawbacks such as increasing the size of memory system controllers that include ECC functionality, among other drawbacks.
The present disclosure includes methods, devices, memory controllers, and systems for performing copyback operations. One or more methods include reading data from a first memory unit of a memory device responsive to a copyback command, performing signal processing on the data using a signal processing component local to the memory device, and programming the data to a second memory unit of the memory device.
Embodiments of the present disclosure can provide various benefits such reducing bus load during copyback operations, reducing the time used for data recovery operations, such as ECC operations during copyback, and reducing or preventing error propagation associated with copyback operations as compared to prior systems and methods, among other benefits.
Embodiments can also provide benefits such increasing memory capacity of memory systems and/or reducing pin counts associated with memory system controllers as compared to prior systems.
In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, the designators “N,” and “M,” particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included with one or more embodiments of the present disclosure. As used herein, “a number of” something can refer to one or more of such things.
The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 104 may reference element “04” in
Examples hosts 102 can include laptop computers, personal computers, digital cameras, digital recording and playback devices, mobile telephones, PDAs, memory card readers, and interface hubs, among other host systems. The interface 106 can include a serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe), or a universal serial bus (USB), among other connectors and interfaces. In general, however, host interface 106 can provide an interface for passing control, address, data, and other signals between the memory system 104 and the host 102.
Host 102 can include one or more processors 105 (e.g., parallel processors, co-processors, etc.) communicatively coupled to a memory and bus control 107. The processor 105 can be one or more microprocessors, or some other type of controlling circuitry, such as one or more application-specific integrated circuits (ASICs), for example. Other components of the computing system 100 may also have processors. The memory and bus control 107 can have memory and other components directly communicatively coupled thereto, for example, dynamic random access memory (DRAM) 111, graphic user interface 118, or other user interface (e.g., display monitor, keyboard, mouse, etc.).
The memory and bus control 107 can also have a peripheral and bus control 109 communicatively coupled thereto, which in turn, can connect to a memory system, such as a flash drive 119 using a universal serial bus (USB) interface, a non-volatile memory host control interface (NVMHCI) flash memory 117, or the memory system 104. As the reader will appreciate, the memory system 104 can be used in addition to, or in lieu of, a hard disk drive (HDD) in a number of different computing systems. The computing system 100 illustrated in
Enterprise solid state storage appliances are a class of memory systems that can currently be characterized by terabytes of storage and fast performance capabilities, for example 100 MB/sec, 100K inputs/outputs per second (IOPS), etc. According to one or more embodiments of the present disclosure, an enterprise solid state storage appliance can be configured using solid state drive (SSD) components. For example, with respect to
The bus 220 can send/receive various signals (e.g., data signals, control signals, and/or address signals) between the memory devices 232-1, . . . , 232-N and the system controller 215. Although the example illustrated in
As illustrated in
The memory units 212-1 to 212-4 can include one or more arrays of memory cells. In this example, the memory units 212-1 to 212-4 include flash arrays having a NAND architecture.
The system controller 215 includes a signal processing component 216. In this example the signal processing component is an error correction component 216 (e.g., an ECC engine), which can determine (e.g., detect) whether an amount of data (e.g., a page of data) includes bit errors and can correct a particular number of errors in the data. The number of bit errors correctable by the error correction component 216 can vary based on factors such as the type of ECC used and/or the complexity of the error correction circuitry, for example. As used herein, error correction can refer to data recovery including, but not limited to, error detection and/or correction. As such, data recovery operations performed by an error correction component such as error correction component 216 can include detection of bit errors and/or correction of bit errors associated with a page of data, among other operations associated with data recovery, for instance. Accordingly, signal processing component 216 can employ an error correction code (ECC) as part of data recovery performed by the component 216 and/or other data recovery components associated with a controller (e.g., 215).
Arrow 251 shown in
In this example, the copyback operation 251 is performed internally to a particular memory device (e.g., 232-1). For instance, the memory device 232-1 can include a page buffer (not shown) that can store a page of data corresponding to a copyback read operation, and the page of data can be reprogrammed from the buffer to the target page. As such, the data does not have to be written out to the system controller 215 via bus 220, which can save processing time, for example. However, a number of bit errors can occur in the data page during the copyback operation 251. Moreover, the number of bit errors associated with copyback operation 251 may reach or exceed the number of errors correctable by the error correction component 216.
The memory devices 332-1, . . . , 332-N can include a number of memory units 312-1, 312-2, 312-3, and 312-4 that provide a storage volume for the memory system 304. The memory units 312-1 to 312-4 can be dies or chips, which can be referred to as logical units (LUNs). As such, the memory devices 332-1, . . . , 332-N can be multi-chip packages (MCPs) that include a number of dies 312-1 to 312-4 (e.g., NAND dies in this example). The system controller 315 includes an error correction component 316, which can determine whether a page of data includes bit errors and can correct a particular number of errors in the page of data.
Unlike the system 204 illustrated in
However, because the copyback operation involves transferring data along bus 320 for both the copyback read and copyback program operations, the bus 320 is not available for performing other operations on other memory devices 332-1, . . . , 332-N of the system 304 during copyback.
The bus 420 can send/receive various signals (e.g., data signals, control signals, and/or address signals) between the memory devices 430-1, . . . , 430-N and the system controller 415. Although the example illustrated in
As illustrated in
In contrast to the systems 204 and 304 described in
In the embodiment illustrated in
Copyback operations performed in system 404 remove restrictions as compared to previous systems such as system 204 shown in
Since the error correction components 435-1, . . . , 435-N are local to (e.g., located within) the respective memory devices 430-1, . . . , 430-N (e.g., as opposed to within the system controller 415), error correction associated with copyback operations can be performed locally within the memory devices 430-1, . . . , 430-N. Performing error correction functions locally within the memory devices 430-1, . . . , 430-N can provide benefits such as reducing the load on the bus 420 during copyback operations, reducing the time used for error correction operations (e.g., ECC operations) during copyback, and reducing or preventing error propagation associated with copyback operations as compared to prior systems and methods, among other benefits.
In the example shown in
In the example shown in
In this example, each of the memory devices 630-1, . . . , 630-M include four chip enable (CE) pins 638-1 (CE1), 638-2 (CE2), 638-3 (CE3), and 638-4 (CE4) that receive CE signals from the channel controller 627-N. However, unlike in the example illustrated in
In the example illustrated in
As illustrated, a daisy chain configuration can be created between the memory devices 730-0, 730-1, 730-2, and 730-3. In this example, the enable input pin 739-0 of device 730-0 and the enable output pin 741-3 of device 730-3 are not connected (NC). The enable input pins 739 of the other devices are connected to the enable output pin 741 of the previous device in a daisy chain configuration as shown in
As illustrated in
In operation, the state of the enable input pins 739-0, 739-1, 739-2, and 739-3 determines whether the respective memory device 730-0, 730-1, 730-2, and 730-3 is able to accept commands. For example, if the enable input pin of a particular device is high and the CE pin 738-1 of the device is low, then the particular device can accept commands. If the enable input of the particular device is low or the CE pin 738-1 is high, then the device cannot accept commands. A volume select command can be issued by the system controller in order to select a particular target volume (e.g., 713-0, 713-1, 713-2, 713-3) coupled to a particular CE pin 744 of the system controller. In this manner, volume addressing can be used to access target volumes of the memory devices 730-0, 730-1, 730-2, and 730-3.
Embodiments of the present disclosure are not limited to the topology illustrated in
The present disclosure includes methods, devices, memory controllers, and systems for performing copyback operations. One or more methods include reading data from a first memory unit of a memory device responsive to a copyback command, performing signal processing on the data using a signal processing component local to the memory device, and programming the data to a second memory unit of the memory device.
It will be understood that when an element is referred to as being “on,” “connected to” or “coupled with” another element, it can be directly on, connected, or coupled with the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled with” another element, there are no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. As used herein the term “or,” unless otherwise noted, means logically inclusive or. That is, “A or B” can include (only A), (only B), or (both A and B). In other words, “A or B” can mean “A and/or B” or “one or more of A and B.”
Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.
In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.
This application is a Non-Provisional Application of U.S. Provisional Application No. 61/409,375, filed Nov. 2, 2010, the entire specification of which is herein incorporated by reference.
Number | Date | Country | |
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61409375 | Nov 2010 | US |