1. Field of the Invention
The present invention relates to a COordinate Rotational DIgital Computer (CORDIC) method and a CORDIC architecture applied in vector rotation, and more particularly, to a CORDIC method based on Extended Elementary-Angle Sets (EEAS) and Trellis-based Searching (TBS) and its architecture.
2. Description of Related Art
Currently, vector rotation is the kernel of various digital signal-processing applications, including discrete orthogonal transformations, lattice-based digital filtering, matrix computation, complex-valued number manipulation, etc. In X-Y coordinates one vector rotation operation can be expressed as:
The CORDIC algorithm is a well-known iterative method for the computation of vector rotation, which requires only one shift operation and one addition operation to perform a vector rotation operation. The CORDIC algorithm decomposes the rotation angle θ into a combination of pre-defined elementary angles as follows:
where N is the number of elementary angles, μ={1, −1} is the rotation sequence which determines the direction of the i-th elementary angle of a(i)=tan−1(2−i), and ε denotes the residue angle.
Based on equation (1), the recurrence equations of the CORDIC algorithm can be written as
for i=0, 1, . . . , N−1. In practical fixed-point implementation, for data wordlength of W bits, no more than W iterations of the recurrence relation in equation (2) need be performed, i.e., N≦W. Also, the final values, x(N) and y(N), need to be scaled by an accumulated scaling factor expressed as follows:
In the above CORDIC algorithm, each elementary angle needs to be performed sequentially so as to complete the micro-rotation phase. However, in the applications where the rotation angles are known in advance, it would be advantageous to relax the sequential constraint on the micro-rotation phase. The angle recoding (AR) technique is done by extending the set of μ(i) from {1, −1} to {1, −1, 0}. By substituting μ(i)=0 into equation (2), one can skip the micro-rotation of the elementary angle a(i )=tan−1(2−i). Nevertheless, the AR technique imposes no restriction on the iteration number. Rotation angles of different values may need unequal numbers of iterations, which may lead to bus/timing alignment problems in VLSI circuits. Therefore, it is desired for the above CORDIC algorithm to be improved to mitigate and/or obviate the aforementioned problems.
The object of the present invention is to provide a CORDIC method and a CORDIC architecture applied in vector rotation, which can effectively improve SQNR performance, reduce the number of iterations and decrease the hardware complexity.
In accordance with one aspect of the present invention, a CORDIC method applied in vector rotation is provided, which first extends an elementary angles set:
S1={ tan−1(a′*2−s′):a′ε{−1,0,1},s′ε{0,1, . . . , N−1}},
by representing the elementary angles as the arctangent of the sum of two single signed-power-of-two (SPT) terms (a′*2−s′) to an extended elementary angles set:
s2={ tan−1(a′0*2−s′
where N is the number of elementary angles. Next, a combination of elementary angles is found from the extended elementary angles set such that the residue angle error:
can be minimized, where θ is a target angle; Rm is the maximum iteration number; j denotes the iteration index; s0(j), s1(j) ε{0, 1, . . . , N−1} are the rotational sequences; a0(j), a1(j) control the direction of j-th micro-rotation of 2−S
In accordance with another aspect of the present invention, a CORDIC processor applied in vector rotation is provided for performing micro-rotational phase operations:
scaling phase operations:
In the CORDIC processor, a first register is provided for temporarily storing x(i) or {tilde over (x)}(m). A second register is provided for temporarily storing y(i) or {tilde over (y)}(m). First and second barrel shifters have input terminals connected to output terminals of the first register. Third and fourth barrel shifters have input terminals connected to output terminals of the second register. A first multiplexer has a first input terminal connected to an output terminal of the first barrel shifter, and a second input terminal connected to an output terminal of the third barrel shifter. A second multiplexer has a first input terminal connected to an output terminal of the second barrel shifter, and a second input terminal connected to an output terminal of the fourth barrel shifter. A third multiplexer has a first input terminal connected to the output terminal of the first barrel shifter, and a second input terminal connected to an output terminal of the third barrel shifter. A fourth multiplexer has a first input terminal connected to the output terminal of the second barrel shifter, and a second input terminal connected to the output terminal of the fourth barrel shifter. A first adder/subtractor has two input terminals connected to output terminals of the first and second multiplexers, respectively. A second adder/subtractor has two input terminals connected to output terminals of the first adder/subtractor and first register, respectively, and an output terminal connected to an input terminal of the first register. A third adder/subtractor has two input terminals connected to output terminals of the third and fourth multiplexers, respectively. A fourth adder/subtractor has two input terminals connected to output terminals of the third adder/subtractor and second register, respectively, and an output terminal connected to an input terminal of the second register. A control unit controls the first to fourth barrel shifters, the first to fourth multiplexers, and the first to fourth adders/subtractors to perform the CORDIC operation iteratively.
In accordance with still another object of the present invention, a CORDIC architecture applied in vector rotation is provided having (Rm+Rs) CORDIC processors connected in cascade form, in which the Rm leading processors are used in the micro-rotation phase and the following Rs processors are used in the scaling phase.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
To depict the EEAS in the first stage, a parameter Rm is employed to be the maximum iteration number in the AR technique. Therefore, the AR problem can be summarized as:
Given a target angle θ and the maximum iteration number Rm, find the rotation sequence μ(i) ε{1,−1,0} for 0≦i≦N−1, such that the residue angle error:
is minimized subject to the constraint:
To facilitate the derivation of the present EEAS scheme, the AR problem described above is rewritten in an alternative form. The reformulation is done by removing the redundant iterations of μ(i)=0 in equation (4), changing the variables and index, and using the equality ±tan−1(A)=tan−1(±A). Then, the equations (4) and (5) can be recast in a single compact form as:
where j(0≦j≦Rm−1) denotes the iteration index; s(j) ε{0, 1, . . . , N−1} is the rotational sequence that determines the micro-rotation angle in the j-th iteration; a(j) ε{−1, 0, 1} is the directional sequence that controls the direction of the j-th micro-rotation of 2−s(j); θ′(j) is the j-th micro-rotation angle and defined as θ′(j)≡ tan−1(a(j)*2−s(j)).
Therefore, equation (6) shows that the AR problem is finding the combination of elements from a set, which consists of all possible values of θ′(j), so that εm can be minimized. Such a set is called the elementary angles set (EAS) S1, and is defined as
S1={ tan−1(a′*2−s′):a′ε{−1,0,1},s′∈{0,1, . . . , N−1}}. (7)
By observing equation (7), it is seen that the EAS S1 is comprised of an arctangent of single signed-power-of-two (SPT) term, i.e., tan−1(a′*2−s′). By representing the elementary angles as the arctangent of the sum of two SPT terms, the EAS S1 can be extended to an extended elementary angles set (EEAS) S2 as follows:
s2={ tan−1(a′0*2−s′
Based on the EEAS S2 developed in equation (8), the recurrence equations of the CORDIC algorithm can be modified as:
for 0≦j≦Rm−1, where a0(j), a1(j), s0(j) and s1(j) denote the parameters to control the j-th micro-rotation of the elementary angle of tan−1(a0(j)*2−S
With the above EEAS S2 and given θ and Rm, it is desired to find the parameters of a0(j), a1(j), s0(j) and s1(j) (i.e., the combination of elementary angles from EEAS S2), such that the residue angle error:
can be minimized.
In the second stage of processing, the TBS algorithm is employed to find the combination of elementary angles, wherein Z(S2) denotes the number of the elementary angles in the extended set S2, and each distinct elementary angle in the set is expressed as r(k), for 1≦k≦Z(S2), i.e., S2={r(1), r(2), . . . , r(Z(S2))}. Moreover, in the TBS algorithm, there are Z(S2) states in each step. For the k-th state (1≦k≦Z(S2)) of the i-th search step, a cumulative angle Φ(i,k) is used to denote the best approximation of angle θ in the k-th state up to the i-th step. The TBS algorithm can be described as follows:
(1) Initialization Step:
The TBS algorithm is started by setting all Φ(i,k) as the corresponding elementary angles, that is:
Φ(1,k)=r(k) for all k. (11)
Taking Z(S2)=15 as an example, the initialization and transfer paths of the TBS algorithm are illustrated in
(2) Accumulation Step
A path in the trellis, which leaves the k-th state at the i-th step and enters the k-th state at the (i+1)-th step, corresponds to an operation of Φ(i,k)+r(k′). For all paths, the appended angle of Φ(i,k)+r(k′) becomes the candidate for Φ(i+1,k′). As shown in
(3) Comparison and Selection Step
The TBS algorithm involves calculating and minimizing the difference between the target angle θ and Φ(i,k) for all k at each search step i. To be specific, Φ(i+1,k) is determined by:
Φ(i+1,k)=min{|Φ(i,k*)+r(k)−θ|:1≦k*≦Z(S2)}. (12)
Then, the selected path is denoted as the surviving path. After calculating all the cumulative angles Φ(i,k) for all k, their corresponding surviving paths can be obtained. Continuing in this manner and moving to the (i+1)-th step until reaching the maximum iteration number (i=Rm), Φ(Rm,k) can be obtained for 1≦k≦Z(S2). Consider the example, in which i=2 and k=12. The process of equation (12) is illustrated in
(4) Determination of the Global Result and Trace Back Step
After calculating the cumulative angles for all states at the last search step, i.e., Φ(Rm,k) for 1≦k≦Z(S2), the next procedure for the TBS algorithm is to determine the global result, θTBS. Similar to the determination of the surviving path, the θTBS is decided as follows:
θTBS=min{|Φ(Rm,K′)−θ|:1≦k′≦Z(S2)}. (13)
Next, all the micro-rotations can be determined by tracing back from the state, whose corresponding Φ(Rm,k) is the best approximation of θ, along with its surviving backward path.
The procedure for trace back is illustrated in
When considering that each micro rotation will scale up the norm of a vector, in the known type-II scaling operation, the accumulated scaling factor P is quantized as:
where {circumflex over (P)} denotes the quantized value of P, k(m)ε{1,−} and q(m)ε{0,1, . . . , W−1}, Rs is the counterpart of Rm in the micro-rotation phase, determining the number of iterations in the scaling phase. With this type-II scaling operation, and by increasing the number of possible values that can be represented by (1+k(m)·2−q(m)), we obtain a similar derivation of the EEAS scheme that employs one extra SPT term in equation (14):
where k0(m)ε{1,−1,0}, k1(m)ε{1,−1,0}, q0(m)ε{0,1, . . . , W−1}, and q1(m)ε{0,1, . . . , W−1}.
By doing so, it is expected to obtain more accurate approximations of P. The scaling operation can be accomplished within Rs, iterations by using the recurrence equations:
wherein the initial settings for the scaling phase are set as {tilde over (x)}(0)=x(Rm) and {tilde over (y)}(0)=y(Rm).
The first register 711 is provided for temporarily storing x(i) or {tilde over (x)}(m), and its output terminal is connected to the first and second barrel registers 721 and 722, and its input terminal is connected to the second adder/subtracter 742. The second register 712 is provided for temporarily storing y(i) or {tilde over (y)}(m), and its output terminal is connected to the third and fourth barrel registers 723 and 724, and its input terminal is connected to the fourth adder/subtractor 744.
The output terminal of the first barrel register 721 is connected to the first input terminal of the first multiplexer 731 and the third multiplexer 733. The output terminal of the second barrel register 722 is connected to the first input terminal of the second multiplexer 732 and the fourth multiplexer 734. The output terminal of the third barrel register 723 is connected to the second input terminal of the first multiplexer 731 and the third multiplexer 733. The output terminal of the fourth barrel register 724 is connected to the second input terminal of the second multiplexer 732 and the fourth multiplexer 734.
The output terminals of the first and second multiplexers 731 and 732 are connected to the input terminals of the first adder/subtractor 741. The output terminal of the first adder/subtractor 741 is connected to the input terminal of the second adder/subtractor 742. The output terminals of the third and fourth multiplexers 733 and 734 are connected to the input terminals of the third adder/subtractor 743. The output terminal of the third adder/subtractor 743 is connected to the input terminal of the fourth adder/subtractor 744. The output terminals of the second and fourth adders/subtractors 742 and 744 are connected to the input terminals of the first and second register 711 and 712, respectively.
The control unit 701 is provided to control the first to fourth barrel shifters 721˜724, the first to fourth multiplexers 731˜734, and the first to fourth adders/subtractors 741˜744, so as to implement the CORDIC algorithm. Two separate phases are performed to complete a single CORDIC rotation, i.e., the micro-rotational phase and the scaling phase. In the micro-rotational phase, under the control of the control unit 701, the first and second barrel shifters 721 and 722 are shifted by s1(i) and s0(i) bits, respectively. The third and fourth barrel shifters 723 and 724 are shifted by s0(i) and s1(i) bits, respectively. The second input terminals of the first and second multiplexers 731 and 732 are switched to connect to their output terminals thereof, respectively. The first input terminals of the third and fourth multiplexers 733 and 734 are switched to connect to their output terminals thereof, respectively. The control unit 701 uses a0(i) and a1(i) to control first to fourth adders/subtracters 741˜744, so as to perform addition and subtraction.
In the scaling phase, under the control of the control unit 701, the first and second barrel shifters 721 and 722 are shifted by q1(m) and q0(m) bits, respectively. The third and fourth barrel shifters 723 and 724 are shifted by q0(m) and q1(m) bits, respectively. The first input terminals of the first and second multiplexers 731 and 732 are switched to connect to their output terminals thereof, respectively. The second input terminals of the third and fourth multiplexers 733 and 734 are switched to connect to their output terminals thereof, respectively. The control unit 701 uses k0(m) and k1(m) to control the first to fourth adders/subtracters 741˜744, so as to perform addition and subtraction.
By unfolding the iterative implementation of the above CORDIC processor, a parallel structure can be obtained as depicted in
In view of the foregoing, it is known that the present invention performs the CORDIC algorithm by extending EAS to EEAS. As shown in
Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed.
Number | Date | Country | Kind |
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90127085 A | Oct 2001 | TW | national |
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20030050949 | Van Wechel et al. | Mar 2003 | A1 |
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Number | Date | Country | |
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20030097388 A1 | May 2003 | US |