Correctable output driver and method of using the same

Abstract

A driver circuit is presented which can transition between output voltage levels at a high switching speed. The preferred output driver is a PECL driver having both a correction circuit portion and a drive circuit portion. The correction circuit senses changes in the base-to-emitter forward bias voltage V.sub.BE of drive transistors within the drive circuit. Thus, any change in performance of those drive transistors is replicated in the correction circuit, which then produces a compensating current. The compensating current is modulated by a reference voltage value, and mirrored to the drive circuit. The drive circuit includes not only differential input transistors and differential drive transistors, but also a resistor coupled to the base terminal of each drive transistor. The resistor receives the compensating current which then offsets any change in voltage level (V.sub.OH or V.sub.OL) produced at the output of the drive transistors. The compensating current and specifically the compensating current as reflected upon the drive transistor outputs offset any dependence upon the forward bias voltage of the drive transistor caused by, for example, temperature or fabrication skews.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an electronic circuit and, more particularly, to an output driver circuit which produces relatively constant output logic levels between logic transitions despite process variations and changes in temperature.

2. Description of the Related Art

The form and function of emitter-coupled logic ("ECL") is generally well known. Typical ECL involves a bipolar form of logic, whereby the bipolar transistors are arranged so that they do not generally operate at saturation. ECL enjoys a high input impedance, rapid switching speed and low output impedance compared to other logic families. The ECL V.sub.DD and V.sub.EE conductors have traditionally been powered from a negative power supply, where V.sub.DD is grounded. In more recent designs, however, ECL is often used with a positive power supply. In this instance, V.sub.DD is generally set at a positive voltage and V.sub.EE is tied to ground. Positive ECL designs are often times referred to as positive- or pseudo-ECL ("PECL"). A benefit of PECL is its compatibility with standard logic supplies, such as those found in metal oxide semiconductors ("MOS") technology.

As clock speeds rise beyond 100 MHz, the advantages of using PECL become more obvious. For example, PECL can be employed within an output driver circuit to produce high speed output signals. The speed of those signals make them well suited as a clocking source or as serial link transmitted signals, if applied in the complementary form.

A clocking signal or a transmission signal must switch rapidly in modern computer and/or communication systems. Using a communication system as an example, a PECL driver is well suited for transferring ECL complementary (i.e., hereinafter "differential") outputs across a transmission medium such as a high-speed serial link comprising fiber, coax, or twisted pair. A CY7B923 transmitter obtainable from Cypress Semiconductor Corp., includes a PECL output driver capable of transferring data over a serial link at rates exceeding 160 Mbits/second.

FIG. 1 depicts a typical communication system linked by a serial bus (i.e., serial link) which is driven by a high speed PECL driver. Differential signals (OUTA and OUTA') output from transmitter 12 of communication system 10 are less susceptible to ground noise problems than, for example, single-ended MOS outputs since noise in differential PECL signals exists on both signals and becomes "common-mode". Common-mode noise is known to be more easily removable than many other types of noise. In addition, output driver 14 within transmitter 12 produces less noise as seen by the power supply. Namely, when one output drive transistor is on, the other output driver transistor is off. This ensures a constant current supply draw regardless of which output state is being produced.

Further illustrated in FIG. 1, and forming a part of transmitter 12 is an encoder 16 which encodes parallel bytes received by transmitter 12 and converts those encoded bytes into a serial stream of bits via serializer 18. The serial bit stream is then presented in complementary form across a serial link 20. Termination resistors 22 can be coupled at or near the receiver 24. Receiver 24 can therefore de-serialize and decode the serial bit stream as shown by blocks 26 and 28.

FIG. 1 illustrates only one example in which a PECL circuit is used. However, it is understood that the speed at which the PECL output signal transitions is equally suited for any application which requires high speed switching. Therefore, the PECL circuit 29 shown in FIG. 2, while suitable as an output driver 14, is nonetheless applicable to any high speed output driver which utilizes differential output signals.

Differential binary signals are defined as the difference between two outputs at dissimilar logic values. Thus, when signal OUTA is at a logic "1" or "high" value, then output OUTA' is at a logic "0" or logic "low" value. At other times, output OUTA' is at a logic high value, while output OUTA is at a logic low value. The logic high value produced at the output of circuit 29 in FIG. 2 is often referred to as V.sub.OH, while the logic low value from circuit 29 is deemed V.sub.OL.

FIG. 2 illustrates one example of a PECL output driver 29. The performance of first and second drive transistors 31 and 33 can substantially vary depending on their operating temperature and the methodology in which they were made. For example, an increase in operating temperature will decrease the base-to-emitter forward bias voltage ("V.sub.BE ") of transistors 31 and 33. V.sub.BE is a well known parameter which typically characterizes a bipolar transistor's performance and is generally defined as a voltage, which, when exceeded, will cause current to flow from the base to the emitter and, more importantly, activation of current from the collector to the emitter. V.sub.BE can also vary based on the parameters used to fabricate transistors 31 and 33. As those parameters change, or as temperature changes, the performance of the transistors correspondingly changes as evidenced by a change in V.sub.BE. There may be numerous processing parameters which might vary to effect that change such as, for example, doping concentrations. It is generally recognized, for example, that for every 1.degree. C. increase in temperature, the forward bias voltage from the base-to-emitter (i.e., V.sub.BE) will decrease approximately 2.0 mV. A decrease in V.sub.BE will affect the performance of output driver 29.

PECL output driver 29 includes a pair of differential inputs (INA and INA') forwarded to a corresponding pair of npn bipolar transistors 35 and 37. If, for example, input INA' is at a logic high value (i.e., a voltage value which permits significant current flow from the collector to the emitter of transistor 35) then the amount of current flow will be equal to that sourced by current source 39. The sourced current is labeled I.sub.DIFF. Current I.sub.DIFF will traverse the collector and emitter of transistor 35, but will not traverse transistor 37 since the complimentary input INA is at a low logic value causing transistor 37 to remain in a "off" state. In this case the output voltage at node OUTA will be at the low logic level, while the output voltage at node OUTA' will be at the high logic level. The output logic levels are described by the following equations which clearly demonstrate the dependence of V.sub.OH and V.sub.OL on V.sub.BE :

V.sub.OH =V.sub.DD -V.sub.BE (eq. 1) V.sub.OL =V.sub.DD -V.sub.BE I.sub.Diff (R.sub.49) (eq. 2)

Referring to FIG. 3, an improved output driver 30 is presented. Specifically, driver 30 includes not only first and second drive transistors 32 and 34, differentially coupled bipolar transistors 36 and 38, and resistor pair 50 and 54, but also includes a pair of diode-connected transistors 42 and 44, and associated resistors 46 and 48 connected in parallel between resistor pairs 50 through 56. Resistors 50, 52, 54 and 56 are shown connected between a positive power supply V.sub.DD and respective collectors of npn transistors 36 and 38. If transistor 38 is conducting, and transistor 36 is non-conducting, then current I.sub.DIFF will produce a voltage through resistor 50 and 52. If driver 30 is operating at temperatures where V.sub.BE required for significant current flow is relatively large, then the voltage developed across resistor 50 will not be sufficient to turn on the diode connected transistor 44, and the current through resistor 50 will be essentially I.sub.DIFF But as temperature rises and V.sub.BE decreases, the voltage across resistor 50 will be enough to create a current flow through resistor 54, transistor 44 and resistor 48. Accordingly, the diode-connected transistor 44 will be forward biased causing current I.sub.T to flow through resistor 54 and resistor 48. Current I.sub.T will add to current I.sub.ON through resistor 50 to equal I.sub.DIFF.

Depending on which of the differential pair of transistors 36 and 38 are on, the current through resistors 50 and 52, and 54 and 56 determine the output logic levels (V.sub.OL and V.sub.OH) at the emitter terminals of transistors 32 and 34. For example, if input INA' causes transistor 38 to turn on, then the base voltage upon transistor 32 is at a logic low level. The result of a logic low level at the base of transistor 32 is a logic level low (V.sub.OL) at output OUTA. The level of V.sub.OL is, however, dependent upon the amount of current ION through resistor 50. If the current which is diverted from one side to the other (i.e., current I.sub.T) increases, I.sub.ON will decrease. The result of a decreasing I.sub.ON is to lower the voltage across resistor 50, and thereby raise the voltage at the base of transistor 32. This results in an increase in V.sub.OL. The converse is true with respect to V.sub.OH. Specifically, an increase in I.sub.T will cause a decrease at the base of transistor 34, and therefore a decrease of V.sub.OH at output signal OUTA'. The relationship between V.sub.BE and V.sub.OH, as well as V.sub.OL for driver 30 shown in FIG. 3 is: as V.sub.BE decreases, V.sub.OH and V.sub.OL increases. However, the diverted current I.sub.T compensates for the decreasing V.sub.BE so that it will cause V.sub.OH to decrease and V.sub.OL to increase. Thus, diverting current will offset the increasing V.sub.OH.

Diverting current I.sub.T must therefore be carefully regulated to establish output high (V.sub.OH) values at or near a midscale voltage of the maximum and minimum output high values. That is, current I.sub.T must be adjusted so that V.sub.OH values fall within a specified or pre-defined maximum and minimum amounts required by the manufacturer for a particular application. For example, transmitter part no. CY7B923 requires for proper, discernible output values, that V.sub.OH maximum and minimum values fall within the range of V.sub.DD -0.83 and V.sub.DD -1.03, respectively. Likewise, the specified V.sub.OL values should not exceed the maximum of V.sub.DD -1.62 and the minimum of V.sub.DD -1.86.

While the diverting current helps compensate for a decrease in V.sub.BE by offsetting the increasing V.sub.OH, its effect on V.sub.OL is to further increase it. It is therefore necessary to utilize yet another compensating mechanism to offset the increasing V.sub.OL. To compensate for current lost through resistor 50 when transistor 38 is on and when V.sub.BE decreases, additional current must be sourced by current source 40. An increase in I.sub.DIFF dependent upon V.sub.BE is, however, difficult to achieve and implement since a temperature-compensating current source is not always accurate across the entire temperature range.

An explanation of the mechanism by which V.sub.OH and V.sub.OL is established can, alternatively, be described in a mathematical sense. If transistor 36 is off, and diverted current I.sub.T is present through a forward biased diode-connected transistor 44, then V.sub.OH is as follows:

V.sub.OH =V.sub.DD -V.sub.BE -I.sub.T (R.sub.54) (eq. 3)

Similarly, transistor 38 being on will produce V.sub.OL at the output of transistor 32 as follows:

V.sub.OL =V.sub.DD -I.sub.DIFF R.sub.52 -(I.sub.DIFF -I.sub.T)R.sub.50 -V.sub.BE (eq. 4)

From equations one and two, it is recognized that both V.sub.OH and V.sub.OL are not only dependent upon the diverted current I.sub.T, but also upon V.sub.BE of the respective output drive transistors 32 and 34. In addition, for low swing output drivers, the swing amounts may not be sufficient to turn on the diode-connected transistors 42 and 44. Yet further, the differential configuration shown in FIGS. 2 and 3 cannot compensate for single ended PECL outputs without adding deleterious compensation to the other half (second end of the complementary set). To help rectify these problems, a circuit is needed to provide better compensation for changes in V.sub.BE. It would be desirable that an improved PECL output driver be derived which does not rely upon tail current or cross coupling of the differential stage's load resistors. Furthermore, the improved output driver circuit must produce output logic levels V.sub.OL and V.sub.OH which are not dependent whatsoever upon V.sub.BE, or the need for varying a current source to compensate for changes in V.sub.BE.

SUMMARY OF THE INVENTION

The problems outlined above are in large part solved by an improved PECL output driver circuit. The present circuit comprises an output driver coupled with a V.sub.BE sensing/correction circuit (henceforth "correction circuit"). The correction circuit replicates or mimics changes in V.sub.BE, and produces a corresponding current from the replicated V.sub.BE value. Thus, if V.sub.BE decreases, the resulting current will also decrease. Current produced from the correction circuit leads to a compensating current which is mirrored possibly in scaled form to the output driver circuit. The compensating current is forwarded through a resistor coupled to a base of a drive transistor. The drive transistor produces the output logic level (either V.sub.OH or V.sub.OL) from the output driver. Compensating current forwarded through the resistor coupled to the drive transistor base varies in proportion to changes in the replicated V.sub.BE to offset changes in V.sub.BE of the drive transistor. Accordingly, as V.sub.BE decreases within the drive transistor, the compensating current will correspondingly and automatically increase to maintain a constant output logic level.

This approach will equally apply to a CMOS circuit with source follower output configurations in which the output voltage levels must be maintained constant across temperature and process variations. In such a case, the correction circuit will replicate changes in the V.sub.GS of the output source follower device(s). The rest of the circuit will function as described above for the PECL output driver.

Beneficially, the compensating current maintains V.sub.OH and V.sub.OL within a specified range regardless of changes in temperature and processing conditions to which and from which the output drive transistor is exposed or produced, respectively. The present output driver circuit is therefore considered to have two circuits which, according to one embodiment, includes the correction circuit and the actual drive transistors. The correction circuit produces a compensating current from a voltage produced across a replicating transistor. The voltage may be placed across a correction resistor to produce a scaled compensating current. The scaled compensating current is represented as a difference between current produced by a current source operably coupled to the output of an operational amplifier and a current forwarded through the correction resistor.

The output driver circuit further includes a current mirror which mirrors the scaled compensating current from the correction circuit to resistors coupled at the base terminals of a pair of output drive transistors. The mirrored current will be forwarded to a pair of differential input transistors. The amount of scaling depends upon a ratio of resistor values, and is approximately the ratio of the correction resistor value to the respective resistor coupled at the base terminal of the corresponding output drive transistor. Scaling serves to minimize power consumption within the correction circuit. Thus, the scaled compensating current is a factor m less than the compensating current forwarded through the resistor at the drive transistor base terminal.

Broadly speaking, the present invention concerns an output driver circuit. The driver circuit comprises a first drive transistor having an emitter and a base. A first resistor is coupled to the base of the first drive transistor. The first resistor is adapted to receive a compensating current which produces a voltage through the first resistor that varies in proportion to changes in the base-to-emitter forward bias voltage V.sub.BE of the first drive transistor. A second drive transistor may also be provided having an emitter and a base. A second resistor is coupled to the base of the second drive transistor, through which another compensating current can be forwarded to produce a voltage that varies in proportion to changes in the V.sub.BE of the second drive transistor.

The present invention yet further concerns a transmitter. The transmitter can transmit any signal, possibly a clocking signal sent to a local load device, or a communications signal forwarded across, for example, a serial link. The transmitter comprises an output driver which includes a pair of bipolar transistors. The transistors produce, during operation, a corresponding pair of complementary output voltage values. Each of the complementary output voltage values transitions between a pair of pre-defined voltage ranges and remains within the pre-defined voltage ranges between transitions regardless of changes in V.sub.BE of the pair of bipolar transistors.

The present invention yet further concerns a method of compensating for changes in V.sub.BE within a drive transistor. The method comprises replicating the V.sub.BE of the drive transistor. The replicated V.sub.BE is then converted into a compensating current. The compensating current is then forwarded to a resistor coupled to the base of the drive transistor to counter any changes in the V.sub.BE within the drive transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

FIG. 1 is a block diagram of a communication system having a transmitter coupled by a serial link to a receiver;

FIG. 2 is a circuit diagram of an output driver potentially used within the transmitter of FIG. 1;

FIG. 3 is a circuit diagram of another type output driver potentially used within the transmitter of FIG. 1;

FIG. 4 is a circuit diagram of an output driver according to one exemplary embodiment of the present invention;

FIG. 5 is a graph of output logic levels forwarded from the output driver which remain relatively constant whenever the temperature increases beyond a specific temperature and, more specifically, the output logic level is shown to remain relatively constant whenever the base-to-emitter voltage (V.sub.BE) of the output drive transistors decrease below a reference voltage (V.sub.REF); and

FIG. 6 is a graph of V.sub.BE decreasing with increase in temperature.

While the invention may be modified and have alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Turning to FIG. 4, a circuit diagram of an output driver 60 is shown according to one embodiment of the present invention. Driver 60 includes a correction circuit portion 62 and a selectable drive portion 64. Beginning with correction circuit portion 62, a replicating transistor 66 is provided between the power supply and a non-inverting input of operational amplifier 68. Since driver 60 is formed on a monolithic substrate, and since transistor 66 is dimensioned and concurrently formed with drive transistors 70 and 72 of output drive portions 64, transistor 66 has the same performance characteristics as transistors 70 and 72. More importantly, transistor 66 demonstrates the same V.sub.BE as transistor 70 and 72 since it is exposed to the same temperature and the same processing parameters as those transistors. Thus, a voltage V.sub.BE is produced across transistor 66 since the collector and base terminals are connected. Amplifier 68 assures the voltage across transistor 66 is isolated from yet mimicked across correction resistor 74.

Current within current source 76 assures a constant current draw across transistor 66 at all times. The replicated voltage placed across resistor 74 corresponds to voltage across transistor 66. Current source 78 produces a current I.sub.REF which is equal to a predefined voltage V.sub.REF divided by a resistance value within source 78. For reasons explained below, V.sub.REF is set approximately near or at a midscale voltage between the maximum and minimum values for V.sub.BE.

By setting V.sub.REF at a midscale value, and defining the resistance of source 78 also at a pre-defined amount, a constant I.sub.REF will be produced which equals the sum of I.sub.VBE and I.sub.M. I.sub.VBE is equal to the replicated V.sub.BE divided by the value of resistor 74. I.sub.REF is preferably defined to exceed I.sub.VBE so that current I.sub.M exists when V.sub.BE is less than V.sub.REF, and is represented as a scaled compensating current. I.sub.M is mirrored by current mirrors 80 and 82 to current I.sub.OUT2 and I.sub.OUT3. Transistors within current mirror 80 are preferably smaller than the mirror transistors of current mirror 82. Likewise, correction resistor 74 is larger than first and second resistors 84 and 86 of driver portion 64. The ratio of resistor values between correction resister 74 and first resistor 84 or second resistor 86 produces a scale factor m. Scale factor m defines an integer difference between current I.sub.M and current I.sub.OUT2 or I.sub.OUT3 For example, m can equal 32, whereby I.sub.OUT3 is 32 times the amount of I.sub.M. Likewise, current I.sub.OUT2 is 32 times current I.sub.M. Scaling helps minimize power consumption and die area within correction circuit portion 62.

Driver portion 64 includes a differential pair of input transistors 88 and 90 which, when active in a complementary fashion, produce a current I.sub.DIFF from source 92 through respective resistors 84 or 86. For example, if input signal INA' is at a high logic level, then transistor 90 will turn on causing a combination of I.sub.DIFF and I.sub.OUT3 through second resistor 86. Absent I.sub.DIFF through transistor 88 will ensure that only I.sub.OUT2 will exist through first resistor 84. A combination of I.sub.DIFF and I.sub.OUT3 will produce a substantial voltage drop through second resistor 86.

The output logic levels V.sub.OH and V.sub.OL upon drive transistor 70 and 72 remain independent of changes in V.sub.BE within those transistors. Any change in V.sub.BE within transistors 70 and 72 is compensated by a variable I.sub.OUT (I.sub.OUT2 or I.sub.OUT3) within the first or second resistors 84 and 86. Thus, I.sub.OUT is deemed a compensating current. If V.sub.BE produced by replication transistor 66 is larger than V.sub.REF, no correction will be necessary and the scaled compensation current I.sub.M as well as the compensating current I.sub.OUT will be zero. If, however, I.sub.BE produced within the replication transistor 66, as mimicked upon transistor 70 and 72, is less than I.sub.REF, then the scaled compensating current I.sub.M will be proportional to V.sub.REF -V.sub.BE. This translates to, or is mirrored to, the compensating current I.sub.OUT. The compensated current I.sub.OUT is deemed to correct both V.sub.OH and V.sub.OL to offset V.sub.BE variations within transistors 70 and 72 (as well as transistor 66), those variations being a result of process skews and temperature changes since compensating current I.sub.OUT is generated from V.sub.BE. A diverting current is not needed, and diversion of that current from one side of the differential transistor pair to the other is no longer necessary.

Replication transistor 66, in combination with the current source 76, are chosen to provide similar current density from the collector to the emitter of transistor 66 as would be expected from transistor 70 or 72. Therefore, V.sub.BE of transistor 66 will be approximately equal to V.sub.BE of the drive transistor 70 or 72. The resulting current across resistor 74 is as follows:

I.sub.VBE =V.sub.BE /R.sub.74 (eq. 5)

To establish a reference voltage V.sub.REF from which point corrections start, it is beneficial to review FIGS. 3 through 5 in combination. Current I.sub.REF is subtracted from I.sub.VBE, and the result is applied to the input of the p-channel current mirror 80. Since mirror 80 can only source current, I.sub.VBE is limited by I.sub.REF. If I.sub.VBE tries to increase above I.sub.REF, the scaled compensating current I.sub.M will be zero. Thus, the following equations apply:

I.sub.M =0, if V.sub.BE is greater than V.sub.REF (eq. 6) I.sub.M =I.sub.REF -I.sub.VBE =(V.sub.REF -V.sub.BE)/R.sub.74, if V.sub.BE is less than V.sub.REF (eq 7)

Since compensating current I.sub.OUT2 and I.sub.OUT3 are scaled versions of I.sub.M, where the scale factor "m" is equal to a ratio of R.sub.74 divided by R.sub.84 or R.sub.86, the resulting correction voltage across first and second resistors 84 and 86 is:

V.sub.C =I.sub.OUT2 R.sub.84 =mI.sub.M R.sub.84 =0, if V.sub.BE is greater than V.sub.REF (eq. 8) V.sub.C =I.sub.OUT2 R.sub.84 =mI.sub.M R.sub.84 =m(V.sub.REF -V.sub.BE)R.sub.84 /R.sub.74 =V.sub.REF -V.sub.BE, if V.sub.BE is less than V.sub.REF (eq. 9)

The correct voltage amounts shown in equations 6 and 7 are deemed compensation voltages at the output of first and second drive transistors 70 and 72. Assuming first transistor 72 produces V.sub.OH when transistor 88 is off, V.sub.OH can be defined as follows:

V.sub.OH =V.sub.DD -V.sub.BE -I.sub.OUT2 (R.sub.84) (eq. 10) which reduces to: V.sub.OH =V.sub.DD -V.sub.BE -(V.sub.REF -V.sub.BE) as set forth above, and which further reduces to: V.sub.OH =V.sub.DD -V.sub.REF if V.sub.BE is less than V.sub.REF

It is important to note that V.sub.OH is no longer dependent upon V.sub.BE and is solely dependent upon pre-defined power and reference voltages.

With regard to V.sub.OL, if transistor 70 produces V.sub.OL when transistor 90 is on, then the resulting V.sub.OL on output OUTA is as follows:

V.sub.OL =V.sub.DD -V.sub.BE -I.sub.DIFF (R.sub.86)-I.sub.OUT3 (R.sub.86)(eq. 11) which reduces to: V.sub.OL =V.sub.DD -(V.sub.REF -V.sub.BE) and which further reduces to: V.sub.OL =V.sub.DD -V.sub.REF -I.sub.DIFF (R.sub.86) if V.sub.BE is less than V.sub.REF.

From the above, it is noted that V.sub.OL, like V.sub.OH, is no longer dependent upon change in V.sub.BE. Instead, V.sub.OL depends only upon power supply voltage, a pre-defined and maintained reference voltage, and a pre-defined and maintained current source (I.sub.DIFF)

FIG. 5 illustrates a reference voltage V.sub.REF established so that correction starts near a mid-scale between the maximum and minimum V.sub.OH and V.sub.OL ranges. For example, if V.sub.OH is between V.sub.DD -0.83 and V.sub.DD -1.03, then V.sub.REF may be established to start correction at V.sub.DD -0.93. Likewise, if V.sub.OL maximum and minimum values are V.sub.DD -1.62 and V.sub.DD -1.86, then V.sub.REF may be selected so that I.sub.REF and I.sub.VBE are equal at the temperature where V.sub.OL is at V.sub.DD -1.74 (i.e., midscale).

As shown in FIGS. 5 and 6, if V.sub.BE decreases as a result of increase in temperature, the decrease will cause an increase in both V.sub.OH and V.sub.OL up until V.sub.BE reaches V.sub.REF. At temperatures beyond the point at which V.sub.BE reaches V.sub.REF, compensation occurs as denoted by the difference between lines 96 and 98. Line 96 illustrates no compensation, and line 98 indicates compensation. Line 98 thereby depicts the advantages of compensation and the benefit of maintaining V.sub.OH and V.sub.OL levels near the midscale between the maximum and minimum specified values regardless of changes in V.sub.BE brought about by change in temperature or process skews.

While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

1. An output driver circuit, comprising:

a first drive transistor having an emitter and a base; and

a first resistor coupled to the base of the first drive transistor, wherein said first resistor is adapted to receive a compensating current which produces a voltage through the first resistor, and wherein the voltage produced through the first resistor offsets changes in low and high output voltage levels caused by changes in the base-to-emitter forward bias voltage of the first drive transistor.

2. The output driver circuit as recited in claim 1, wherein the voltage produced through the first resistor is a correction portion of the voltage which is proportional to a reference voltage minus the base-to-emitter forward bias voltage, and wherein the reference voltage is at approximately a midscale voltage of the base-to-emitter forward bias voltage.

3. The output driver circuit as recited in claim 1, further comprising a sense correction circuit which includes a current source and a correction resistor, and wherein the correction circuit produces a scaled said compensating current as a difference between current produced by the current source and current forwarded through the correction resistor of which a voltage across the correction resistor substantially matches the first drive transistor base-to-emitter forward bias voltage.

4. The output driver circuit as recited in claim 3, wherein the scaled said compensating current is a factor m less than said compensating current.

5. The output driver circuit as recited in claim 4, wherein said m is a ratio of said correction resistor and said first resistor.

6. The output driver circuit as recited in claim 3, wherein the correction circuit further includes a current mirror coupled to mirror the scaled said compensating current to the compensating current.

7. The output driver circuit as recited in claim 1, further comprising:

a second drive transistor having an emitter and a base; and

a second resistor coupled to the base of the second drive transistor, wherein said second resistor is adapted to receive another compensating current which produces a voltage through the second resistor that varies in proportion to changes in the base-to-emitter forward bias voltage of the second drive transistor.

8. The output driver circuit as recited in claim 7, wherein the second drive transistor operably produces an output which is at a logic value that is a complement of a logic value produced at the output of the first drive transistor.

9. A transmitter, comprising an output driver which includes a pair of bipolar transistors that produce, during operation, a corresponding pair of differential output voltage values from the transmitter, each of said differential output voltage values transitioning between a pair of pre-defined voltage ranges and remaining within the predefined voltage ranges between transitions regardless of changes in a base-to-emitter forward bias voltage of the pair of bipolar transistors, wherein said transmitter is biased using a current source substantially invariant to said changes in the base-to-emitter forward bias voltage.

10. The transmitter as recited in claim 9, wherein changes in the base-to-emitter forward bias voltage result from changes in a temperature to which the pair of bipolar transistors is subjected.

11. The transmitter as recited in claim 10, wherein changes in the base-to-emitter forward bias voltage result from changes in fabrication parameters used to produce the pair of bipolar transistors.

12. The transmitter as recited in claim 9, wherein said base-to-emitter forward bias voltage is a voltage which, when exceeded, causes current to flow from the base to the emitter.

13. The transmitter as recited in claim 9, wherein said pair of differential output voltage values comprise a first voltage value and a second voltage value, and wherein said first voltage value is at a binary logic level dissimilar from the second voltage value.

14. A method of compensating for changes in a base-to-emitter forward bias voltage within a drive transistor, comprising:

continuously replicating the base-to-emitter forward bias voltage of the drive transistor whenever power is supplied to a circuit containing the drive transistor;

converting the replicated base-to-emitter forward bias voltage into a compensating current; and

forwarding the compensating current to a resistor coupled to the base of the drive transistor to counter said changes in the base-to-emitter forward bias voltage within the drive transistor.

15. The method as recited in claim 14, wherein said converting comprises:

presenting the replicated base-to-emitter forward bias voltage across a correcting resistor to produce a current;

subtracting from a current sourced amount from the current to produce a remainder current; and

scaling the remainder current into said compensating current.

16. The method as recited in claim 15, wherein said scaling comprises mirroring the remainder current to an increased quantity upon the resistor coupled to the base of the driver transistor.

17. The method as recited in claim 14, wherein said forwarding comprises presenting to the resistor a compensating current that is a function of the replicated base-to-emitter forward bias voltage and a pre-defined reference voltage.

18. The method as recited in claim 17, wherein said reference voltage is approximately at a midscale voltage output high level to which the drive transistor is defined to produce.

19. An output driver circuit, comprising:

a first drive transistor having source and a gate; and

a first resistor coupled to the gate of the first drive transistor, wherein said first resistor is adapted to receive a compensating current which produces a voltage through the first resistor that varies in proportion to changes in the gate-to-source voltage of the first drive transistor.