The present invention relates to a complex intermediate frequency mixer for frequency translating received complex intermediate frequency signals and to a receiver comprising the complex intermediate frequency mixer.
A known complex intermediate frequency (IF) based receiver architecture is depicted in
A further simplification can be made where only the frequency translation operations are considered. This is shown in
It is known that quadrature mixers suffer from gain and phase imbalance and that the performance in this respect is usually measured as image-rejection ratio (IRR). For a RF quadrature mixer the IRR is typically in the range of 30 to 40 dB. In the architecture described above, a finite image rejection will lead to that the lower side carrier effectively will leak into the upper side carrier and vice versa. Gain and phase imbalance will also be present in the IF filters and the complex mixers. The complex mixer will, however, have a much better IRR compared with the RF mixer as it operates with much lower frequencies.
Another scenario where even higher IRR might be required is when the first carrier has a first bandwidth and the second carrier has a second bandwidth, where the first bandwidth is narrower than the second bandwidth. The image frequency range for the second carrier will then be larger than the first carrier. This means that not only the first carrier may leak into the second carrier due to limited IRR but also other carriers present adjacent to the first carrier and within the image frequency range of the second carrier. The power of these signals may be much larger and therefore have a large impact on performance when interfering with the second carrier. This can only be mitigated by providing an improved IRR.
An object of the present invention is to reduce both gain and phase imbalances introduced by an RF mixer in a receiver.
According to an aspect of the invention, the object is achieved by a complex intermediate frequency mixer for frequency translating a received complex intermediate frequency, IF, signal, wherein the received complex IF signal comprises at least two frequency bands located at upper-side and lower-side of 0 Hz. The complex intermediate frequency mixer comprises a first-phase path input for receiving a first-phase signal of the received complex IF signal, a second-phase path input for receiving a second-phase signal of the received complex IF signal. Moreover, the complex IF mixer comprises a first mixer configured to be driven by a first-phase local oscillator signal and connected to the first-phase path input, the first mixer having a first mixer output,
a second mixer configured to be driven by a second-phase local oscillator signal and connected to the first-phase path input, the second mixer having a second mixer output, wherein the first-phase and second-phase local oscillator signals are in quadrature phase, a third mixer configured to be driven by the second-phase local oscillator signal and connected to the second-phase path input, the third mixer having a third mixer output, a fourth mixer configured to be driven by the first-phase local oscillator signal and connected to the second-phase path input, the fourth mixer having a fourth mixer output. The first mixer is configured to down-convert said first-phase signal of the received complex IF signal from said received frequency to a baseband frequency using the first-phase local oscillator signal to form a first signal to be output from the first mixer output. Furthermore, the second mixer is configured to down-convert said first-phase signal of the received complex IF signal from said received frequency to a baseband frequency using the second-phase local oscillator signal to form a second signal to be output from the second mixer output and the third mixer is configured to down-convert said second-phase signal of the received complex IF signal from said received frequency to a baseband frequency using the second-phase local oscillator signal to form a third signal to be output from the third mixer output. The fourth mixer is configured to down-convert said second-phase signal of the received complex IF signal from said received frequency to a baseband frequency using the first-phase local oscillator signal to form a fourth signal to be output from the fourth mixer output. The complex intermediate frequency mixer further comprises a first gain adjusting component, having a first gain input, a first gain output and a first gain control input for adjusting gain of the first gain adjusting component. The first gain input is connected to the first mixer output. The complex IF mixer further comprises a second gain adjusting component, having a second gain input, a second gain output and a second gain control input for adjusting gain of the second gain adjusting component. The second gain input is connected to the second mixer output. The complex IF mixer further comprises a third gain adjusting component, having a third gain input, a third gain output and a third gain control input for adjusting gain of the third gain adjusting component. The third gain input is connected to the third mixer output. The complex IF mixer further comprises a fourth gain adjusting component, having a fourth gain input, a fourth gain output and a fourth gain control input for adjusting gain of the fourth gain adjusting component. The fourth gain input is connected to the fourth mixer output. Moreover, the complex IF mixer comprises a first summing unit, having a first summing input and a first summing output. The first summing input is connected to the first gain output, the fourth gain output and the third mixer output negated. The complex IF mixer further comprises a second summing unit, having a second summing input and a second summing output. The second summing input is connected to the second gain output, the third gain output and the fourth mixer output. The first and second summing units are configured to output a first baseband complex signal of the received complex IF signal.
According to another aspect of the invention, the object is achieved by a receiver comprising a complex intermediate frequency mixer according to embodiments of the present invention, and a quadrature RF mixer for generating the complex intermediate frequency signal by down-conversion of a radio frequency signal.
Thanks to the fact that the first, second, third and fourth gain adjusting components are inserted into the signal paths at a location after signals has been down-converted to baseband frequency signals, it is possible to compensate for gain and phase imbalances introduced by the quadrature RF mixer by using only gain correction in the first-phase signal path and the second-phase signal path. In this manner, power consumption of the receiver may be reduced and the performance, in terms of reduced imbalances, may be increased. As a result, the above mentioned object is achieved. It may be noted that the first phase signal path may be the in-phase signal path and the second phase signal path may be the quadrature phase signal path of the complex IF mixer, or vice versa.
Advantageously, since the correction of gain and phase imbalances is performed where signal frequencies are in the base band, power consumption of the complex IF mixer may be reduced. In addition, the complex IF mixer may become more accurate, i.e. imbalances in the receiver and/or IF mixer are reduced.
In some embodiments of the complex intermediate frequency mixer according to the present invention, the complex intermediate frequency mixer may further comprise a third summing unit, having a third summing input and a third summing output. The third summing input is connected to the first gain output, the fourth gain output and the third mixer output. The complex IF mixer further comprises a fourth summing unit, having a fourth summing input and a fourth summing output. The fourth summing input is connected to the second gain output negated, the third gain output negated and the fourth mixer output. The third and fourth summing units are configured to output a second baseband complex signal of the received complex IF signal. Thereby, the complex IF mixer may process and output a second baseband complex signal of the received complex IF signal in addition to the first baseband complex signal. Consequently, the complex IF mixer may support dual carriers in the received complex IF signal.
In some embodiments of the complex intermediate frequency mixer according to the present invention, the complex intermediate frequency mixer may further comprise a fifth gain adjusting component, having a fifth gain input, a fifth gain output and a fifth gain control input. The fifth gain input is connected to the first mixer output. The complex IF mixer further comprises a sixth gain adjusting component, having a sixth gain input, a sixth gain output and a sixth gain control input. The sixth gain input is connected to the second mixer output. The complex IF mixer further comprises a seventh gain adjusting component, having a seventh gain input, a seventh gain output and a seventh gain control input. The seventh gain input is connected to the third mixer output. The complex IF mixer further comprises an eighth gain adjusting component, having an eighth gain input, an eighth gain output an eighth gain control input. The eighth gain input is connected to the fourth mixer output. The complex IF mixer further comprises a third summing unit, having a third summing input and a third summing output. The third summing input is connected to the first gain output, the sixth gain output and the seventh gain output. The complex IF mixer further comprises a fourth summing unit, having a fourth summing input and a fourth summing output. The fourth summing input is connected to the second gain output negated, the fifth gain output and the eighth gain output. The first summing input is connected to the third mixer output via the seventh gain adjusting component negated. The second summing input is connected to the fourth mixer output via the eighth gain adjusting component. The third and fourth summing units (S3, S4) are configured to output a second baseband complex signal of the received complex IF signal. Thanks to the addition of a fifth, sixth, seventh and eighth gain adjusting component, a symmetric architecture is obtained. An advantage with a symmetric architecture is that circuit implementation will exhibit lower signal path imbalance within itself compared to a non-symmetric architecture.
In some embodiments of the complex intermediate frequency mixer according to the present invention, the first summing input further is connected to the sixth gain output, the second summing input further is connected to the fifth gain output, the third summing input further is connected to the fourth gain output, and the fourth summing input further is connected to the third gain output negated.
In some embodiments of the complex intermediate frequency mixer according to the present invention, the first-phase is in-phase and second-phase is quadrature phase.
In some embodiments of the complex intermediate frequency mixer according to the present invention, the gain adjusting components are resistor/capacitor networks, voltage-to-current-converters or any signal converting network.
In some embodiments of the complex intermediate frequency mixer according to the present invention, the first and second gain adjusting components have been controlled to apply different gain to signals passing though the first and second gain adjusting components, respectively, and the third and fourth gain adjusting components have been controlled to apply different gain to signals passing though the third and fourth gain adjusting components, respectively. Since there is an imbalance introduced by irregularities in the gain adjusting components and the first, second, third and fourth mixers, it is advantageous to individually control the gain adjusting components, such as to correct for these imbalances as well.
Further features of, and advantages with, the present invention will become apparent when studying the appended claims and the following description. It is to be understood that different features of the present invention may be combined to create embodiments other than those described in the following, without departing from the scope of the present invention, as defined by the appended claims.
The various aspects of the invention, including its particular features and advantages, will be readily understood from the following detailed description and the accompanying drawings, in which:
Throughout the following description similar reference numerals have been used to denote similar elements, parts, items or features, when applicable. It may be noted that α1, α2, β1, β2, ε1, ε2, δ1 and δ2 have been used to denote elements α1, α2, β1, β2, ε1, ε2, δ1 and δ2 in the drawings. Furthermore, not all reference numeral have been inserted into all drawing in order to keep the drawings simple and easier to comprehend. See
In the conception of the present invention, the observations described below in conjunction with
Notably, in this model all imbalances are defined to occur in the I-path, i.e. the Q-path is defined as the reference. Consequently, for a real quadrature down-converter with incorrect gain in the Q path, the incorrect gain is referred to as a common gain error for the complete quadrature down-converter. In other words, as long as only gain and phase imbalances are considered this model does not impose any restrictions.
Moreover,
and gain of gain adjusting component δ should be equal to −tan(θ) in order to fully cancel imbalances (these relationships are referred to as statement A1). It is understood that I and Q paths may be interchanged.
Furthermore, the present inventors have realized that the architecture shown in
With reference to
So far only lower-side carrier support has been discussed in order to keep drawings and discussion less complex. In the following, dual-carrier support is to be discussed.
With reference to
As a consequence of statement A1 above, the value of δ may always be much smaller than unity as the initial IRR introduced by the RF down-converter is typically 30 dB or higher. This implies that the implementation of summing multiple mixer outputs as this “leak path” only will need to handle a very small signal (a few percent) as compared to the main signal paths (passing though gain adjusting components (denoted a) or directly from the third and fourth mixer, M3, M4). Thus, an advantage with this embodiment is that the power consumption associated with this signal path, i.e. the “leak path”, will be negligible.
Above, the first and second gain adjusting components (α, α1, α2) have been assumed to be adjusted to apply the same gain to a signal passing therethough and the third and fourth gain adjusting components (δ, δ1, δ2) have been assumed to be adjusted to apply the same gain to a signal passing therethrough. It shall be understood that it is not required that two or more gain adjusting components, such as any of the first, second, third and fourth gain adjusting component, are adjusted to apply the same gain to the signal passing through said two or more gain adjusting components.
Thus, in a further embodiment of the complex intermediate frequency mixer IFM, the first and second gain adjusting components have been controlled to apply different gain to signals passing though the first and second gain adjusting components, respectively, and the third and fourth gain adjusting components have been controlled to apply different gain to signals passing though the third and fourth gain adjusting components, respectively.
The gain of the gain adjusting components α and δ are each applied on two signal paths (as shown in
In the embodiments illustrated above, the first, second, third and fourth gain adjusting components have been placed after the IF mixer multiplying devices. In most cases, this will be a good option as they operate in portions of the signal paths where the frequency is low, i.e. baseband frequency. But it is readily understood that the gain adjusting components may be moved to facilitate a specific circuit implementation of the IF mixer architecture. It may though be advantageous to arrange the gain adjusting components such that gain of the signals are adjusted at base band frequency. For example, a gain adjusting component may be implemented in different ways, such as gain adjustable amplifiers, separate variable swing LO drivers driving individual mixers (M1-M4) to indirectly alter gain, tuneable passive networks, or weighted summing networks.
In embodiments of the present invention, it may be preferred that the design of the circuit is symmetric. For example, the embodiment of
The embodiments of
With reference to
The complexity of the architecture in
With reference to
The advantages of this architecture are easily seen. From the Figure, it may be seen that it is a symmetrical structure. This has, for example, the advantage that the first, second, third and fourth mixers are equally loaded. Thereby, it is possible to achieve a matched implementation. A matched implementation means that loads in the circuit are equally distributed among the components therein and aims to maximize the balance between the signal paths. Moreover, this embodiment uses a few number of summing unit inputs than the embodiment of
As an alternative, the first, second, third and fourth mixers and the corresponding gain adjusting components may be merged together, or the gain adjusting components and corresponding summing units may be merged together.
If only the part resulting in the lower-side carrier of the embodiment of
When implementing the complex IF mixer and the associated correction network is possible to consider each multiplying element to have a voltage output and the signal summing to be carried out by adding currents into a low impedance node, such as a virtual ground. A V-I conversion may be implemented by use of resistors or passive/active circuit blocks performing V-I conversion as gain adjusting components (tuneable resistors to incorporate control of gain).
The corresponding summation network, i.e. the summing units, for dual carrier reception architecture (again based on
A resistor-based summation network based on
For these circuit implementations where gain adjusting components are duplicated to facilitate multiple summations of currents it should be understood that the corresponding resistors actually could be set to different values, e.g. R1u does not have to be set to the same value as R11 as exemplified in the Figures. The set of the resistors for the lower-side carrier can be set partly or completely independently from the set of resistors for the upper-side carrier.
The above resistor-based solutions maybe generalized such that each resistor is actually representing any V-I conversion (passive and/or active) from the mixer outputs to the current summing nodes. A more generalized circuitry may for example be configured to provide the same impedance level as seen from the mixer outputs as well as the summing nodes. One example of such a circuit is a resistive Pi-network. Use of an active V-I conversion provides increased isolation between mixer outputs.
A further generalization includes the use of V-I conversion network including reactive components to provide a frequency selective summing. This can be used to implement part of the channel-selective filtering.
If the embodiment of
While the examples above primarily concern implementation in analog domain, it is understood that the embodiments described herein may be implemented in analog or digital domain or partitioned to include both domains. For example, the multiplying devices may be implemented in analog domain and signal summation in the digital domain. For this case, there will be no imbalance introduced in those parts that are implemented in the digital domain.
Even though the invention has been described with reference to specific exemplifying embodiments thereof, many different alterations, modifications and the like will become apparent for those skilled in the art. The described embodiments are therefore not intended to limit the scope of the invention, which is defined by the appended claims.
Number | Date | Country | Kind |
---|---|---|---|
10010555 | Sep 2010 | EP | regional |
Filing Document | Filing Date | Country | Kind | 371c Date |
---|---|---|---|---|
PCT/EP2011/066101 | 9/16/2011 | WO | 00 | 3/15/2013 |
Publishing Document | Publishing Date | Country | Kind |
---|---|---|---|
WO2012/038338 | 3/29/2012 | WO | A |
Number | Name | Date | Kind |
---|---|---|---|
5926500 | Odenwalder | Jul 1999 | A |
6330290 | Glas | Dec 2001 | B1 |
6833770 | Fukumoto et al. | Dec 2004 | B1 |
6892060 | Zheng | May 2005 | B2 |
7130604 | Wong et al. | Oct 2006 | B1 |
7248625 | Chien | Jul 2007 | B2 |
7301686 | Tanaka et al. | Nov 2007 | B2 |
20020160741 | Kim et al. | Oct 2002 | A1 |
20040137869 | Kim | Jul 2004 | A1 |
20060133548 | Oh et al. | Jun 2006 | A1 |
20090291649 | Fortier et al. | Nov 2009 | A1 |
20100067622 | Komaili et al. | Mar 2010 | A1 |
20110043277 | Sakamoto et al. | Feb 2011 | A1 |
20110159833 | Kenington | Jun 2011 | A1 |
Number | Date | Country |
---|---|---|
0305603 | Mar 1989 | EP |
1111803 | Jun 2001 | EP |
9914863 | Mar 1999 | WO |
0139364 | May 2001 | WO |
2005091493 | Sep 2005 | WO |
2009057051 | May 2009 | WO |
2012038336 | Mar 2012 | WO |
Entry |
---|
Der, L. and Razavi, B., “A 2GHz CMOS Image-Reject Receiver with LMS Calibration”, IEEE Journal of Solid-State Circuits, vol. 32, No. 2, Feb. 2003, pp. 167-175. |
Number | Date | Country | |
---|---|---|---|
20130177113 A1 | Jul 2013 | US |
Number | Date | Country | |
---|---|---|---|
61389331 | Oct 2010 | US |