Correlated noise canceller for high-speed ethernet receivers

Abstract

A method of operation in an ethernet receiver circuit is disclosed. The method comprises sampling an input signal to generate a sampled signal having a sampled noise component and a sampled data component. The sampled signal is sliced, and a slicer error determined based on the slicing of the sampled signal. A subsequently sampled noise component is filtered based on the slicer error.

Description

TECHNICAL FIELD

The disclosure herein relates to electronic communications, and more particularly to reducing correlated noise in high-speed wired electronic communications.

BACKGROUND

10 Gigabit Ethernet is an increasingly popular communication standard, with a nominal data rate of 10 Gbit/s. One form of 10 Gigabit Ethernet is IEEE 10 GBASE-T, used to provide 10 gigabit per second connections over unshielded or shielded twisted pair copper wires. The transmit wire-level modulation for 10 GBASE-T is a Tomlinson-Harashima Precoded (THP) version of pulse-amplitude modulation with 16 discrete levels (PAM-16), encoded in a two-dimensional constellation pattern known as 128-DSQ (Double Square QAM).

The receiver circuitry that receives and processes the transmitted 128DSQ symbols includes a slicer circuit that evaluates the received symbols and produces a preliminary decision of each data value. The decision generally involves taking the input data values at the PAM-16 levels, and assigning values based on the proximity of the received value to a particular PAM-16 level. The decision may be done sample by sample in which case the PAM-16 levels are used, or it can be done on pairs of samples in which case the 128-DSQ grid points are used. A forward error correction mechanism (like LDPC coding) may additionally help to make the right decision of mapping the received symbols to constellation points. This decision mechanism, which may include some level of error correction, is referred to as a slicer in this document. A communication system that is designed to meet performance targets in presence of background Gaussian noise may suffer from a burst of correlated noise, particularly in the form of radio frequency interference (RFI).

One proposal in the art to address RFI involves detecting common-mode noise, and utilizing the detected common-mode noise to filter the effects of RFI. In many cases this works well for its intended applications. However, some implementations utilize a fifth channel, with the common-mode representing the 5^th channel (in addition to the four data channels). Providing a fifth channel may cause an increase in package pincount for each transceiver chip. Thus, for some applications, it would be desirable to address the RFI problem in a high-speed ethernet system without the need to employ a 5^th channel.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

FIG. 1 illustrates a high-level transmitter/receiver channel architecture for the GBASE-T communication standard;

FIG. 2 illustrates one embodiment of a transceiver block diagram used in the architecture of FIG. 1;

FIG. 3 illustrates one embodiment of correlated noise canceller in a slicer circuit for use in the transceiver architecture of FIG. 2;

FIG. 4 illustrates one embodiment of an FIR (finite impulse response) implementation of the correlated noise canceller for use with the slicer circuit of FIG. 3;

FIG. 5 is a flow diagram of one embodiment of a method of cancelling correlated noise;

FIGS. 6A-6D represent simplified data histograms for one example of a PAM 2 signal at various locations in the circuit and architecture of FIGS. 2 and 3;

FIGS. 7A-7D represent slicer error signals in respective time and frequency domains for both pre-canceller and post canceller nodes of the slicer circuit of FIG. 3;

FIG. 8 is a graphical representation of the filter of FIG. 4 converging on a solution based on slicer error; and

FIG. 9 illustrates a further embodiment of a MIMO (multiple input multiple output) implementation of the correlated noise canceller in the slicer circuit of 4 receiver channels similar to FIG. 3.

DETAILED DESCRIPTION

Embodiments of a receiver circuit and associated methods of operation are disclosed. In one embodiment, a method of operation in a receiver circuit comprises sampling an input signal to generate a sampled signal having a sampled noise component and a sampled data component. The sampled signal is sliced, and a slicer error determined based on the slicing of the sampled signal. A subsequently sampled noise component is filtered based on the slicer error.

In a further embodiment, a receiver circuit is disclosed. The receiver circuit includes an input sampler to sample an input signal having a sampled noise component. A slicer circuit receives the sampled data and noise components to generate a slicer error signal. A feedback path including a correlated noise canceller is coupled to the slicer circuit to predict a subsequently sampled noise component for summation with a subsequently received input signal. By utilizing slicer error in a feedback context, correlated noise, such as RFI, may be filtered from sampled data to enhance signal fidelity.

FIG. 1 is a block diagram illustrating one embodiment of a communication system 100. The system includes a first transceiver integrated circuit (IC) or chip 102 and a second transceiver chip 104 that can communicate with each other. The first transceiver 102 includes “transceiver components” including one or more transmitters TX_A-TX_D and one or more receivers RX_A-RX_D. Similarly, the second transceiver 104 includes various transceiver components including one or more transmitters TX_E-TX_H and one or more receivers RX_E-RX_H. The transmitters TX_A-TX_H shown in FIG. 1 can be considered individual “transmitters,” as typically referenced herein, or can be considered individual transmitter channels which a transmitter block within the transceiver can independently transmit signals on. Similarly, receivers RX_A-RX_H can be considered individual “receivers,” as typically referenced herein, or can alternately be considered individual receiver channels which a receiver block within the transceiver can independently receive signals on. The transmitters and receivers are connected to one or more components (not shown) of a computer system, device, processor, or other “controller” associated with each respective transceiver which wants to communicate data over the communication network. For example, the transmitters receive data and control signals from the controller connected to the first transceiver 102 in order to send the data over the network to other transceivers and controllers, while the receivers receive data from other transceivers and controllers via the network in order to provide the data to the controller connected to the first transceiver 102.

The first transceiver chip 102 can communicate with the second transceiver chip 104 over one or more communication channels of a communication link 106. In one embodiment, such as that corresponding to the 10 GBASE-T Ethernet standard, four communication channels are provided on the communication link 106, each channel including a twisted pair cable. Thus, in that standard, there are four transmitters TX and four corresponding receivers RX provided in each of the transceivers 102 and 104, each transmitter associated with one of the local near-end receivers in the same transceiver, and each such transmitter/receiver pair dedicated to one channel used for duplex communication. A transmitter/receiver pair in the first transceiver 102 communicates across a channel of the link 106 to a far-end transmitter/receiver pair in the second transceiver 104. A transmitter TX and a receiver RX that are connected to the same channel/link, or two transceivers connected by the communication link 106, are considered “link partners.”

An interface 108 can be provided in the first transceiver chip 102 and an interface 110 can be provided in the second transceiver chip 104 to allow data transmissions between the transceivers to be routed to the appropriate transceiver blocks. For example, the interfaces 108 and 110 can include transformers, and circuitry used for directing signals or data (alternatively, some or all circuitry can be included in other components, such as transmitters TX and receivers RX).

In one example, from the point of view of the first transceiver chip 102, data transmissions during normal operation from a local transmitter TX are provided to the interface 108, which outputs the data on a corresponding channel of the communication link 106. The data is received by the link partner, the second transceiver chip 104. The interface 110 of the transceiver 104 provides the received data to its receiver RX connected to that same channel. Furthermore, due to noise effects such as near-end crosstalk and echo, the data transmitted by the transmitters is also received by the near-end receivers in the same transceiver. Filters can be used to filter out this noise so that the receivers receive only data from other transceivers. In some embodiments, the transceivers 102 and 104 are asymmetric, such that data transmitted by a local transmitter has no dependence or relation with data being received by the corresponding local receiver.

FIG. 2 is a block diagram illustrating one example of a transceiver 200. This example is suitable for a 10 GBASE-T standard, but other different configurations and types of transceiver components can be used in other embodiments for 10 GBASE-T or for other, different communication standards. For explanatory purposes, the example shown in FIG. 2 illustrates a single transmitter path/channel and a single receiver path/channel for data. Multiple such paths/channels are provided in embodiments having multiple channels, e.g. four of the transmitter paths and the receiver data paths shown in FIG. 2 are used in the GBASE-T standard.

One or more processors 202 are typically included in transceiver 200, or connected to the transceiver, to control various operations for the transceiver components. Furthermore, additional hardware and/or software/firmware can be provided to implement the components themselves and can include processor functionality.

In the transmitter portion TX (denoted in phantom) of the transceiver 200, an encoder/decoder 204 can be used to encode data desired to be transmitted in a particular desired format or standard, followed by a scrambler 206 for self-synchronized scrambling of the data to be transmitted, providing clock transitions, a statistically random power spectrum for EMI (electromagnetic interference) control, equalizer convergence, etc. A low density parity check (LDPC) encoder 208 encodes the data according to the parity check for error correction. A 128DSQ mapper 210 (or other type of mapper) then can use a coset-partitioned constellation to map the data to symbols, and each 128-DSQ symbol is transmitted using two back-to-back PAM-16 signals (Pulse Amplitude Modulation, 16 levels). A Tomlinson-Harashima Precoding (THP) precoder 212 can then adjust the signal to assist the far-end receiver in performing signal equalization. An analog front end (AFE) for the transmitter can include a digital-to-analog converter (DAC) and driver block 214 which converts the data to analog form for transmission and transmits the data via the hybrid coupler and transformer block 216 to the channel 217.

Different embodiments can implement the hybrid and transformer block 217 differently. For example, in some embodiments the transformers may be separately connected directly to the communication link, and the hybrid coupler is connected between the transformers and the rest of the transceiver components. Other embodiments may provide transformers between hybrid and the other transceiver components, or another configuration.

In a receiver portion RX (in phantom) of the transceiver 200, data is received at the hybrid coupler 216. As noted above, four data communication channels are used in a 10GBASE-T embodiment (other amounts of channels can be used in other embodiments), and are sent to an analog front end (AFE) for the receiver which can include a variable gain amplifier (VGA) and filter 218 for filtering, and an analog-to-digital converter (ADC) 220. An equalizer circuit 222 receives sampled signals from the ADC and can include one or more equalizers to reduce inter-symbol interference (ISI) effects on the data. The output of the equalizer circuit 222 is summed with the outputs of a plurality of filters 240, 242, and 244 at adder 224, and the output of the adder provided to a slicer circuit 306. Further details regarding an embodiment of the slicer circuit are shown in FIGS. 3 and 4, and described below. The signal can then be provided to a DSQ128 decoder 228, which outputs decoded data to a framer 230 that extracts frames from the received data and provides the frames to an LDPC decoder 232. The LDPC decoder generally performs an error-correction process on the data. The data can then be provided to a descrambler 234 which outputs de-scrambled data to the encoder/decoder 204 for decoding. The decoded signals are then fed to a connected computer system, processor, or other device.

The filters 240, 242 and 244 are used to reduce echo and crosstalk (NEXT and FEXT) noise which may be introduced in the transmission and reception of data over one or more of the four communication channels. Filters can include an Echo canceller 240, a Near End Crosstalk (NEXT) canceller 242, and a Far End Crosstalk (FEXT) canceller 244. The filters cancel out the effect of signal echo and crosstalk from adjacent lines to achieve an acceptable bit error rate. The output of the THP precoder 212 in the transmitter portion of the transceiver 200 is provided to the Echo canceller 240 and the NEXT canceller 242, which calculate the values for cancellation of echo and NEXT and output these values to the adder 224. Similarly, the output of ADC 220 is provided to the FEXT canceller 244, which calculates the values for cancellation of FEXT and outputs the values to the adder 224. The digital values of echo and crosstalk calculated by the filter are subtracted from the incoming noisy analog data (digitized by ADC 220) by adder 224 to provide received data on each channel with reduced noise. As explained in further detail below, each of the filters includes an input to accept a slicer error value fed back from the slicer circuit 226. As explained below, the slicer error feedback enables a significant reduction in correlated noise without the need for a common-mode fifth channel.

FIG. 3 illustrates one embodiment of a slicer circuit 226 for use in the transceiver 200 of FIG. 2. The various echo, NEXT and FEXT filters 240, 242, and 244 from FIG. 2 are also shown for context purposes. The slicer circuit 226 includes an input node, at 302, that feeds an input adder 304. The adder, in turn, couples to a slicer 306. An output adder 308 receives the input signal to the slicer, and the output from the slicer to generate a slicer error signal (“slicer error”).

Further referring to FIG. 3, the slicer error signal is fed to a correlated noise canceller 310, where a filtered output is generated based on the slicer error, and fed back along a feedback path 312 to the input adder 304. The slicer error signal is also fed as an input to the echo canceller 240, the NEXT canceller 242, the FEXT canceller 244 and the equalizer 222. An additional summer 314 receives sampled data from the input node 302 and the output of the slicer circuit, at 316, and produces a second error signal fed to the correlated noise canceller 310.

In one embodiment, the correlated noise canceller 310 is realized as an adaptive filter that continually adapts, and more particularly a finite impulse response (FIR) filter. While the structure and operation of FIR filters are generally well-known to those skilled in the art, FIG. 4 illustrates a high-level implementation that includes a plurality of delay elements D0-Dn, for delaying respective data samples. A number of taps T0-Tn corresponding to the delay elements are respectively coupled to delay output nodes. The taps receive respective weights or coefficients h0-hn+1 that represent factors applied to a sequence of data samples. A summing circuit 402 receives weighted samples, averages them, and outputs a filtered value.

The length of the adaptive filter, or number of samples to evaluate and average to determine an output, is selectable for a user depending on the application involved. Implications involving amplifier gain may warrant the use of only one sample (weighted with a gain or tap value of 1) or many samples (weighted with a corresponding number of low-gain values). Generally, however, the longer the filter, the less correlation in the noise, and correspondingly less predictability. As discussed below, high gain values may have a tendency to promote error propagation, and possibly cause filter non-convergence.

A variety of algorithms may be employed to derive values for the selected number of tap weights, or coefficients. Least mean squares (LMS) and minimum mean square error are 2 of well known algorithms. One variant to adapt the coefficients is to “regularize” the filter by utilizing a least squares algorithm, as is well-known in the art. As an example, one might use the least squares algorithm to find a solution that minimizes gain for the coefficients. Another possible algorithm to employ is the least mean squares method, which provides a leakage term that allows each adaptation step to “leak” a little bit away from the result so that the output doesn't grow too large too fast (thus, avoiding a high gain situation). In a further embodiment, the taps may have programmable saturation levels to maximize tap gain levels.

In operation, the slicer circuit structure described above takes advantage of the fact that correlated noise, such as that typically associated with RFI, may be predictable in many cases based on historical statistics. Thus, by sampling correlated noise over time, and assuming that the sampled noise is correlated between samples, evaluating the history of the noise may be a reliable predictor of future noise. Further, by predicting the future noise, it can be filtered/canceled from a current sample to enhance the signal fidelity of the system. Note that the use of the term “cancellation” is not meant to require a complete cancellation of a target signal, but rather a significant mitigation or reduction of the target signal that provides the advantages noted herein.

FIG. 5 illustrates a method of operation, generally designated 500, of the circuitry involving the slicer circuit of FIG. 3. Transmitted data symbols in the form of multi-PAM signals are transmitted by the transmitter circuitry TXA-TXD of a first transceiver chip 102 (FIG. 1) and received by the corresponding receiver circuitry of another chip 104. FIG. 6A illustrates a histogram representing PAM-2 signals at two signaling levels (approximately +9 and −9 along the x-axis) from a transmit side of a signaling system (for ease of illustration and explanation, it is assumed that PAM-2 signals are being transmitted rather than PAM-16 signals). The hybrid coupler 216 (FIG. 2) receives the symbols and passes them to the VGA and filter 218 and subsequently the ADC 220. A histogram representing the received signals with correlated sinusoidal noise is shown in FIG. 6B. The ADC 220 then samples the received input signals, at step 502, which are passed to the slicer circuit 226 for slicing, at step 504. The slicing involves receiving the sampled signals, at 506, equalizing and cancelling the echo/NEXT/FEXT components, at step 507, then assigning data values based on the proximity of the received values to a particular PAM level, or after forward error correction, at step 508. Once the slicing for a particular sample is carried out, the error between the slicer input and the slicer output is detected, at step 510.

Further referring to FIG. 5, following detection of the slicer error, a series of steps are carried out that result in feeding back a cancellation signal to various circuit components based on the slicer error, at step 512. The sub-steps involve first presenting the slicer error to the correlation noise canceller, at step 514. FIG. 6C illustrates a histogram of slicer error in the presence of sinusoidal noise as presented to the canceller, while FIGS. 7A and 7B illustrate the slicer error in respective time and frequency domains. In one embodiment, as explained above, the canceller is in the form of an adaptive filter that aggregates a plurality of error samples, at step 516. The error samples are acted upon within the filter with weightings applied and averaging carried out as described above. The filter generates a filtered output that represents a noise sample prediction, at step 518, to offset an expected subsequent noise sample. The predicted noise sample is then fed back to the summing node 304 to iteratively assist in cancelling the RFI noise. FIG. 6D illustrates a Gaussian histogram that shows the resultant noise after reducing the RFI through application of the predicted noise component, while FIGS. 7C and 7D illustrate the resulting signal output from the correlated noise canceller in respective time and frequency domains.

The error samples are also fed to the echo filter 240, NEXT filter 242, FEXT filter 244 and equalization circuitry 222 to provide the required information for their adaptation. As the transceiver 200 continues to operate, the correlated noise canceller continues to iteratively adapt its error sample predictions in a manner that eventually converges to a solution. FIG. 8 illustrates such a convergence. Thus, the correlated noise canceller 310 provides a way for the transceiver circuit 200 to effectively filter the effects of RFI without necessarily needing an additional channel to, for example, provide a common mode signal indicative of RFI noise for cancelling by an adaptive filter.

FIG. 9 illustrates a high-level embodiment of a correlated noise cancellation architecture similar to that discussed above, but that operates across multiple receiver channels. The architecture includes a plurality of channels C1-C4 that correspond to the twisted wire pairs 106 of FIG. 1. In one embodiment, the channels cross-couple slicer error in a multiple-input-multiple-output (MIMO) fashion to cancel the effects of RFI. Generally, each channel may include structure as described above with respect to FIGS. 2-4, but additionally involve cross-channel summing nodes S1-S4 that each receive the slicer error signals from the other channels through respective filters such as that shown at 902. In this way, slicer error for current and previous samples from the other channels may be used in the adaptation for a particular channel to more accurately determine the predicted noise samples for that channel.

In other embodiments, the MIMO architecture described above may be simplified by aggregating slicer error from all the channels to less than all of the channels. In one embodiment, slicer error signals from three channels are summed at a fourth channel only. One way to prioritize which channel(s) will receive the slicer error (from the other channels) is to determine the channel(s) with the highest SNR. This choice will minimize the noise that is fed back by the correlated noise cancellers. Another way to prioritize is to choose a channel with the strongest RFI signal. In this case the correlated noise canceller will create a weaker feedback path that reduces the noise that is injected back and also it reduces the chance of error propagation. Depending on the application, tradeoffs in gain versus SNR may need to be made to optimize circuit operation.

Those skilled in the art will appreciate the benefits and advantages afforded by the transceiver slicer circuitry and method described above. By minimizing the effects of RFI with the correlated noise canceller, a fifth channel may be avoided. This minimizes the number of package connections for each transceiver chip. Moreover, utilizing a correlated noise canceller provides a straightforward implementation scheme that provides cancellation even without the most recent samples.

In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like may be different from those described above in alternative embodiments. Also, the interconnection between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single conductor signal links may alternatively be multi-conductor signal links. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. Component circuitry within integrated circuit devices may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology or any other technology in which logical and analog circuits may be implemented. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “deasserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted. Additionally, the prefix symbol “I” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ‘ <signal name>’) is also used to indicate an active low signal. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Integrated circuit device “programming” may include, for example and without limitation, loading a control value into a register or other storage circuit within the device in response to a host instruction and thus controlling an operational aspect of the device, establishing a device configuration or controlling an operational aspect of the device through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and/or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The term “exemplary” is used to express an example, not a preference or requirement.

While the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method of operation in an Ethernet receiver circuit comprising: for each of a plurality of channels, sampling an input live Ethernet data signal to generate a sampled signal having a sampled correlated noise component caused by an interfering signal, and a sampled data component, the sampled correlated noise component being correlated to a previously sampled correlated noise component;equalizing the sampled signal to generate an equalized signal;summing, at a summer, the equalized signal with compensation signals from respective near-end crosstalk (NEXT) and far-end crosstalk (FEXT) filters to generate a summed signal;feeding the summed signal as an input to a slicer circuit;slicing the summed signal with the slicer circuit;determining a slicer error based on a difference between the summed signal and a signal produced at the output of the slicer circuit;feeding the slicer error to a correlated noise filter;filtering the slice error to generated a correlated noise compensation signal for feeding to the summer to cancel at least a portion of the interfering signal;wherein the summing includes summing the equalized signal with respective correlated noise compensation signals fed from the other of the plurality of channels.

2. The method according to claim 1 wherein the filtering comprises adaptively filtering.

3. The method according to claim 1 wherein the filtering comprises: predicting a subsequent sampled noise component based on the slicer error; andsubtracting the predicted subsequent sampled noise component from a subsequently sampled signal.

4. The method according to claim 3 wherein the subsequent sampled noise component includes evaluating a plurality of previous samples.

5. The method according to claim 4 wherein the plurality of previous samples are each weighted differently in the evaluating.

6. An Ethernet receiver circuit comprising: a plurality of channels, each channel including an input sampler to sample an input live Ethernet data signal having a sampled correlated noise component caused by an interfering signal, the sampled correlated noise component being correlated to a previously sampled correlated noise component;an equalizer to equalize the sampled noise component;a summer to sum the equalized sampled noise component with compensation signals from respective NEXT and FEXT filters and generate a summed signal;a slicer circuit to receive the summed signal to generate a slicer error signal, the slicer error signal based on a difference between the summed signal and a signal produced at the output of the slicer circuit;a feedback path including a correlated noise canceller coupled to the slicer circuit to receive the slicer error signal and predict a subsequently sampled noise component for summation with a subsequently received input signal to generate a correlated noise compensation signal to cancel at least a portion of the interfering signal:wherein the summer further receives respective correlated noise compensation signals fed from the other of the plurality of channels.

7. The Ethernet receiver circuit according to claim 6 wherein the noise component is based on a sinusoidal noise source.

8. The Ethernet receiver circuit according to claim 7 wherein the sinusoidal noise source comprises radio frequency interference (RFI).

9. The Ethernet receiver circuit according to claim 6 wherein the correlated noise canceller comprises an adaptive filter.

10. The Ethernet receiver circuit according to claim 9 wherein the predicted noise component is based on one or more previous noise samples.

11. The Ethernet receiver circuit according to claim 10 wherein each noise sample is associated with a tap weighting.

12. The Ethernet receiver circuit according to claim 9 wherein the adaptive filter includes a selectable number of taps.

13. The Ethernet receiver circuit according to claim 12 wherein the adaptive filter converges on a solution based upon a leakage term-based algorithm.

14. The Ethernet receiver circuit according to claim 12 wherein the adaptive filter converges on a solution based upon a regularization-based algorithm.

15. The Ethernet receiver circuit according to claim 6 embodied as a 10GBASE-T transceiver circuit.