A phase-locked loop (PLL) is an electrical circuit that generates an output dock that is phase-locked to an input reference dock. PLLs are used for a variety of purposes including, for example, communication systems, computers, and the like. PLLs can be digital PLLS (DPLL) or analog PLL (APLL).
In at least one example, a circuit includes a selection circuit coupled to receive a plurality of reference clocks. The selection circuit is controlled by a control signal to output one of the plurality of reference clocks. A phase-locked loop is coupled to an output of the selection circuit and uses the output reference clock from the selection circuit for phase locking an output clock generated by the phase-locked loop. A plurality of reference clock window detector circuits is included. Each reference clock window detector circuit is coupled to receive a separate one of the plurality of reference clocks. Each reference clock window detector circuit asserts an error signal responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window. Further, each reference clock window detector circuit asserts the error signal responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window.
In another example, a method includes detecting a first error condition corresponding to a first edge of a reference clock occurring before expiration of a first counter, detecting a second error condition corresponding to a second edge of the reference clock occurring after expiration of a second counter, asserting an error signal responsive to detection of the first error condition, and asserting the error signal responsive to detection of the second error condition.
For a detailed description of various examples, reference will now be made to the accompanying drawings in which:
As noted above, a PLL phase locks an output clock to a reference clock. The reference clock should have a constant frequency and thus constant period. However, it is possible that the period can vary from cycle to cycle of a reference clock. Jitter or other effects may cause a variation in the period of a reference clock. A PLL should detect a corrupted reference clock as quickly as possible to eliminate phase perturbation on the PLL's output clock.
Some PLLs include a missing clock detection capability as illustrated in
Some PLL systems include a late clock detection capability in which a valid window 70 is implemented. If the next clock edge is detected before the current valid window 70 ends (as illustrated at 73), then that clock cycle is deemed to be valid. However, if the valid window 70 ends before the next reference clock edge (e.g., edge 75) occurs, a missing clock detect signal 80 is generated and the PLL system responds in a suitable manner.
While generally satisfactory for detecting a late or missing clock, early clocks cannot be detected with this scheme. An early clock (i.e., a clock edge that occurs substantially before it should have occurred) can also impair the performance of a PLL. The examples described herein advantageously detect both early and late clocks.
Each REFCLK_1 through REFCLK_n is provided to a separate reference clock window detector 210. REFCLK_1 is provided to reference clock window detector 210a and REFCLK_n is provided to reference clock window detector 210n (reference clock window detector circuits 210a through 210n collectively referred to as reference clock window detector circuits 210). Each of the reference clock window detector circuits 210 asserts an error signal (ERROR) to the FSM 220 to indicate whether an early or late error condition has been detected for the corresponding reference clock. For example, ERROR asserted high indicates an early or late error condition and ERROR being low indicates absence of either kind of early/late error, or vice versa. Each reference clock window detector 210 asserts ERROR responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window. Each reference clock window detector circuit also asserts ERROR responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window. Thus, two separate time windows are implemented—one for the detection of an erroneously early reference clock and the other for the detection of an erroneously late reference clock. In this example, ERROR being asserted to the FSM 220 does not distinguish as to which type of error condition has occurred—either way a reference clock error has occurred and the FSM 220 will take corrective action.
If one of REFCLK_1 through REFCLK_n is currently being selected through multiplexer 202 to provide REFCLK_IN to the PLL 204 and the reference clock window detector 210 for that particular reference clock detects an early or late condition, that reference clock window detector asserts is ERROR signal to the FSM 220. In response, the FSM 220 monitors the ERROR signals from the other reference clock window detectors 210, selects another reference clock (assuming the corresponding reference clock window detector has not also actively asserted its ERROR signal), and asserts the control signal 222 to the multiplexer 202 to switch to a different reference clock. The selection of which reference clock to use, to the extent multiple other reference clocks are provided to the multiplexer 202, is preconfigured into the FSM logic in some examples.
Assertion of load input (e.g., a rising edge of REFCLK_IN) causes each counter 310, 350 to reset itself to an initial count value and to begin counting pulse of the sampling clock. The initial count value is set to be different between the two counters so as to implement a late window that is longer than an early window. The count value for the early counter 310 is shown as “n” and for the late counter 350 is shown a “m”. The value m is larger than the value n in this example.
In the example of
The Q outputs of flip-flops 315 and 355 are provided to the data inputs of flips-flops 320 and 360, respectively. The sampling clock is used to clock flip-flop 360. Flip-flop 320 is clocked by the Q output (labeled as Q2) of flip-flop 330. The Q bar (QB) output of flip-flop 320 is a signal labeled as EARLY FLAG. Flip-flop 330 is clocked by REFCLK_x. The Q output of flip-flop 360 is a signal labeled as LATE FLAG. Absent an early reference clock, the QB output (EARLY FLAG) of flip-flop 320 is logic low. Similarly, absent a late reference clock, the Q output (LATE FLAG) of flip-flop 360 also is logic low. The data input of flip-flop 330 is tied to a logic high. The Q output of flip-flop 330 transitions from low to high upon a rising edge of REFCLK_X. Flip-flop 330 is used to introduce a small time delay so that a subsequent edge of REFCLK_x is used to clock flip-flop 330 from the edge of REFCLK_x (REFCLK_IN) that resets the early counter 310.
OR gate 380 is coupled to the QB output of flip-flop 320 and the Q output of flip-flop 360 to logically OR together EARLY FLAG and LATE FLAG to generate an ERROR signal. Flip-flop 385 functions as a latch to hold ERROR on its Q output to the FSM 220. The ERROR signal to the FSM 220 can be either the output of OR gate 380 or the latched output from flip-flop 385.
The following discussion explains the operation of the early window to detect an early reference clock. For the early reference clock detection, while early counter 310 is counting down, but before its terminal count is reached, the output 311 of the early counter is 0 and the Q output of flip-flop 315 is 0. Flip-flop 320 has been preset by the output of inverter 322 (via FSM 220) and thus its QB output (EARLY FLAG) is logic 0. Upon occurrence of an early reference clock (i.e., a reference clock rising edge that occurs after the early counter 310 has been reset and is counting down but before the early counter 310 reaches 0), flip-flop 330 is clocked thereby forcing its Q output to transition from low to high and clocking flip-flop 320. Flip-flop 320 at this point is clocked with its D input being 0 which then causes EARLY FLAG to transition to a high logic level and ERROR is asserted high via OR gate 380.
The following discussion explains the operation of the late window to detect a late reference clock. For the late reference clock detection, while late counter 350 is counting down, but before its terminal count is reached, the output 351 of the late counter is 0 and the Q output of flip-flop 315 is 0. Flip-flop 360 has been cleared by the FSM 220, and thus its Q output (LATE FLAG) is logic 0. Once the late counter 350 counts down to 0, flip-flop 355 is then clocked thereby forcing the Q output of flip-flop 355 to a logic high level, which in turn forces the Q output of flip-flop 360 (LATE) FLAG to become logic high upon the next rising edge of the sampling clock. OR gate 380 then causes its ERROR output signal to become logic high in response to LATE FLAG being high. Had the next rising edge of REFCLK_x occurred before the late counter 350 expired, the late counter 350 would have been reset by the REFCLK_x edge and not permitted to count down to 0.
The reference-based clear circuit 362 generates a clear signal to clear flip-flops 330, 315 and 355 responsive to REFCLK_IN. In one example, the reference-based clear circuit 362 asserts the clear signal high upon a rising edge of REFCLK_IN and de-asserts the clear signal upon the next sampling clock rising edge.
EARLY FLAG remains logic low when Q2 is asserted high as long as Q1 is logic high. The rising edge 401 occurs after the expiration of the early window which ends at 405, and thus the EARLY FLAG remains at a logic 0 level as shown at 420 because Q1 is high when Q2 becomes high. EARLY FLAG is asserted high at 430 because Q1 is low when Q2 experiences rising edge 425. As soon as EARLY FLAG is asserted high, ERROR is also asserted high at 440 from ORE gate 380 and/or from latching flip-flop 385.
Upon each rising edge of REFCLK_IN, both counters 310, 350 are reset. Late counter 350 is reset and before it reaches zero, and thus LCOUT remains low as shown. With LCOUT being low, the LATE FLAG remains low as well.
Waveform 600 shows multiple cycles of an ideal reference clock. Waveform 602 shows an example of reference clock in which one of the edges 603 occurs prematurely. Waveform 602 shows an example of reference clock in which one of the edges 605 occurs too late. Edge 603 occurs before the valid time window 630 starts, a condition which causes EARLY FLAG to be asserted high (640). Edge 605 occurs after the expiration of the valid time window 630 starts, a condition which causes LATE FLAG to be asserted high (650).
In this description, the term “couple” or “couples” means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, X may be a function of Y and any number of other factors.
Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
This application claims priority to U.S. Provisional Application No. 62/640,603, filed Mar. 9, 2018, which is hereby incorporated by reference.
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