Patent Application
20050071529
Network Processing Engines (NPEs) typically contain hardware support for a relatively limited number of first-in-first-out (FIFO) memories. It is often the case, however, that the software running on NPEs could benefit from more FIFOs.
While it is possible to implement additional FIFOs in software, there are problems with this approach. A FIFO typically has separate reader and writer contexts, and a software FIFO typically must maintain a read pointer and a write pointer. However, it is generally infeasible to maintain an explicit count of the amount of data in each FIFO because the count must be written by both the reader after reading data, and the writer after writing data, which creates problems if the reader and writer are running at different priorities, as is often the case, and one is interrupted by the other. Such a count would be useful, however, since the reader typically must check whether the FIFO is empty before reading from it, and the writer typically must check whether the FIFO is full before writing to it. Without an explicit count, the reader and writer will generally need to compare the read and write pointers to determine the empty/full status of the FIFO, and this comparison can consume several cycles of execution time. Moreover, even if it is determined that the read and write pointers are equal, this can indicate either that the FIFO is full or that it is empty, so additional processing is generally needed to make the correct determination, which further degrades performance.
In the accompanying drawings, like reference numerals designate like structural elements.
Systems and methods are disclosed for using counting semaphores in network processing engines. The counting semaphores can be used to implement software FIFOs and/or to provide other functionality. For example, counting semaphores can be implemented in network processing engines to provide support for software FIFOs. The logic needed to support these FIFOs is believed to be less than that needed to support additional hardware FIFOs, especially as the number of additional FIFOs is increased. Thus, embodiments described herein enable network processing engines to utilize more FIFOs at less cost. The counting semaphores that are used in the embodiment can also, or alternatively, be used to provide NPEs with additional resource-locking and signaling functionality.
It should be appreciated that the concepts and methodologies presented herein can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium such as a computer readable storage medium or a computer network wherein program instructions are sent over optical or electronic communication lines. Several inventive embodiments are described below.
In one embodiment, a method is provided for implementing a software FIFO in a network processing engine. When a request to write data to a FIFO is received, the value of a counting semaphore is compared with a predefined maximum value in order to determine whether the FIFO is full. If the value of the counting semaphore is less than the predefined maximum value, the counting semaphore is incremented, and the data is written to the FIFO. If a request to read data from the FIFO is received, the value of the counting semaphore is compared with a predefined minimum value in order to determine whether the FIFO is empty. If the value of the counting semaphore is greater than the predefined minimum value, then the counting semaphore is decremented and data is read from the FIFO.
In another embodiment, a network processing engine is provided. The network processing engine contains one or more coprocessors, memory, a counting semaphore, signaling logic for signaling the status of a FIFO, and computer code operable to implement a FIFO using the counting semaphore and the signal generation logic. In one embodiment, the signal generation logic is operable to generate a signal indicating whether or not the FIFO is full or empty, and whether the FIFO contains more than a first predefined amount of data or less than a second predefined amount of data.
In yet another embodiment, a method for implementing a software FIFO in a network processing engine is provided that makes use of a counting semaphore to maintain a count of the amount of data in the FIFO.
In yet another embodiment, a signaling method is provided that is suitable for performance by a network processing engine. A counting semaphore is maintained, the value of which can be atomically incremented and decremented. The semaphore can be incremented in response to a first action taken by a first process—such as writing data to a FIFO—and a second process can take a second action based on the value of the semaphore—such as reading data from the FIFO. In some embodiments, additional signaling functionality can be provided by a set of flags, which may, for example, be set to indicate that a FIFO is full, empty, almost full, almost empty, and/or the like.
These and other features and advantages will be presented in more detail in the following detailed description and the accompanying figures which illustrate by way of example the principles presented herein. The following description is presented to enable any person skilled in the art to make and use the inventive body of work. Descriptions of specific embodiments and applications are provided only as examples and various modifications will be readily apparent to those skilled in the art. The general principles defined herein may be applied to other embodiments and applications. For example, while several embodiments are described in the context of network processing engines, it will be appreciated that the systems and methods described herein could be implemented in other contexts as well. Thus, the concepts and methodologies presented herein are to be accorded the widest scope, encompassing numerous alternatives, modifications, and equivalents consistent with the principles and features disclosed herein. For purpose of clarity, details relating to technical material that is known in the related fields have not been described in detail so as not to unnecessarily obscure the concepts and methodologies presented herein.
A Network Processing Engine (NPE) often contains numerous coprocessors that each perform specialized functions to assist the NPE firmware in data processing. For example, NPEs such as those contained in the IXP425, manufactured by Intel Corporation of Santa Clara, Calif., include a condition coprocessor that contains, among other features, a set of mutually exclusive (mutex) semaphores. These semaphores provide a simple and efficient mechanism for controlling access to a resource (sometimes referred to as resource locking), as well as signaling between NPE software contexts or threads.
Each mutex semaphore consists of a single bit, whose state can be one of two values: set or clear. The mutex semaphore hardware supports two basic operations for each mutex: TestAndSet and TestAndClear. Each of these operations is atomic, meaning that it cannot be interrupted by other operations (e.g., is executed in a single cycle). Thus, a context can effectively read-and-set a mutex or read-and-clear a mutex without concern for being preempted in the middle by a higher-priority context. In addition, the state (set or clear) can be wired to signal other contexts. For example, a context could “wake up” when a particular mutex is set or cleared.
Conventional mutex semaphores are often used to protect the use of a resource or to coordinate the execution of critical code sections in multi-threaded environments. For example, each thread may wish to modify the value of a shared variable or to make use of the same resource, and thus it might be important to ensure that only one thread can execute its critical section at a time. There are a variety of ways to implement mutex semaphores to ensure their atomicity, including in hardware (e.g., using a J-K flip flop) and/or in software (e.g., by disabling interrupts to ensure that only one process can modify the semaphore at a time).
Embodiments described herein extend the conventional mutex semaphore functionality. The one-bit state of the mutex semaphores is replaced with an N-bit count, where N is an arbitrary number greater than 1. The TestAndSet and TestAndClear operations are replaced with ReadAndIncrement and ReadAndDecrement operations. These two operations may be atomic, depending on the specific implementation in hardware.
The ReadAndIncrement operation performs a read of the semaphore count, and then increments the count by one. The ReadAndDecrement operation performs a read of the semaphore count, and then decrements the count by one. If N equals 1, the counting semaphore functionality is basically equivalent to the mutex semaphore functionality described above.
In various embodiments, further signaling and condition functionality is provided by the addition of three predefined, configuration values: Maximum Value, High Watermark, and Low Watermark. Each of these values may be sized similarly to the semaphore count (e.g., N bits). These configuration values can be used in conjunction with the semaphore count to generate four single-bit condition signals: Empty, Nearly Empty, Nearly Full, and Full. In one embodiment, these signals are defined as follows:
Empty is asserted when the semaphore count equals zero.
Nearly Empty is asserted when the semaphore count is less-than or equal-to the value of the Low Watermark.
Nearly Full is asserted when the semaphore count is greater-than or equal-to the value of the High Watermark.
Full is asserted when the semaphore count equals Maximum Value.
In one embodiment, the ReadAndDecrement operation performs no function if the semaphore count equals zero prior to the decrement operation, thereby ensuring that the count never drops below zero. Likewise, the ReadAndIncrement operation optionally performs no function if the semaphore count equals Maximum Value, thereby ensuring that the count never exceeds that value. This is illustrated in row 210 of
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In one embodiment, at least part of the processes shown in
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The counting semaphores described above can be quite useful for implementing software FIFOs in network processing engines. NPEs typically contain hardware support for only a limited number of FIFOs. Although additional FIFOs could be implemented in software, there are problems with this approach.
For example, a FIFO typically has a separate “writer” (e.g., a context that writes data into the FIFO) and a “reader” (e.g., a context that reads data from the FIFO). As shown in
A counting semaphore can be used to maintain a FIFO count for a software FIFO by providing the ability to atomically increment and decrement the count. It is also very useful for the reader and writer to be able to ascertain the empty/full status of a FIFO, since the reader typically must check whether the FIFO is empty before reading from it, and the writer typically must check whether the FIFO is full before writing to it. Without an explicit count, the reader and writer will generally need to compare the read and write pointers to determine the empty/full status, and this comparison typically requires several cycles of execution time at a minimum, and thus can tangibly degrade overall data throughput. Moreover, additional processing is generally needed to determine whether the FIFO is full or empty when the read and write pointers are equal, resulting in further performance degradation.
The counting semaphores can be used to solve some or all of the problems described above. In addition to enabling the maintenance of an atomic FIFO count, counting semaphores can provide convenient status and signaling capability, which is otherwise typically infeasible in a software-only FIFO implementation. In some embodiments, the reader and writer contexts can read and/or test the semaphore status for the Empty, Nearly Empty, Nearly Full, and Full conditions. These conditions could also be used for signaling the reader and writer contexts. For example, the FIFO reader could use the Full condition as a signal to read the FIFO, and the FIFO writer could use the Empty condition as a signal to write more data.
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Network processing engine 900 will also typically include one or more interfaces 914, 916, 918 for communicating with other devices and/or networks. For example, network processing engine 900 may include an AHB bus interface 918 for communicating with a larger network processing chip, one or more high-speed serial ports 916 for communicating using serial bit stream protocols such as T1 and E1, one or more Media Independent Interfaces 914 for interfacing with, e.g., Ethernet networks, and/or the like. One or more internal buses 909 are also provided to facilitate communication between the various components of the system.
Network processing engine 900 also includes hardware and/or software for implementing the counting semaphore functionality described above. For example, the processes shown in
One of ordinary skill in the art will appreciate that the systems and methods described herein can be practiced with devices and architectures that lack many of the components and features shown in
While various embodiments are described and illustrated herein, it will be appreciated that they are merely illustrative, and that modifications can be made to these embodiments. Thus, the concepts and methodologies presented herein are intended to be defined only in terms of the following claims.
