Patent Application
20190052109
The present invention relates to a system and method for maintaining a synchronized state of charge of a plurality of parallel interconnected independent battery packs.
Parallel connected battery packs are known to provide power to loads with relatively high amp-hour requirements. It is important with parallel connected batteries that the charge of each of the batteries be the same. Otherwise, the charge imbalance will result in batteries with high charge levels having a higher voltage than batteries with low charge levels. This voltage difference will cause extremely large surges of energy to flow from the batteries at high charge levels to the batteries with low charge levels. Thus, it is important that the batteries be balanced before being connected in parallel.
Known lithium battery packs include an integrated protection circuit. The protection circuit provides protection of the cells within the battery pack against certain anomalies, such as over-current, over-voltage and over-temperature. When multiple lithium ion battery packs are connected in parallel, an anomaly in one of the battery packs normally results in that battery pack being taken off-line, i.e. interrupting its power flow path, by its protection circuit. When initially balanced batteries are connected in parallel, the disruption of energy flow from a battery that is off-line will result in an imbalance with all the other parallel connected batteries, as the other parallel connected batteries continue their energy flow. This imbalance worsens in time as the other parallel connected batteries continue to flow energy while the off-line pack does not flow energy.
In such a situation, it is necessary to prevent the off-line battery pack from coming back on line since it will not be balanced with the rest of batteries connected in parallel. To ensure charge balance, the off-line battery pack should not be allowed to come back on-line until the other parallel connected batteries are either charged or discharged to the charge level of the off-line battery.
Various methods are known for equalizing the charge among battery cells connected in parallel. For example, Korean patent KR101634012 B1 discloses a method for balancing the charge in a plurality of parallel interconnected batteries. Upon an event that causes the charge in one or more parallel interconnected batteries to be depleted and therefore unbalanced relative to the other batteries, the disclosed charge balance methodology is based upon leaving all batteries connected and allowing the batteries with higher charge levels to equalize the charge of batteries with lower charge levels.
There are several problems associated with the system disclosed in the Korean patent. One problem relates to the fact that the battery cell initiating the event is not taken off-line to preserve the charge levels of the other parallel interconnected batteries. Another problem is that the charge control of the batteries is under the control of a separate battery management system (BMS) controller that is external to the battery packs. Such external controllers are expensive and add to the complexity of the system. Battery management systems that utilize external controllers are generally not modular and are not generally scalable which requires the need for customized battery charge control systems.
Other systems are known which utilize BMS that are external to a modular battery solution. For example, Valence Technology, Inc (www.valence.com) provides BMS that are configured for external use. (see www.valence.com/products/standard-modules/xp-module/). Also, U.S. Pat. No. 8,324,868 illustrates an application in which battery charge control is under the control of an external BMS.
Thus, there is a need for a control system capable of solving problems associated with the charge control of a plurality of parallel interconnected battery packs which can synchronize the charge levels of all interconnected battery packs without the need for an external battery management system controller and thereby provide a modular and scalable solution.
Briefly, the present invention relates to a method and system for maintaining a synchronized state of charge of a plurality of independent parallel interconnected battery packs. The novel system is modular and scalar and relies on an embedded BMS in each battery pack for operation, thus eliminating the need for an external BMS. The embedded BMS has dual functions. One function is to work in conjunction with known battery pack protection systems for providing various safety functions, such as, over-current, over-voltage and over-temperature protection. The other function of the BMS relates to maintaining a synchronized charge among the interconnected battery packs.
Three circuits are provided within each battery pack, including a monitoring circuit, a protection circuit and a signaling circuit. The signaling circuit includes a shared status line connected to all interconnected paralleled battery packs. The shared status line is connected to a Monitor input port on the BMS, and is pulled-up to a high-logic voltage level (such as 3.3V) through a resistor. The monitoring circuit alerts the embedded BMS of changes in the logic level of the shared status line. When a change in the logic level of the shared status signal is sensed by the BMS, representing that a safety condition has been encountered, such as over-voltage, over-current, or over-temperature or the battery pack has been taken off-line manually, the battery is taken off-line by the protection circuit under the control of the BMS. The BMS simultaneously generates a high Alert signal at its output port. The logic level of the Alert signal is provided as an input to a signal circuit which is capable of changing the state of a status signal shared by all interconnected battery packs. The monitoring circuit within each battery pack senses the change of the shared status signal, informing the embedded BMS to trip its protection circuit and similarly take each parallel connected battery pack offline. When the issue with the initiating battery pack is resolved, the embedded BMS of the initiating battery pack releases its respective protection circuit allowing its battery pack to come back on-line and simultaneously resets the Alert signal which allows the shared status signal to return to a high-logic level. The monitoring circuits of the interconnected battery packs sense the restored logic state of the shared status line, and their embedded BMS releases their respective protection circuits to allow each interconnected battery packs to come back online. This method of control allows energy flow to remain synchronized between all parallel interconnected battery packs, without the need for an external “master” BMS. Further, this method of control allows each individual battery to remain entirely functional both parallel and single applications, without the need for any hardware or firmware adjustments to the individual battery, nor any other customization.
These and other advantages of the present invention will be readily understood with reference to the following specification and attached drawing wherein:
The present invention relates to a method and system for maintaining a synchronized state of charge of a plurality of independent parallel interconnected battery packs. The system includes a monitoring circuit, a protection circuit and a signaling circuit that work in conjunction with an embedded Battery Management System (BMS) in each of the interconnected battery packs.
The signaling circuit may include one or more shared status lines that are connected to all parallel connected battery packs to indicate an anomaly with one of the interconnected battery packs. In lieu of a status line, the signaling circuit may be formed as a communication bus for communicating information in digital packetized form, for example, SPI, UART, I2C, CAN, Ethernet or other protocols, between battery packs or other battery systems and/or a remote server. The signaling circuit may also be formed as a series of dedicated signal lines, each intended to signal a specific status, such as over-charge, over-discharge, over-temperature, or other distinct statuses. The signaling circuit may alternately include wireless communication links, incorporating Bluetooth or Near Field Communication (NFC) technology. Alternately, the signaling circuit may be formed as an optical link that includes LEDs, optical receivers, for example, photo transistors and optical fiber connected among the BMS. All such communication systems are well known and within the ordinary skill in the art.
The signaling circuit provides indication to all interconnected battery packs by way of a shared status line to communicate when one or more of the interconnected batteries are off line. The shared status line is monitored by the BMS by way of a monitor circuit in each battery pack to inform the battery packs of the status of all other battery packs. In a normal mode of operation, i.e. when all battery packs are on-line and their respective charge levels are synchronized, the shared status line is high. If an anomaly is detected in any one of the interconnected battery packs, i.e. one of the battery pack is off-line, the embedded BMS of the initiating off-line battery pack transitions the logic level of its Alert output, causing the signaling circuit to pull the shared status line low. The low shared status line is monitored by all interconnected battery packs causing them to be taken off-line by their respective BMS. Once the issue is resolved in the initiating battery pack, the BMS of the initiating battery pack releases its respective protection circuit to allow the battery pack to come back on-line and also resets its Alert output, which resets the signaling circuit and allows the shared status line to return to a normal low state. The monitoring circuits of the other interconnected battery packs will sense this transition of the shared status line and will signal their respective BMS to release their protection circuits and similarly allow their respective battery packs to come back online.
As used herein, the term “battery pack” is to be understood to include a device that includes one or more battery modules and a protection module in a common housing. Each battery module is to be understood to include one or more battery cells 28.
An exemplary battery protection module protection module is disclosed in U.S. Pat. No. 9,450,428, hereby incorporated by reference. Such battery protection modules are known to be included in battery packs to protect the battery modules from various abnormal conditions including: over-voltage, over-current and over-temperature by taking the battery modules off-line when an abnormal condition occurs and reconnecting the battery module when the abnormal problem is resolved.
Referring to
The embedded BMS 28 may be implemented as one or more integrated circuits, for example, Model No.bq40z50-R1, manufactured by Texas Instruments. The BMS 28 may be connected to a current sensor 35, a temperature sensor 37 and a voltage sensor (not shown) for providing over-current, over-temperature and over-voltage protection, respectively. The BMS 28 also controls the protection circuitry 42, 44 which automatically takes the battery packs 22, 24 and 26 off-line, i.e. interrupting energy flow when an anomaly occurs, and enabling the battery packs 22, 24 and 26 to be brought back on line when the anomaly is resolved.
The system and method disclosed herein is implemented with a monitoring circuit 30 for detecting anomalies in one or more battery packs 22, 24 and 26, a protection circuit 32 for controlling the energy flow from the battery packs 22, 24 and 26 and a signaling circuit 33 for alerting the battery packs 22, 24 and 26 when one or more battery packs 22, 24 and 26 are off-line.
The monitoring circuit 30 includes a pair of resistors R1 and R2, a pair of diodes D1 and D2, and a voltage reference, such as a 3.3V TTL reference 14. The protection circuit 32 includes a switch 42 and a switch 44. The signaling circuit 33 includes a shared status line 34 connected to all interconnected battery packs 22, 24 and 26, which it controls following an Alert signal output from the BMS 28. The signaling circuit also includes a transistor Q1 and a pair resistors R3 and R4. The shared status line 34 from the signaling circuit 33 is connected to an input port of the BMS 28 by means of the monitoring circuit 30 in each respective battery pack 22, 24 and 26. During normal conditions, the shared status line 34 is conditioned by the monitoring circuit 30 and pulled high, i.e. logical 1, by way of a voltage pull up resistor R1, a diode D1 and a pull-up voltage 14, for example, 3.3 volts DC. The logical “1” is applied to an input port on the BMS 28 by way of a resistor R2 and diode D2. During a normal condition, the diodes D1 and D2 are forward biased, thereby applying a logical “1” to the “monitor” input of the BMS 28. During this condition, the BMS 28 reads the logical “1” at its “monitor” input and assumes that no abnormal conditions exist, i.e. that all battery packs 22, 24 and 26 are on-line. An alert signal available at an output port of the BMS 28 is inactive during this condition.
The protection circuit 32 includes an over-current sensor 35, an over-temperature sensor 37 and an over-voltage sensor (not shown), connected to the BMS 28 and the switches 42 and 44. The switches 42, 44 are under the control of the BMS 28. When the BMS detects a safety condition and must terminate energy flow, or a battery pack 22, 24 or 26 is otherwise manually taken off line, the BMS 28 will control the switches 42,44 to disable energy flow and take the initiating battery pack off-line. When the safety condition is resolved, or the battery pack 22, 2426 is brought on-line manually, the BMS 28 will signal the switches 42, 44 to bring the battery pack back online, thereby restoring the energy flow path.
The signaling circuit 33 includes a shared status line 34 that is connected to all interconnected battery packs 22, 24 and 26. The signaling signal 33 also includes a transistor Q1 and a pair resistors R3 and R4. The transistor Q1 may be, for example, an n-channel enhance mode field effect transistor (FET) Q1. The drain and source terminals of the FET are connected between the “shared status” line 34 and battery ground. Since the ground path is not interrupted by the protection circuits 42,44, the battery ground provides a stable reference for the open collector TTL output port of the BMS 28 for signal coherence. Alternatively in applications where the ground path is interrupted, the positive battery voltage rail may be used as a stable TTL signal reference. In such an application, the logic signals will be similarly inverted and an alternative control device, such as an p-channel enhance mode field effect transistor, may be used. The gate terminal of the transistor Q1 is connected to an output port of the BMS 28 defining an Alert signal. During normal conditions, the Alert signal is inactive and is low. The low Alert signal is applied to the gate of the transistor Q1 to maintain the transistor Q1 in an open position.
When any one of the battery packs 22, 24 and 26 is off-line, either automatically as a result of the protection circuitry or manually, the BMS 28 causes the Alert signal to become active to cause the transistor Q1 to close. When the transistor Q1 closes, the shared status line 34 of the initiating battery pack 22, 24 and 26 is connected to ground, thus resulting in its Monitor signal at the input port of its BMS 28 going low. Since all interconnected battery packs 22, 24 and 26 monitor the shared status line, all interconnected battery packs 22, 24 and 26 are alerted of the anomaly. As a result, their respective BMS 28 will cause their respective switches 42,44 (
When the issue relating to the initiating battery pack 22, 24 and 26 is resolved, its BMS 28 will cause the Alert signal to go low which causes the transistor Q1 to open, thereby disconnecting the shared status line from ground. Once the shared status line is disconnected from ground, the Monitor signal will be pulled high by the pull-up voltage 14, resistors R1 and R2 and the diodes D1 and D2. The high Monitor signal at the BMS input port is applied to the monitor input port of all BMS 28 of the interconnected battery packs 22, 24 and 26 by way of the shared status line 34. The high Monitor signal causes all interconnected battery packs 22, 24 and 26 to be placed back on line by way of the switches 42,44.
A state diagram of the system described above is illustrated in
Obviously, many modifications and variations of the present invention are possible in light of the above teachings. Thus, it is to be understood that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described above.
